11. JTAG Boundary-Scan Testing in Stratix V Devices

Transcription

1 ecember 2 SV JTAG Boundary-Scan Testing in Stratix V evices SV52-.4 This chapter describes the boundary-scan test (BST) features that are supported in Stratix V devices. Stratix V devices support IEEE Std. 49. and IEEE Std The IEEE Std is only supported on the high-speed serial interface (HSSI) transceivers in Stratix V devices. IEEE Std enables board-level connectivity checking between transmitters and receivers that are AC coupled (connected with a capacitor in series between the source and destination). This chapter includes the following sections: IEEE Std Boundary-Scan Register on page 2 BST Operation Control on page 3 I/O Voltage Support in a JTAG Chain on page 5 Boundary-Scan escription Language Support on page 6 f For more information about the following IEEE Std. 49. BST features, refer to the IEEE 49. (JTAG) Boundary-Scan Testing in Stratix III evices chapter in volume of the Stratix III evice Handbook: IEEE Std. 49. BST architecture and circuitry IEEE Std. 49. boundary-scan register IEEE Std. 49. BST guidelines Test access port (TAP) controller state-machine 2 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARCOPY, MAX, MEGACORE, NIOS, UARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. ISO 9:28 Registered Stratix V evice Handbook Volume 2: evice Interfaces and Integration ecember 2 Subscribe

2 2 Chapter : JTAG Boundary-Scan Testing in Stratix V evices IEEE Std Boundary-Scan Register IEEE Std Boundary-Scan Register The boundary-scan cells (BSCs) for HSSI transmitters (GXB_TX[p,n]) and receivers/input clock buffer (GXB_RX[p,n])/(REFCLK[p,n]) in Stratix V devices are different from the BSCs for the I/O pins. Figure shows the Stratix V HSSI transmitter BSC. Figure. HSSI Transmitter BSC with IEEE Std BST Circuitry for Stratix V evices BSCAN PMA SOUT BSTX OE AC JTAG Output BSOEB Mission (ATAOUT) TX_BUF_OE noe Tx Output MORHZ OE Logic ACJTAG_BUF_OE MEM_INIT SIN SHIFT CLK UPATE HIGHZ AC_TEST MOE AC_MOE BSTX OE AC JTAG Output Capture Update Registers Figure 2 shows the Stratix V HSSI receiver/input clock buffer BSC. Figure 2. HSSI Receiver/Input Clock BSC with IEEE Std BST Circuitry for Stratix V evices BSCAN PMA SOUT BSRX AC JTAG Test Receiver BSOUT Hysteretic Memory Mission (ATAIN) Optional INTEST/RUNBIST not supported Rx Input BSRX BSOUT Hysteretic Memory AC JTAG Test Receiver HIGHZ SIN SHIFT CLK UPATE AC_TEST MOE MEM_INIT AC_MOE Capture Update Registers Stratix V evice Handbook ecember 2 Altera Corporation Volume 2: evice Interfaces and Integration

3 Chapter : JTAG Boundary-Scan Testing in Stratix V evices 3 BST Operation Control BST Operation Control Table lists the ICOE information for Stratix V devices. Table. 32-Bit ICOE Information for Stratix V evices Preliminary Family Stratix V GX Stratix V GT Stratix V GS Stratix V E evice Version (4 Bits) Part Number (6 Bits) ICOE (32 Bits) () Manufacturer Identity ( Bits) LSB ( Bit) (2) 5SGXA3 5SGXA4 5SGXA5 5SGXA7 5SGXA9 5SGXAB 5SGXB5 5SGXB6 5SGTC5 5SGTC7 5SGS3 5SGS4 5SGS5 5SGS6 5SGS8 5SEE9 5SEEB Notes to Table : () The MSB is on the left. (2) The LSB of the ICOE is always. Table 2 lists the JTAG instructions that are supported by Stratix V devices. Table 2. JTAG Instruction Supported by Stratix V evices (Part of 2) JTAG Instruction Instruction Code escription SAMPLE/PRELOA EXTEST () BYPASS USERCOE Allows a snapshot of signals at the device pins to be captured and examined during normal device operation and permits an initial data pattern to be an output at the device pins. Also used by the SignalTap II Embedded Logic Analyzer. Allows the external circuit and board-level interconnects to be tested by forcing a test pattern at the output pins and capturing test results at the input pins. Places the -bit bypass register between the TI and TO pins, allowing the BST data to pass synchronously through selected devices to adjacent devices during normal device operation. Selects the 32-bit USERCOE register and places it between the TI and TO pins, allowing USERCOE to be serially shifted out of TO. ecember 2 Altera Corporation Stratix V evice Handbook Volume 2: evice Interfaces and Integration

4 4 Chapter : JTAG Boundary-Scan Testing in Stratix V evices BST Operation Control Table 2. JTAG Instruction Supported by Stratix V evices (Part 2 of 2) JTAG Instruction Instruction Code escription ICOE HIGHZ () CLAMP () PULSE_NCONFIG CONFIG_IO LOCK Selects the ICOE register and places it between the TI and TO pins, allowing ICOE to be serially shifted out of TO. ICOE is the default instruction at power up and in the TAP RESET state. Places the -bit bypass register between the TI and TO pins, allowing the BST data to pass synchronously through selected devices to adjacent devices during normal device operation while tri-stating all of the I/O pins. Places the -bit bypass register between the TI and TO pins, allowing the BST data to pass synchronously through selected devices to adjacent devices during normal device operation while holding I/O pins to a state defined by the data in the boundary-scan register. Emulates pulsing the nconfig pin low to trigger reconfiguration even though the physical pin is unaffected. Allows I/O reconfiguration through JTAG ports using IOCSR for JTAG testing. This is executed after or during configurations. The nstatus pin must go high before you can issue the CONFIG_IO instruction. isables the access by JTAG instructions and places the device into JTAG secure mode. UNLOCK Enables access for JTAG instructions that are not disabled by security fuses. KEY_CLR_VREG Clears the non-volatile key. KEY_VERIFY Verifies the non-volatile key has been cleared. EXTEST_PULSE EXTEST_TRAIN Note to Table 2: Enables board-level connectivity checking between the transmitters and receivers that are AC coupled by generating three output transitions: river drives data on the falling edge of TCK in the UPATE_IR/R state. river drives inverted data on the falling edge of TCK after entering the RUN_TEST/ILE state. river drives data on the falling edge of TCK after leaving the RUN_TEST/ILE state. Behaves the same as the EXTEST_PULSE instruction except that the output continues to toggle on the TCK falling edge as long as the TAP controller is in the RUN_TEST/ILE state. () Bus hold and weak pull-up resistor features override the high-impedance state of HIGHZ, CLAMP, and EXTEST. If any of the security fuses is blown, some of the JTAG instructions are disabled. UNLOCK instruction enables the JTAG instructions that are not blocked by these fuses. LOCK instruction disables these JTAG instructions, returning to the JTAG secure state. You can only issue the LOCK or UNLOCK instruction from the JTAG core access. The ICOE instruction is the default instruction when the TAP controller is in the reset state. Without loading any instructions, you can go to the SHIFT_R state and shift out the JTAG device I. Stratix V evice Handbook ecember 2 Altera Corporation Volume 2: evice Interfaces and Integration

5 Chapter : JTAG Boundary-Scan Testing in Stratix V evices 5 I/O Voltage Support in a JTAG Chain If the device is in reset state, when the nconfig or nstatus signal is low, the device ICOE might not be read correctly. To read the device ICOE correctly, you must issue the ICOE JTAG instruction only when the nconfig and nstatus signals are high. IEEE Std mandates the addition of two new instructions EXTEST_PULSE and EXTEST_TRAIN. These two instructions enable edge-detecting behavior on the signal path containing the HSSI pins. These instructions implement new test behaviors for the HSSI pins and simultaneously behave identically to the IEEE Std. 49. EXTEST instruction for non-hssi pins. If you use C coupling on the HSSI signals, execute the EXTEST instruction. If you use AC coupling on the HSSI signals, execute the EXTEST_PULSE instruction. I/O Voltage Support in a JTAG Chain A device operating in BST mode uses four required pins TI, TO, TMS, TCK, and one optional pin, TRST. The TCK pin has an internal weak pull-down resistor, while the TI, TMS, and TRST pins have internal weak pull-up resistors. The TO output pin and all the JTAG input pins are powered by the 2.5-V/3.-V V CCP supply of I/O bank 3A. All user I/O pins are tri-stated during JTAG configuration. The JTAG chain can support several different devices. However, use caution if the chain contains devices that have different V CCIO levels. The output voltage level of the TO pin must meet the specification of the TI pin it drives. Table 3 lists board design recommendations to ensure proper JTAG chain operation. Table 3. Supported TO and TI Voltage Combinations Stratix V evice Non-Stratix V TI Input Power Stratix V TO V CCP V CCP = 3. V () V CCP = 2.5 V (2) V CCP = 3. V v v V CCP = 2.5 V v v V CC = 3.3 V v (3) v (4) V CC = 2.5 V v (3) v (4) V CC =.8 V v (3) v (4) V CC =.5 V v (3) v (4) Notes to Table 3: () The TO output buffer meets V OH (MIN) = 2.4 V. (2) The TO output buffer meets V OH (MIN) = 2. V. (3) Input buffer must be 3.-V tolerant. (4) Input buffer must be 2.5-V tolerant. ecember 2 Altera Corporation Stratix V evice Handbook Volume 2: evice Interfaces and Integration

6 6 Chapter : JTAG Boundary-Scan Testing in Stratix V evices Boundary-Scan escription Language Support Boundary-Scan escription Language Support The boundary-scan description language (BSL), a subset of VHL, provides a syntax that allows you to describe the features of an IEEE Std BST-capable device that can be tested. You can test software development systems, then use the BSL files for test generation, analysis, and failure diagnostics. f f For more information about BSL files for IEEE Std compliant Stratix V devices, refer to the IEEE 49.6 BSL Files page on the Altera website. You can also generate BSL files (pre-configuration and post-configuration) for IEEE Std compliant Stratix V devices with the uartus II software version. SP and later. For more information about the procedure to generate BSL files using the uartus II software, refer to the BSL Files Generation in II page on the Altera website. ocument Revision History Table 4. ocument Revision History Table 4 lists the revision history for this chapter. ate Version Changes ecember 2.4 Updated Table 2 to include KEY_CLR_VREG and KEY_VERIFY JTAG instructions. November 2.3 Updated Table and Table 2. May 2.2 Chapter moved to volume 2 for the. release. Updated Table. ecember 2. No changes to the content of this chapter for the uartus II software.. July 2. Initial release. Stratix V evice Handbook ecember 2 Altera Corporation Volume 2: evice Interfaces and Integration