KAI-4021 IMAGE SENSOR 2048 (H) X 2048 (V) INTERLINE CCD IMAGE SENSOR JUNE 9, 2014 DEVICE PERFORMANCE SPECIFICATION REVISION 1.

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1 KAI-4021 IMAGE SENSOR 2048 (H) X 2048 (V) INTERLINE CCD IMAGE SENSOR JUNE 9, 2014 DEVICE PERFORMANCE SPECIFICATION REVISION 1.1 PS-0014

2 TABLE OF CONTENTS Summary Specification... 6 Description... 6 Features... 6 Applications... 6 Ordering Information... 7 Device Description... 8 Architecture... 8 Pixel... 9 Vertical to Horizontal Transfer Horizontal Register to Floating Diffusion Horizontal Register Split Single Output Operation Dual Output Operation Output ESD Protection Pin Description and Physical Orientation Imaging Performance Typical Operational Conditions Specifications All Configurations KAI-4021-ABA Configuration KAI-4021-CBA-Configuration Typical Performance Curves Quantum Efficiency Monochrome with Microlens Monochrome without Microlens Color (Bayer RGB) with Microlens Angular Quantum Efficiency Monochrome with Microlens Dark Current versus Temperature Power - Estimated Frame Rates Defect Definitions Defect Map Test Definitions Test Regions of Interest OverClocking Tests Dark Field Center Non-Uniformity Dark Field Global Non-Uniformity Global Non-Uniformity Global Peak to Peak Non-Uniformity Center Non-Uniformity Dark Field Defect Test Bright Field Defect Test Operation Maximum Ratings Maximum Voltage Ratings Between Pins Revision 1.1 PS-0014 Pg 2

3 DC Bias Operating Conditions AC Operating Conditions Clock Levels Clock Line Capacitances Timing Requirements Timing Modes Progressive Scan Summed Interlaced Scan Non-Summed Interlaced Scan Frame Timing Frame Timing without Binning Progressive Scan Frame Timing for Vertical Binning by 2 Progressive Scan Frame Timing Non-Summed Interlaced Scan (Even) Frame Timing Non-Summed Interlaced Scan (Odd) Frame Timing Summed Interlaced Scan (Even) Frame Timing Summed Interlaced Scan (Odd) Frame Timing Edge Alignment Line Timing Line Timing Single Output Progressive Scan Line Timing Dual Output Progressive Scan Line Timing Vertical Binning by 2 Progressive Scan Line Timing Detail Progressive Scan Line Timing Binning by 2 Detail Progressive Scan Line Timing Interlaced Modes Line Timing Edge Alignment Pixel Timing Pixel Timing Detail Fast Line Dump Timing Electronic Shutter Electronic Shutter Line Timing Electronic Shutter Integration Time Definition Electronic Shutter Description Large Signal Output Storage and Handling Storage Conditions ESD Cover Glass Care and Cleanliness Environmental Exposure Soldering Recommendations Mechanical Information Completed Assembly Die to Package Alignment Glass Glass Transmission Quality Assurance and Reliability Quality and Reliability Replacement Liability of the Supplier Liability of the Customer Test Data Retention Revision 1.1 PS-0014 Pg 3

4 Mechanical Life Support Applications Policy Revision Changes MTD/PS PS Revision 1.1 PS-0014 Pg 4

5 TABLE OF FIGURES Figure 1: Block Diagram... 8 Figure 2: Pixel Architecture... 9 Figure 3: Vertical to Horizontal Transfer Architecture Figure 4: Horizontal Register to Floating Diffusion Architecture Figure 5: Horizontal Register Figure 6: Output Architecture Figure 7: ESD Protection Figure 8: Package Pin Designations - Top View Figure 9: Monochrome with Microlens Quantum Efficiency Figure 10: Monochrome without Microlens Quantum Efficiency Figure 11: Color Quantum Efficiency Figure 12: Monochrome with Microlens Angular Quantum Efficiency Figure 13: Dark Current versus Temperature Figure 14: Power Figure 15: Frame Rates Figure 16: Overclock Regions of Interest Figure 17: Output Amplifier Figure 18: Clock Line Capacitances Figure 19: Progressive Scan Operation Figure 20: Progressive Scan Flow Chart Figure 21: Summed Interlaced Scan Operation Figure 22: Summed Interlaced Scan Flow Chart Figure 23: Non- Summed Interlaced Scan Operation Figure 24: Non- Summed Interlaced Scan Flow Chart Figure 25: Framing Timing without Binning Figure 26: Frame Timing for Vertical Binning by Figure 27: Non-Summed Interlaced Scan Even Frame Timing Figure 28: Non-Summed Interlaced Scan Odd Frame Timing Figure 29: Summed Interlaced Scan Even Frame Timing Figure 30: Summed Interlaced Scan Odd Frame Timing Figure 31: Frame Timing Edge Alignment Figure 32: Line Timing Single Output Figure 33: Line Timing Dual Output Figure 34: Line Timing Vertical Binning by Figure 35: Line Timing Detail Figure 36: Line Timing by 2 Detail Figure 37: Line Timing Interlaced Modes Figure 38: Line Timing Edge Alignment Figure 39: Pixel Timing Figure 40: Pixel Timing Detail Figure 41: Fast Line Dump Timing Figure 42: Electronic Shutter Line Timing Figure 43: Integration Time Definition Figure 44: Completed Assembly Figure 45: Die to Package Alignment Figure 46: Glass Drawing Figure 47: Glass Transmission Revision 1.1 PS-0014 Pg 5

6 Summary Specification KAI-4021 Image Sensor DESCRIPTION The KAI-4021 Image Sensor is a high-performance 4- million pixel sensor designed for a wide range of medical, scientific and machine vision applications. The 7.4 μm square pixels with microlenses provide high sensitivity and the large full well capacity results in high dynamic range. The two high-speed outputs and binning capabilities allow for frames per second (fps) video rate for the progressively scanned images. The vertical overflow drain structure provides antiblooming protection and enables electronic shuttering for precise exposure control. Other features include low dark current, negligible lag and low smear. FEATURES High resolution High sensitivity High dynamic range Low noise architecture High frame rate Binning capability for higher frame rate Electronic shutter APPLICATIONS Intelligent Transportation Systems Machine Vision Scientific Parameter Architecture Total Number of Pixels Number of Effective Pixels Number of Active Pixels Value Number of Outputs 1 or 2 Pixel Size Imager Size Chip Size Aspect Ratio 1:1 Interline CCD; Progressive Scan Saturation Signal 40,000 e - Peak Quantum Efficiency KAI-4021-ABA KAI-4021-CBA (BRG) 2112 (H) x 2072 (V) = approx. 4.38M 2056 (H) x 2062 (V) = approx. 4.24M 2048 (H) x 2048 (V) = approx. 4.19M 7.4 μm (H) x 7.4 μm (V) 21.43mm (diagonal) 16.67mm (H) x 16.05mm (V) 55% 45%, 42%, 35% Output Sensitivity 31 μv/e - Total System Noise (at 40MHZ) 25 e - Total System Noise (at 20MHz) 12 e - Dark Current < 0.5 na/cm 2 Dark Current Doubling Temperature 7 C Dynamic Range 60 db Charge Transfer Efficiency > Blooming Suppression Smear 300X 80 db Image Lag <10 e - Maximum Data Rate 40 MHz All parameters above are specified at T = 40 C Revision 1.1 PS-0014 Pg 6

7 Ordering Information Catalog Number 4H0667 4H0668 4H0669 4H0670 4H0671 4H0672 4H0674 4H0675 4H0709 4H0710 4H0696 Product Name Description Marking Code KAI-4021-AAA-CR-BA KAI-4021-AAA-CR-AE KAI-4021-ABA-CD-BA KAI-4021-ABA-CD-AE KAI-4021-ABA-CR-BA KAI-4021-ABA-CR-AE KAI-4021-CBA-CD-BA KAI-4021-CBA-CD-AE KAI-4021-CBA-CR-BA KAI-4021-CBA-CR-AE KEK-4H0696-KAI-4011/ Monochrome, No Microlens, CERDIP Package (sidebrazed), Taped Clear Cover Glass with AR coating (2 sides), Standard Grade Monochrome, No Microlens, CERDIP Package (sidebrazed), Taped Clear Cover Glass with AR coating (2 sides), Engineering Sample Monochrome, Telecentric Microlens, CERDIP Package (sidebrazed), Clear Cover Glass with AR coating (both sides), Standard Grade Monochrome, Telecentric Microlens, CERDIP Package (sidebrazed), Clear Cover Glass with AR coating (both sides), Engineering Sample Monochrome, Telecentric Microlens, CERDIP Package (sidebrazed), Taped Clear Cover Glass with AR coating (2 sides), Standard Grade Monochrome, Telecentric Microlens, CERDIP Package (sidebrazed), Taped Clear Cover Glass with AR coating (2 sides), Engineering Sample Color (Bayer RGB), Telecentric Microlens, CERDIP Package (sidebrazed), Clear Cover Glass with AR coating (both sides), Standard Grade Color (Bayer RGB), Telecentric Microlens, CERDIP Package (sidebrazed), Clear Cover Glass with AR coating (both sides), Engineering Sample Color (Bayer RGB), Telecentric Microlens, CERDIP Package (sidebrazed), Taped Clear Cover Glass with AR coating (both sides), Standard Grade Color (Bayer RGB), Telecentric Microlens, CERDIP Package (sidebrazed), Taped Clear Cover Glass with AR coating (both sides), Engineering Grade Evaluation Board (Complete Kit) KAI-4021 S/N KAI-4021M S/N KAI-4021CM S/N n/a See Application Note Product Naming Convention for a full description of the naming convention used for image sensors. For reference documentation, including information on evaluation kits, please visit our web site at Please address all inquiries and purchase orders to: Truesense Imaging, Inc Lake Avenue Rochester, New York Phone: (585) info@truesenseimaging.com ON Semiconductor reserves the right to change any information contained herein without notice. All information furnished by ON Semiconductor is believed to be accurate. Revision 1.1 PS-0014 Pg 7

8 12 Dummy Pixels 12 Dummy Pixels 28 Dark Columns 4 4Buffer Columns Rows 4 Buffer Columns 28 Dark Columns KAI-4021 Image Sensor Device Description ARCHITECTURE B G G R 8 Buffer Rows B G G R B G G R B G G R 2048 (H) x 2048 (H) Active Pixels G R Pixel 1,1 B G B G G R Video L B G G R 6 Buffer Rows 10 Dark Rows B G G R Video R Single or Dual Output Figure 1: Block Diagram There are 10 light shielded rows followed 2062 photoactive rows. The first 6 and the last 8 photoactive rows are buffer rows giving a total of 2048 lines of image data. In the single output mode all pixels are clocked out of the Video L output in the lower left corner of the sensor. The first 12 empty pixels of each line do not receive charge from the vertical shift register. The next 28 pixels receive charge from the left light-shielded edge followed by 2056 photo-sensitive pixels and finally 28 more light shielded pixels from the right edge of the sensor. The first and last 4 photosensitive pixels are buffer pixels giving a total of 2048 pixels of image data. In the dual output mode the clocking of the right half of the horizontal CCD is reversed. The left half of the image is clocked out Video L and the right half of the image is clocked out Video R. Each row consists of 12 empty pixels followed by 28 light shielded pixels followed by 1028 photosensitive pixels. When reconstructing the image, data from Video R will have to be reversed in a line buffer and appended to the Video L data. There are no dark reference rows at the top and 10 dark rows at the bottom of the image sensor. The 10 dark rows are not entirely dark and so should not be used for a dark reference level. Use the 28 dark columns on the left or right side of the image sensor as a dark reference. Of the 28 dark columns, the first and last dark columns should not be used for determining the zero signal level. Some light does leak into the first and last dark columns. Only use the center 26 columns of the 28 column dark reference. Revision 1.1 PS-0014 Pg 8

9 PIXEL Top View Direction of Charge Transfer Photodiode Transfer Gate V1 V2 7.4 m Cross Section Down Through VCCD V1 V2 V1 n- n- n- n p Well (GND) Direction of Charge Transfer 7.4 m True Two Phase Burried Channel VCCD Lightshield over VCCD not shown n Substrate Photo diode Cross Section Through Photodiode and VCCD Phase 1 Light Shield V1 Cross Section Through Photodiode and VCCD Phase 2 at Transfer Gate Transfer Gate Light Shield V2 p p+ n p n p p p p+ n n p p p p n Substrate n Substrate Cross Section Showing Lenslet Drawings not scale Lenslet Red Color Filter Light Shield VCCD Photodiode Light Shield VCCD Figure 2: Pixel Architecture An electronic representation of an image is formed when incident photons falling on the sensor plane create electronhole pairs within the individual silicon photodiodes. These photoelectrons are collected locally by the formation of potential wells at each photosite. Below photodiode saturation, the number of photoelectrons collected at each pixel is linearly dependent upon light level and exposure time and non-linearly dependent on wavelength. When the photodiodes charge capacity is reached, excess electrons are discharged into the substrate to prevent blooming. Revision 1.1 PS-0014 Pg 9

10 VERTICAL TO HORIZONTAL TRANSFER Direction of Vertical Charge Transfer Top View Photo diode Transfer Gate V1 V2 V1 Fast Line Dump V2 Lightshield not shown H 1 B H2 S H 2 B H1S Direction of Horizontal Charge Transfer Figure 3: Vertical to Horizontal Transfer Architecture When the V1 and V2 timing inputs are pulsed, charge in every pixel of the VCCD is shifted one row towards the HCCD. The last row next to the HCCD is shifted into the HCCD. When the VCCD is shifted, the timing signals to the HCCD must be stopped. H1 must be stopped in the high state and H2 must be stopped in the low state. The HCCD clocking may begin T HD µs after the falling edge of the V1 and V2 pulse. Charge is transferred from the last vertical CCD phase into the H1S horizontal CCD phase. Refer to Figure 35 for an example of timing that accomplishes the vertical to horizontal transfer of charge. If the fast line dump is held at the high level (FDH) during a vertical to horizontal transfer, then the entire line is removed and not transferred into the horizontal register. Revision 1.1 PS-0014 Pg 10

11 HORIZONTAL REGISTER TO FLOATING DIFFUSION RD R OG H2S H2B H1S H1B H2S H2B H1S n+ n n+ n- n- n- n (burried channel) Floating Diffusion p (GND) n (SUB) Figure 4: Horizontal Register to Floating Diffusion Architecture The HCCD has a total of 2124 pixels. The 2112 vertical shift registers (columns) are shifted into the center 2112 pixels of the HCCD. There are 12 pixels at both ends of the HCCD, which receive no charge from a vertical shift register. The first 12 clock cycles of the HCCD will be empty pixels (containing no electrons). The next 28 clock cycles will contain only electrons generated by dark current in the VCCD and photodiodes. The next 2056 clock cycles will contain photoelectrons (image data). Finally, the last 28 clock cycles will contain only electrons generated by dark current in the VCCD and photodiodes. Of the 28 dark columns, the first and last dark columns should not be used for determining the zero signal level. Some light does leak into the first and last dark columns. Only use the center 26 columns of the 28 column dark reference. When the HCCD is shifting valid image data, the timing inputs to the electronic shutter (SUB), VCCD (V1, V2), and fast line dump (FD) should be not be pulsed. This prevents unwanted noise from being introduced. The HCCD is a type of charge coupled device known as a pseudo-two phase CCD. This type of CCD has the ability to shift charge in two directions. This allows the entire image to be shifted out to the video L output, or to the video R output (left/right image reversal). The HCCD is split into two equal halves of 1068 pixels each. When operating the sensor in single output mode the two halves of the HCCD are shifted in the same direction. When operating the sensor in dual output mode the two halves of the HCCD are shifted in opposite directions. The direction of charge transfer in each half is controlled by the H1BL, H2BL, H1BR, and H2BR timing inputs. Revision 1.1 PS-0014 Pg 11

12 HORIZONTAL REGISTER SPLIT H1 H2 H2 H1 H1 H2 H2 H1 H1 H2 H1BL H2SL H2BL H1SL H1BL H2SL H1BR H1SR H2BR H2SR Pixel 1068 Single Output Pixel 1069 H1 H2 H2 H1 H1 H2 H1 H1 H2 H2 H1BL H2SL H2BL H1SL H1BL H2SL H1BR H1SR H2BR H2SR Pixel 1068 Dual Output Pixel 1068 Single Output Operation Figure 5: Horizontal Register When operating the sensor in single output mode all pixels of the image sensor will be shifted out the Video L output (pin 12). To conserve power and lower heat generation the output amplifier for Video R may be turned off by connecting VDDR (pin 24) and VOUTR (pin 23) to GND (zero volts). The H1 timing from the timing diagrams should be applied to H1SL, H1BL, H1SR, H2BR, and the H2 timing should be applied to H2SL, H2BL, H2SR, and H1BR. In other words, the clock driver generating the H1 timing should be connected to pins 16, 15, 19, and 21. The clock driver generating the H2 timing should be connected to pins 17, 14, 18, and 20. The horizontal CCD should be clocked for 12 empty pixels plus 28 light shielded pixels plus 2056 photoactive pixels plus 28 light shielded pixels for a total of 2124 pixels. Dual Output Operation In dual output mode the connections to the H1BR and H2BR pins are swapped from the single output mode to change the direction of charge transfer of the right side horizontal shift register. In dual output mode both VDDL and VDDR (pins 11, 24) should be connected to 15 V. The H1 timing from the timing diagrams should be applied to H1SL, H1BL, H1SR, H1BR, and the H2 timing should be applied to H2SL, H2BL, H2SR, and H2BR. The clock driver generating the H1 timing should be connected to pins 16, 15, 19, and 20. The clock driver generating the H2 timing should be connected to pins 17, 14, 18, and 21. The horizontal CCD should be clocked for 12 empty pixels plus 28 light shielded pixels plus 1028 photoactive pixels for a total of 1068 pixels. If the camera is to have the option of dual or single output mode, the clock driver signals sent to H1BR and H2BR may be swapped by using a relay. Another alternative is to have two extra clock drivers for H1BR and H2BR and invert the signals in the timing logic generator. If two extra clock drivers are used, care must be taken to ensure the rising and falling edges of the H1BR and H2BR clocks occur at the same time (within 3 ns) as the other HCCD clocks. Revision 1.1 PS-0014 Pg 12

13 OUTPUT H2B H2S HCCD Charge Transfer H1B H1S H2B H2S VDD OG R RD Floating Diffusion VOUT Source Follower #1 Source Follower #2 Source Follower #3 Figure 6: Output Architecture Charge packets contained in the horizontal register are dumped pixel by pixel onto the floating diffusion (fd) output node whose potential varies linearly with the quantity of charge in each packet. The amount of potential charge is determined by the expression ΔVfd=ΔQ/Cfd. A three-stage source-follower amplifier is used to buffer this signal voltage off chip with slightly less than unity gain. The translation from the charge domain to the voltage domain is quantified by the output sensitivity or charge to voltage conversion in terms of microvolts per electron (μv/e - ). After the signal has been sampled off chip, the reset clock (R) removes the charge from the floating diffusion and resets its potential to the reset drain voltage (RD). When the image sensor is operated in the binned or summed interlaced modes there will be more than 20,000 electrons in the output signal. The image sensor is designed with a 31 µv/e - charge to voltage conversion on the output. This means a full signal of 20,000 electrons will produce a 640 mv change on the output amplifier. The output amplifier was designed to handle an output swing of 640 mv at a pixel rate of 40 MHz. If 40,000 electron charge packets are generated in the binned or summed interlaced modes then the output amplifier output will have to swing 1280 mv. The output amplifier does not have enough bandwidth (slew rate) to handle 1280 mv at 40 MHz. Hence, the pixel rate will have to be reduced to 20 MHz if the full dynamic range of 40,000 electrons is desired. The charge handling capacity of the output amplifier is also set by the reset clock voltage levels. The reset clock driver circuit is very simple, if an amplitude of 5 V is used. But the 5 V amplitude restricts the output amplifier charge capacity to 20,000 electrons. If the full dynamic range of 40,000 electrons is desired then the reset clock amplitude will have to be increased to 7 V. If you only want a maximum signal of 20,000 electrons in binned or summed interlaced modes, then a 40 MHz pixel rate with a 5 V reset clock may be used. The output of the amplifier will be unpredictable above 20,000 electrons so be sure to set the maximum input signal level of your analog to digital converter to the equivalent of 20,000 electrons (640 mv). Revision 1.1 PS-0014 Pg 13

14 The following table summarizes the previous explanation on the output amplifier s operation. Certain trade-offs can be made based on application needs such as Dynamic Range or Pixel frequency. Pixel Freq. (MHz) Reset Clock Amplitude (V) Output Gate (V) Saturation Signal (mv) Saturation Signal (ke - ) Dynamic Range (db) Notes: 1. 80,000 electrons achievable in summed interlaced or binning modes. Notes Revision 1.1 PS-0014 Pg 14

15 ESD PROTECTION D2 D2 D2 D2 D2 D2 RL H1SL H2SL H1BL H2BL OGL ESD VSUB D1 D2 D2 D2 D2 D2 D2 RR H1SR H2SR H1BR H2BR OGR Figure 7: ESD Protection The ESD protection on the KAI-4021 is implemented using bipolar transistors. The substrate (VSUB) forms the common collector of all the ESD protection transistors. The ESD pin is the common base of all the ESD protection transistors. Each protected pin is connected to a separate emitter as shown in Figure 7: ESD Protection. The ESD circuit turns on if the base-emitter junction voltage exceeds 17 V. Care must be taken while operating the image sensor, especially during the power on sequence, to not forward bias the base-emitter or base-collector junctions. If it is possible for the camera power up sequence to forward bias these junctions then diodes D1 and D2 should be added to protect the image sensor. Put one diode D1 between the ESD and VSUB pins. Put one diode D2 on each pin that may forward bias the base-emitter junction. The diodes will prevent large currents from flowing through the image sensor. Note that external diodes D1 and D2 are optional and are only needed if it is possible to forward bias any of the junctions. Note that diodes D1 and D2 are added external to the KAI Revision 1.1 PS-0014 Pg 15

16 PIN DESCRIPTION AND PHYSICAL ORIENTATION SUB 1 34 GND V2E 2 33 V2E V2O 3 32 V2O V1E 4 31 V1E V1O 5 30 V1O ESD 6 29 SUB GND 7 28 FD OGL 8 27 OGR GND 9 26 GND RDL RDR VDDL 11 Pixel 1,1 24 VDDR VOUTL VOUTR RL RR H2BL H2BR H1BL H1BR H1SL H1SR H2SL H2SR Figure 8: Package Pin Designations - Top View Pin Name Description Pin Name Description 1 SUB Substrate 34 GND Ground 2 V2E Vertical Clock, Phase 2, Even 33 V2E Vertical Clock, Phase 2, Even 3 V2O Vertical Clock, Phase 2, Odd 32 V2O Vertical Clock, Phase 2, Odd 4 V1E Vertical Clock, Phase 1, Even 31 V1E Vertical Clock, Phase 1, Even 5 V1O Vertical Clock, Phase 1, Odd 30 V1O Vertical Clock, Phase 1, Odd 6 ESD ESD 29 SUB Substrate 7 GND Ground 28 FD Fast Line Dump Gate 8 OGL Output Gate, Left 27 OGR Output Gate. Right 9 GND Ground 26 GND Ground 10 RDL Reset Drain, Left 25 RDR Reset Drain, Right 11 VDDL Vdd, Left 24 VDDR Vdd, Right 12 VOUTL Video Output, Left 23 VOUTR Video Output. Right 13 RL Reset Gate, Left 22 RR Reset Gate, Right 14 H2BL H2 Barrier, Left 21 H2BR H2 Barrier, Right 15 H1BL H1 Barrier, Left 20 H1BR H1 Barrier, Right 16 H1SL H1 Storage, Left 19 H1SR H1 Storage, Right 17 H2SL H2 Storage, Left 18 H2SR H2 Storage, Right The pins are on a spacing Revision 1.1 PS-0014 Pg 16

17 Imaging Performance TYPICAL OPERATIONAL CONDITIONS Unless otherwise noted, the Imaging Performance Specifications are measured using the following conditions. Description Condition Notes Frame Time 538 msec 1 Horizontal Clock Frequency Light Source Operation 10 MHz Continuous red, green and blue illumination centered at 450, 530 and 650 nm Nominal operating voltages and timing Notes: 1. Electronic shutter is not used. Integration time equals frame time. 2. LEDs used: Blue: Nichia NLPB500, Green: Nichia NSPG500S and Red: HP HLMP For monochrome sensor, only green LED used. SPECIFICATIONS All Configurations Description Symbol Min. Nom. Max. Units Sampling Plan Temperature Tested At ( C) Dark Center Non-Uniformity n/a n/a 2 mvrms Die 27, 40 Dark Global Non-Uniformity n/a n/a 5.0 mvpp Die 27, 40 Global Non-Uniformity n/a %rms Die 27, 40 1 Global Peak to Peak Non-Uniformity PRNU n/a %pp Die 27, 40 1 Center Non-Uniformity n/a %rms Die 27, 40 1 Maximum Photoresponse Nonlinearity NL n/a 2 % Design 2, 3 Maximum Gain Difference Between Outputs Max. Signal Error due to Nonlinearity Dif. G n/a 10 % Design 2, 3 NL n/a 1 % Design 2, 3 Horizontal CCD Charge Capacity HNe 100 ke - Design Vertical CCD Charge Capacity VNe ke - Die Photodiode Charge Capacity PNe ke - Die Horizontal CCD Charge Transfer Efficiency HCTE n/a Design Vertical CCD Charge Transfer Efficiency VCTE n/a Design Photodiode Dark Current Ipd n/a e/p/s Die Photodiode Dark Current Ipd n/a na/cm 2 Die Vertical CCD Dark Current Ivd n/a e/p/s Die Vertical CCD Dark Current Ivd n/a na/cm 2 Die Image Lag Lag n/a <10 50 e - Design Antiblooming Factor Xab n/a Vertical Smear Smr n/a db Total Noise n e-t 12 e - rms Design 4 Total Noise n e-t 25 e - rms Design 5 Dynamic Range DR 60 db Design 5, 6 Output Amplifier DC Offset V odc V Die Output Amplifier Bandwidth F -3db 140 MHz Design Output Amplifier Impedance R OUT Ohms Die Output Amplifier Sensitivity V/ N 31 μv/e - Design 2,3 Notes Revision 1.1 PS-0014 Pg 17

18 KAI-4021-ABA Configuration Description Symbol Min. Nom. Max. Units Sampling Plan Peak Quantum Efficiency QE max n/a % Design Peak Quantum Efficiency Wavelength λqe XXX 500 n/a nm Design Temperature Tested At ( C) Notes KAI-4021-CBA-Configuration Description Symbol Min. Nom. Max. Units Peak Quantum Efficiency Blue Green Red Peak Blue Quantum Green Efficiency Red Wavelength n/a: not applicable QE max λqe n/a n/a n/a n/a n/a n/a Sampling Plan % Design nm Design Notes: 1. Per color. 2. Value is over the range of 10% to 90% of photodiode saturation. 3. Value is for the sensor operated without binning 4. Includes system electronics noise, dark pattern noise and dark current shot noise at 20 MHz. 5. Includes system electronics noise, dark pattern noise and dark current shot noise at 40 MHz. 6. Uses 20LOG(PNe/ ne-t) Tempera-ture Tested At ( C) Notes Revision 1.1 PS-0014 Pg 18

19 Absolute Quantum Efficiency Absolute Quantum Efficiency KAI-4021 Image Sensor Typical Performance Curves QUANTUM EFFICIENCY Monochrome with Microlens Measured with glass Wavelength (nm) Figure 9: Monochrome with Microlens Quantum Efficiency Monochrome without Microlens Wavelength (nm) Figure 10: Monochrome without Microlens Quantum Efficiency Revision 1.1 PS-0014 Pg 19

20 Absolute Quantum Efficiency KAI-4021 Image Sensor Color (Bayer RGB) with Microlens Measured with glass Wavelength (nm) Red Green Blue Figure 11: Color Quantum Efficiency Revision 1.1 PS-0014 Pg 20

21 Electrons/second KAI-4021 Image Sensor ANGULAR QUANTUM EFFICIENCY For the curves marked Horizontal, the incident light angle is varied in a plane parallel to the HCCD. For the curves marked Vertical, the incident light angle is varied in a plane parallel to the VCCD. Monochrome with Microlens Relative Quantum Efficiency (% ) Vertical Horizontal Angle (degrees) Figure 12: Monochrome with Microlens Angular Quantum Efficiency DARK CURRENT VERSUS TEMPERATURE VCCD Photodiodes /T(K) T (C) Figure 13: Dark Current versus Temperature Revision 1.1 PS-0014 Pg 21

22 Frame Rate (fps) Power (mw) KAI-4021 Image Sensor POWER - ESTIMATED Right Output Disabled Horizontal Clock Frequency (MHz) Output Pow er One Output(mW) Vertical Pow er (mw) Horizonatl Pow er (mw) Total Pow er One Output (mw) Figure 14: Power FRAME RATES Dual 2x2 binning Dual output or Single 2x2 binning 5 Single output Pixel Clock (MHz) Figure 15: Frame Rates Revision 1.1 PS-0014 Pg 22

23 Defect Definitions Description Definition Maximum Major dark field defective pixel Major bright field defective pixel Minor dark field defective pixel Temperature(s) tested at ( C) Defect 148 mv , 40 Defect 10% 1 Defect 76 mv , 40 Dead pixel Defect 80% 5 27, 40 1 Saturated pixel Defect 340 mv 10 27, 40 1 Cluster defect Column defect A group of 2 to 10 contiguous major defective pixels, but no more than 2 adjacent defects horizontally A group of more than 10 contiguous major defective pixels along a single column Notes: 1. There will be at least two non-defective pixels separating any two major defective pixels. Notes 8 27, , 40 1 DEFECT MAP The defect map supplied with each sensor is based upon testing at an ambient (27 C) temperature. Minor point defects are not included in the defect map. All defective pixels are reference to pixel 1, 1 in the defect maps. Revision 1.1 PS-0014 Pg 23

24 Horizontal Overclock KAI-4021 Image Sensor Test Definitions TEST REGIONS OF INTEREST Active Area ROI: Pixel (1, 1) to Pixel (2048, 2048) Center 100 by 100 ROI: Pixel (974, 974) to Pixel (1073, 1073) Only the active pixels are used for performance and defect tests. OVERCLOCKING The test system timing is configured such that the sensor is overclocked in both the vertical and horizontal directions. See Figure 16 for a pictorial representation of the regions. H Pixel 1,1 V Vertical Overclock Figure 16: Overclock Regions of Interest Revision 1.1 PS-0014 Pg 24

25 TESTS Dark Field Center Non-Uniformity This test is performed under dark field conditions. Only the center 100 by 100 pixels of the sensor are used for this test - pixel (974,974) to pixel (1073,1073). Units: mv rms Dark Field Center Non-Uniformity = Standard Deviation of center 100 by 100 pixels in mv Dark Field Global Non-Uniformity This test is performed under dark field conditions. The sensor is partitioned into 256 sub regions of interest, each of which is 128 by 128 pixels in size. The average signal level of each of the 256 sub regions of interest is calculated. The signal level of each of the sub regions of interest is calculated using the following formula: Signal of ROI[i] = (ROI Average in ADU Horizontal overclock average in ADU) * mv per count. Where i = 1 to 256. During this calculation on the 256 sub regions of interest, the maximum and minimum signal levels are found. The dark field global non-uniformity is then calculated as the maximum signal found minus the minimum signal level found. Units: mvpp (millivolts peak to peak) Global Non-Uniformity This test is performed with the imager illuminated to a level such that the output is at 70% of saturation (approximately 868 mv). Prior to this test being performed the substrate voltage has been set such that the charge capacity of the sensor is 1240 mv. Global non-uniformity is defined as Global Non - Uniformity Active Area Standard Deviation 100* Active Area Signal Units: %rms Active Area Signal = Active Area Average Horizontal Overclock Average Global Peak to Peak Non-Uniformity This test is performed with the imager illuminated to a level such that the output is at 70% of saturation (approximately 868 mv). Prior to this test being performed the substrate voltage has been set such that the charge capacity of the sensor is 1240 mv. The sensor is partitioned into 256 sub regions of interest, each of which is 128 by 128 pixels in size. The average signal level of each of the 256 sub regions of interest (ROI) is calculated. The signal level of each of the sub regions of interest is calculated using the following formula: A[i] = (ROI Average Horizontal Overclock Average) Where i = 1 to 256. During this calculation on the 256 sub regions of interest, the maximum and minimum average signal levels are found. The global peak to peak non-uniformity is then calculated as: Global Non - Uniformity 100* A[i] Maximum Signal - A[i] MinimumSignal Active Area Signal Active Area Signal = Active Area Average Horizontal Overclock Average Units: %pp Revision 1.1 PS-0014 Pg 25

26 Center Non-Uniformity This test is performed with the imager illuminated to a level such that the output is at 70% of saturation (approximately 868 mv). Prior to this test being performed the substrate voltage has been set such that the charge capacity of the sensor is 1240 mv. Defects are excluded for the calculation of this test. This test is performed on the center 100 by 100 pixels (See Test Regions of Interest) of the sensor. Center non-uniformity is defined as: Center ROI Non - Uniformity Center ROI Standard Deviation 100* Center ROI Signal Units: %rms Center ROI Signal = Center ROI Average Horizontal Overclock Average Dark Field Defect Test This test is performed under dark field conditions. The sensor is partitioned into 256 sub regions of interest, each of which is 128 by 128 pixels in size. In each region of interest, the median value of all pixels is found. For each region of interest, a pixel is marked defective if it is greater than or equal to the median value of that region of interest plus the defect threshold specified in Defect Definitions section. Bright Field Defect Test This test is performed with the imager illuminated to a level such that the output is at 70% of saturation (approximately 28,000 electrons). Prior to this test being performed the substrate voltage has been set such that the charge capacity of the sensor is 40,000 electrons. The average signal level of all active pixels is found. The bright and dark thresholds are set as: Dark defect threshold = Active Area Signal * threshold Bright defect threshold = Active Area Signal * threshold The sensor is then partitioned into 256 sub regions of interest, each of which is 128 by 128 pixels in size. In each region of interest, the average value of all pixels is found. For each region of interest, a pixel is marked defective if it is greater than or equal to the median value of that region of interest plus the bright threshold specified or if it is less than or equal to the median value of that region of interest minus the dark threshold specified. Example for major bright field defective pixels: Average value of all active pixels is found to be 868 mv (28,000 electrons). Dark defect threshold: 868mV * 15% = mv Bright defect threshold: 868mV * 15% = mv Region of interest #1 selected. This region of interest is pixels 1, 1 to pixels 128, 128. o o o Median of this region of interest is found to be 868 mv. Any pixel in this region of interest that is ( mv) mv in intensity will be marked defective. Any pixel in this region of interest that is ( mv) mv in intensity will be marked defective. All remaining 255 sub-regions of interest are analyzed for defective pixels in the same manner. Revision 1.1 PS-0014 Pg 26

27 Operation MAXIMUM RATINGS Absolute maximum rating is defined as a level or condition that should not be exceeded at any time per the description. If the level or the condition is exceeded, the device will be degraded and may be damaged. Description Symbol Minimum Maximum Units Notes Operating Temperature T C 1 Humidity RH 5 90 % 2 Output Bias Current Iout ma 3 Off-chip Load C L 10 pf 4 Notes: 1. Noise performance will degrade at higher temperatures. 2. T=25 ºC. Excessive humidity will degrade MTTF. 3. Each output. See Figure 17: Output Amplifier. Note that the current bias affects the amplifier bandwidth. 4. With total output load capacitance of CL = 10pF between the outputs and AC ground. 5. Absolute maximum rating is defined as a level or condition that should not be exceeded at any time per the description. If the level or the condition is exceeded, the device will be degraded and may be damaged. MAXIMUM VOLTAGE RATINGS BETWEEN PINS Description Minimum Maximum Units Notes RL, RR, H1S, H2S, H1BL, H2BL, H1BR, H2BR, OGR, OGL to ESD 0 17 V Pin to Pin with ESD Protection V 1 VDDL, VDDR to GND 0 25 V Notes: 1. Pins with ESD protection are: RL, RR, H1S, H2S, H1BL, H2BL, H1BR, H2BR, OGL, and OGR. Revision 1.1 PS-0014 Pg 27

28 DC BIAS OPERATING CONDITIONS Description Symbol Minimum Nominal Maximum Units Maximum DC Current (ma) Output Gate OG V 1 μa 4, 5 Reset Drain RD V 1 μa 4 Output Amplifier Supply VDD V 1 ma 3 Ground GND V Substrate SUB 8.0 Vab 17.0 V 1, 7 ESD Protection ESD V 2 Output Bias Current Iout ma 6 Notes: 1. The operating value of the substrate voltage, Vab, will be marked on the shipping container for each device. The value Vab is set such that the photodiode charge capacity is 40,000 electrons. 2. VESD must be equal to FDL and more negative than H1L, H2L and RL during sensors operation AND during camera power turn on. 3. One output, unloaded. The maximum DC current is for one output unloaded and is shown as Iss in Figure 17. This is the maximum current that the first two stages of one output amplifier will draw. This value is with Vout disconnected. 4. May be changed in future versions. 5. Output gate voltage level must be set to 3V for 40,000 80,000 electrons output in summed interlaced or binning modes. 6. One output. 7. Refer to Application Note Using Interline CCD Image Sensors in High Intensity Visible Lighting Conditions. Notes VDD Idd Floating Diffusion Iout VOUT Iss Source Follower #1 Source Follower #2 Source Follower #3 Figure 17: Output Amplifier Revision 1.1 PS-0014 Pg 28

29 AC OPERATING CONDITIONS Clock Levels Description Symbol Minimum Nominal Maximum Units Notes Vertical CCD Clock High V2H V Vertical CCD Clocks Midlevel V1M, V2M V Vertical CCD Clocks Low V1L, V2L V Horizontal CCD Clocks High H1H, H2H V Horizontal CCD Clocks Low H1L, H2L V Reset Clock Amplitude RH 5.0 V 1 Reset Clock Low RL V Electronic Shutter Voltage Vshutter V 2 Fast Dump High FDH V Fast Dump Low FDL V Notes: 1. Reset amplitude must be set to 7.0 V for 40,000 80,000 electrons output in summed interlaced or binning modes. 2. Refer to Application Note Using Interline CCD Image Sensors in High Intensity Visible Lighting Conditions. Clock Line Capacitances V1E 20nF 5nF H1SL+H1BL 50pF 25pF V1O 20nF 5nF H2SL+H2BL 50pF V2E 20nF 5nF H1SR+H1BR 50pF 25pF V2O 20nF 5nF H2SR+H2BR 50pF GND GND Reset SUB FD 10pF 4nF 40pF GND GND Figure 18: Clock Line Capacitances GND Revision 1.1 PS-0014 Pg 29

30 TIMING REQUIREMENTS Description Symbol Minimum Nominal Maximum Units Notes HCCD Delay T HD μs VCCD Transfer time T VCCD μs Photodiode Transfer time T V3rd μs VCCD Pedestal time T 3P μs VCCD Delay T 3D μs Reset Pulse time T R ns Shutter Pulse time T S μs Shutter Pulse delay T SD μs HCCD Clock Period T H ns 1 VCCD rise/fall time T VR μs Fast Dump Gate delay T FD 0.5 μs Vertical Clock Edge Alignment T VE ns Notes: 1. For operation at the minimum HCCD clock period (40 MHz), the substrate voltage will need to be raised to limit the signal at the output to 20,000 electrons. Revision 1.1 PS-0014 Pg 30

31 TIMING MODES Progressive Scan photodiode CCD shift register output 0 HCCD Figure 19: Progressive Scan Operation In progressive scan read out every pixel in the image sensor is read out simultaneously. Each charge packet is transferred from the photodiode to the neighboring vertical CCD shift register simultaneously. The maximum useful signal output is limited by the photodiode charge capacity to 40,000 electrons. Vertical Frame Timing Line Timing Repeat for 2072 Lines Figure 20: Progressive Scan Flow Chart Revision 1.1 PS-0014 Pg 31

32 Summed Interlaced Scan even field odd field Figure 21: Summed Interlaced Scan Operation In the summed interlaced scan read out mode, charge from two photodiodes is summed together inside the vertical CCD. The clocking of the VCCD is such that one pixel occupies the space equivalent to two pixels in the progressive scan mode. This allows the VCCD to hold twice as many electrons as in progressive scan mode. Now the maximum useful signal is limited by the charge capacity of two photodiodes at 80,000 electrons. If only one field is read out of the image sensor the apparent vertical resolution will be 1024 rows instead of the 2048 rows in progressive scan (equivalent to binning). To recover the full resolution of the image sensor two fields, even and odd, are read out. In the even field rows 0+1, 2+3, 4+5, are summed together. In the odd field rows 1+2, 3+4, 5+6, are summed together. The modulation transfer function (MTF) of the summed interlaced scan mode is less in the vertical direction than the progressive scan. But the dynamic range is twice that of progressive scan. The vertical MTF is better than a simple binning operation. In this mode the VCCD needs to be clocked for only 1037 rows to read out each field. Summed Interlaced Even Frame Timing Summed Interlaced Odd Frame Timing Interlaced Line Timing Interlaced Line Timing Repeat for 1037 Lines Repeat for 1037 Lines Figure 22: Summed Interlaced Scan Flow Chart Revision 1.1 PS-0014 Pg 32

33 Non-Summed Interlaced Scan even field odd field Figure 23: Non- Summed Interlaced Scan Operation In the non-summed interlaced scan mode only half the photodiode are read out in each field. In the even field rows 0, 2, 4, are transferred to the VCCD. In the odd field rows 1, 3, 5, are transferred to the VCCD. When the charge packet is transferred from a photodiode is occupies the equivalent of two rows in progressive scan mode. This allows the VCCD to hold twice as much charge a progressive scan mode. However, since only one photodiode for each row is transferred to the VCCD the maximum usable signal is still only 40,000 electrons. The large extra capacity of the VCCD causes the anti-blooming protection to be increased dramatically compared to the progressive scan. The vertical MTF is the same between the non-summed interlaced scan and progressive scan. There will be motion related artifacts in the images read out in the interlaced modes because the two fields are acquired at different times. Non-Summed Interlaced Even Frame Timing Non-Summed Interlaced Odd Frame Timing Interlaced Line Timing Interlaced Line Timing Repeat for 1037 Lines Repeat for 1037 Lines Figure 24: Non- Summed Interlaced Scan Flow Chart Revision 1.1 PS-0014 Pg 33

34 FRAME TIMING Frame Timing without Binning Progressive Scan V1 T L T V3rd T L V2 Line 2071 T 3P T 3D Line 2072 Line 1 H1 H2 Figure 25: Framing Timing without Binning Frame Timing for Vertical Binning by 2 Progressive Scan V1 T L T V3rd T L 3 x T VCCD V2 Line 1035 T 3P T 3D Line 1036 Line 1 H1 H2 Figure 26: Frame Timing for Vertical Binning by 2 Revision 1.1 PS-0014 Pg 34

35 Frame Timing Non-Summed Interlaced Scan (Even) V1E V1M V1L V2H V2E V2M V2L V1O V1M V1L V2O V2M V2L T V3rd T V3rd T V3rd T VCCD H2 last odd line readout even frame timing vertical retrace horizontal retrace first even line readout Figure 27: Non-Summed Interlaced Scan Even Frame Timing Revision 1.1 PS-0014 Pg 35

36 Frame Timing Non-Summed Interlaced Scan (Odd) V1E V1M V1L V2E V2M V2L V1O V1M V1L V2H V2O V2M V2L T V3rd T V3rd T V3rd T VCCD H2 last even line readout odd frame timing vertical retrace horizontal retrace first odd line readout Figure 28: Non-Summed Interlaced Scan Odd Frame Timing Revision 1.1 PS-0014 Pg 36

37 Frame Timing Summed Interlaced Scan (Even) V1E V1M V1L V2H V2E V2M V2L V1O V1M V1L V2H V2O V2M V2L T 3P T V3rd T 3D T VCCD T VCCD T VCCD TVCCD TVCCD T VCCD T VCCD H2 last odd line readout even frame timing vertical retrace horizontal retrace first even line readout Figure 29: Summed Interlaced Scan Even Frame Timing Revision 1.1 PS-0014 Pg 37

38 Frame Timing Summed Interlaced Scan (Odd) V1E V1M V1L V2H V2E V2M V2L V1O V1M V1L V2H V2O V2M V2L T 3P T V3rd T 3D T VCCD T VCCD T VCCD TVCCD TVCCD T VCCD T VCCD H2 last even line readout odd frame timing vertical retrace horizontal retrace first odd line readout Figure 30: Summed Interlaced Scan Odd Frame Timing Revision 1.1 PS-0014 Pg 38

39 Frame Timing Edge Alignment V1 V1M V1L V2H V2M V2 T VE V2L Figure 31: Frame Timing Edge Alignment Revision 1.1 PS-0014 Pg 39

40 KAI-4021 Image Sensor LINE TIMING Line Timing Single Output Progressive Scan T L V1 V2 T VCCD T HD H1 H2 R pixel count Line Timing Dual Output Progressive Scan Figure 32: Line Timing Single Output V1 T L V2 T VCCD T HD H1 H2 R pixel count Figure 33: Line Timing Dual Output Revision 1.1 PS-0014 Pg 40

41 KAI-4021 Image Sensor Line Timing Vertical Binning by 2 Progressive Scan V1 T L V2 3 x T VCCD T HD H1 H2 R pixel count Figure 34: Line Timing Vertical Binning by 2 Revision 1.1 PS-0014 Pg 41

42 Line Timing Detail Progressive Scan V1 V2 T VCCD 1/2 T H T HD H1 H2 R Figure 35: Line Timing Detail Line Timing Binning by 2 Detail Progressive Scan V1 V2 1/2 T H T VCCD T VCCD T VCCD T HD H1 H2 R Figure 36: Line Timing by 2 Detail Revision 1.1 PS-0014 Pg 42

43 Line Timing Interlaced Modes V1E V2E V1O V2O H2 T VCCD Figure 37: Line Timing Interlaced Modes Revision 1.1 PS-0014 Pg 43

44 Line Timing Edge Alignment Applies to all modes. T VCCD V1 V2 T VE T VE Figure 38: Line Timing Edge Alignment Revision 1.1 PS-0014 Pg 44

45 PIXEL TIMING V1 V2 H1 H2 Pixel Count R Vout Dummy Pixels Light Shielded Pixels Photosensitive Pixels Figure 39: Pixel Timing Pixel Timing Detail H2 R H1 T R RH RL H1H H1L H2H H2L VOUT Figure 40: Pixel Timing Detail Revision 1.1 PS-0014 Pg 45

46 FAST LINE DUMP TIMING FD V1 V2 T FD T VCCD T FD T VCCD H1 H2 Figure 41: Fast Line Dump Timing Revision 1.1 PS-0014 Pg 46

47 ELECTRONIC SHUTTER Electronic Shutter Line Timing V1 V2 T VCCD VShutter T HD T S VSUB T SD H1 H2 R Figure 42: Electronic Shutter Line Timing Electronic Shutter Integration Time Definition V2 VShutter Integration Time VSUB Figure 43: Integration Time Definition The figure below shows the DC bias (SUB) and AC clock (Vshutter) applied to the SUB pin. Both the DC bias and AC clock are referenced to ground. Vshutter SUB GND GND Revision 1.1 PS-0014 Pg 47

48 Electronic Shutter Description The voltage on the substrate (SUB) determines the charge capacity of the photodiodes. When SUB is 8 volts the photodiodes will be at their maximum charge capacity. Increasing VSUB above 8 volts decreases the charge capacity of the photodiodes until 48 volts when the photodiodes have a charge capacity of zero electrons. Therefore, a short pulse on SUB, with a peak amplitude greater than 48 volts, empties all photodiodes and provides the electronic shuttering action. It may appear the optimal substrate voltage setting is 8 volts to obtain the maximum charge capacity and dynamic range. While setting VSUB to 8 volts will provide the maximum dynamic range, it will also provide the minimum antiblooming protection. The KAI-4021 VCCD has a charge capacity of 60,000 electrons (60 ke - ). If the SUB voltage is set such that the photodiode holds more than 60 ke -, then when the charge is transferred from a full photodiode to VCCD, the VCCD will overflow. This overflow condition manifests itself in the image by making bright spots appear elongated in the vertical direction. The size increase of a bright spot is called blooming when the spot doubles in size. The blooming can be eliminated by increasing the voltage on SUB to lower the charge capacity of the photodiode. This ensures the VCCD charge capacity is greater than the photodiode capacity. There are cases where an extremely bright spot will still cause blooming in the VCCD. Normally, when the photodiode is full, any additional electrons generated by photons will spill out of the photodiode. The excess electrons are drained harmlessly out to the substrate. There is a maximum rate at which the electrons can be drained to the substrate. If that maximum rate is exceeded, (for example, by a very bright light source) then it is possible for the total amount of charge in the photodiode to exceed the VCCD capacity. This results in blooming. The amount of antiblooming protection also decreases when the integration time is decreased. There is a compromise between photodiode dynamic range (controlled by VSUB) and the amount of antiblooming protection. A low VSUB voltage provides the maximum dynamic range and minimum (or no) antiblooming protection. A high VSUB voltage provides lower dynamic range and maximum antiblooming protection. The optimal setting of VSUB is written on the container in which each KAI-4021 is shipped. The given VSUB voltage for each sensor is selected to provide antiblooming protection for bright spots at least 100 times saturation, while maintaining at least 40ke- of dynamic range. The electronic shutter provides a method of precisely controlling the image exposure time without any mechanical components. If an integration time of T INT is desired, then the substrate voltage of the sensor is pulsed to at least 40 volts T INT seconds before the photodiode to VCCD transfer pulse on V2. Use of the electronic shutter does not have to wait until the previously acquired image has been completely read out of the VCCD. Revision 1.1 PS-0014 Pg 48

49 LARGE SIGNAL OUTPUT When the image sensor is operated in the binned or summed interlaced modes there will be more than 20,000 electrons in the output signal. The image sensor is designed with a 31 µv/e charge to voltage conversion on the output. This means a full signal of 20,000 electrons will produce a 640 mv change on the output amplifier. The output amplifier was designed to handle an output swing of 640 mv at a pixel rate of 40 MHz. If 40,000 electron charge packets are generated in the binned or summed interlaced modes then the output amplifier output will have to swing 1280 mv. The output amplifier does not have enough bandwidth (slew rate) to handle 1280 mv at 40 MHz. Hence, the pixel rate will have to be reduced to 20 MHz if the full dynamic range of 40,000 electrons is desired. The charge handling capacity of the output amplifier is also set by the reset clock voltage levels. The reset clock driver circuit is very simple if an amplitude of 5 V is used. But the 5 V amplitude restricts the output amplifier charge capacity to 20,000 electrons. If the full dynamic range of 40,000 electrons is desired then the reset clock amplitude will have to be increased to 7 V. If you only want a maximum signal of 20,000 electrons in binned or summed interlaced modes, then a 40 MHz pixel rate with a 5 V reset clock may be used. The output of the amplifier will be unpredictable above 20,000 electrons so be sure to set the maximum input signal level of your analog to digital converter to the equivalent of 20,000 electrons (640 mv). Revision 1.1 PS-0014 Pg 49

50 Storage and Handling STORAGE CONDITIONS Description Symbol Minimum Maximum Units Notes Storage Temperature T ST C 1 Humidity RH 5 90 % 2 Notes: 1. Long-term exposure toward the maximum temperature will accelerate color filter degradation. 2. T=25 ºC. Excessive humidity will degrade MTTF ESD 1. This device contains limited protection against Electrostatic Discharge (ESD). ESD events may cause irreparable damage to a CCD image sensor either immediately or well after the ESD event occurred. Failure to protect the sensor from electrostatic discharge may affect device performance and reliability. 2. Devices should be handled in accordance with strict ESD procedures for Class 0 (<250V per JESD22 Human Body Model test), or Class A (<200V JESD22 Machine Model test) devices. Devices are shipped in static-safe containers and should only be handled at static-safe workstations. 3. See Application Note Image Sensor Handling Best Practices for proper handling and grounding procedures. This application note also contains workplace recommendations to minimize electrostatic discharge. 4. Store devices in containers made of electroconductive materials. COVER GLASS CARE AND CLEANLINESS 1. The cover glass is highly susceptible to particles and other contamination. Perform all assembly operations in a clean environment. 2. Touching the cover glass must be avoided. 3. Improper cleaning of the cover glass may damage these devices. Refer to Application Note Image Sensor Handling Best Practices. ENVIRONMENTAL EXPOSURE 1. Extremely bright light can potentially harm CCD image sensors. Do not expose to strong sunlight for long periods of time, as the color filters and/or microlenses may become discolored. In addition, long time exposures to a static high contrast scene should be avoided. Localized changes in response may occur from color filter/microlens aging. For Interline devices, refer to Application Note Using Interline CCD Image Sensors in High Intensity Visible lighting Conditions. 2. Exposure to temperatures exceeding maximum specified levels should be avoided for storage and operation, as device performance and reliability may be affected. 3. Avoid sudden temperature changes. 4. Exposure to excessive humidity may affect device characteristics and may alter device performance and reliability, and therefore should be avoided. 5. Avoid storage of the product in the presence of dust or corrosive agents or gases, as deterioration of lead solderability may occur. It is advised that the solderability of the device leads be assessed after an extended period of storage, over one year. SOLDERING RECOMMENDATIONS 1. The soldering iron tip temperature is not to exceed 370 C. Higher temperatures may alter device performance and reliability. 2. Flow soldering method is not recommended. Solder dipping can cause damage to the glass and harm the imaging capability of the device. Recommended method is by partial heating using a grounded 30 W soldering iron. Heat each pin for less than 2 seconds duration. Revision 1.1 PS-0014 Pg 50

51 Mechanical Information COMPLETED ASSEMBLY Notes: 1. See Ordering Information for Marking Code 2. The cover glass is manually placed and aligned. Figure 44: Completed Assembly Revision 1.1 PS-0014 Pg 51

52 DIE TO PACKAGE ALIGNMENT Figure 45: Die to Package Alignment Revision 1.1 PS-0014 Pg 52

53 GLASS Notes: 1. Multi-Layer Anti-Reflective Coating on 2 sides: a. Double Sided Reflectance: b. Range (nm) i nm < 2.0% ii nm < 0.8% iii nm < 2.0% 2. Dust, Scratch specification 10 microns max. 3. Substrate Schott D263T eco or equivalent 4. Epoxy: NCO-150HB a. Thickness: Dimensions a. Units: INCH [MM] 6. Tolerance, unless otherwise specified a. Ceramic: ± 1% no less than b. L/F: ± 1% no more than Figure 46: Glass Drawing Revision 1.1 PS-0014 Pg 53

54 Transmission (%) KAI-4021 Image Sensor GLASS TRANSMISSION Wavelength (nm) Figure 47: Glass Transmission Revision 1.1 PS-0014 Pg 54

55 Quality Assurance and Reliability QUALITY AND RELIABILITY All image sensors conform to the specifications stated in this document. This is accomplished through a combination of statistical process control and visual inspection and electrical testing at key points of the manufacturing process, using industry standard methods. Information concerning the quality assurance and reliability testing procedures and results are available from ON Semiconductor upon request. For further information refer to Application Note Quality and Reliability. REPLACEMENT All devices are warranted against failure in accordance with the Terms of Sale. Devices that fail due to mechanical and electrical damage caused by the customer will not be replaced. LIABILITY OF THE SUPPLIER A reject is defined as an image sensor that does not meet all of the specifications in this document upon receipt by the customer. Product liability is limited to the cost of the defective item, as defined in the Terms of Sale. LIABILITY OF THE CUSTOMER Damage from mishandling (scratches or breakage), electrostatic discharge (ESD), or other electrical misuse of the device beyond the stated operating or storage limits, which occurred after receipt of the sensor by the customer, shall be the responsibility of the customer. TEST DATA RETENTION Image sensors shall have an identifying number traceable to a test data file. Test data shall be kept for a period of 2 years after date of delivery. MECHANICAL The device assembly drawing is provided as a reference. ON Semiconductor reserves the right to change any information contained herein without notice. All information furnished by ON Semiconductor is believed to be accurate. Life Support Applications Policy ON Semiconductor image sensors are not authorized for and should not be used within Life Support Systems without the specific written consent of ON Semiconductor. Revision 1.1 PS-0014 Pg 55

56 Revision Changes MTD/PS-0719 Revision Number Description of Changes 1.0 Initial formal release Removed caution for cover glass protective tape. The use of the protective tape has been discontinued. Removed note under Cover Glass Care and Cleanliness section that referred to cover glass protective tape. Updated format Updated package drawings. 3.0 Reformatted Ordering Information, Storage and Handling, and Quality Assurance and Reliability pages 4.0 Added the note Refer to Application Note Using Interline CCD Image Sensors in High Intensity Visible Lighting Conditions to the following sections o DC Bias Operating Conditions o AC Operating Conditions o Storage and Handling Added figure in Electronic Shutter section showing relationship between ground and the substrate DC bias and the electronic shutter pulse Changed cover glass material to D263T eco or equivalent PS-0014 Revision Number 1.0 Description of Changes Initial release with new document number, updated branding and document template Updated Storage and Handling and Quality Assurance and Reliability sections Reorganized structure for consistency with other Interline Transfer CCD documents 1.1 Updated branding Revision 1.1 PS-0014 Pg , Semiconductor Components Industries, LLC.