gate symbols will appear in schematic Dierent of a circuit. Standard gate symbols have been diagram Figures 5-3 and 5-4 show standard shapes introduce

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1 chapter is concerned with examples of basic This circuits including decoders, combinational xor gate and parity circuits, multiplexers, comparators, adders. Those basic building circuits frequently and Standards Documentation is necessary for correct design and Documentation debug and maintenance of digital systems. ecient should consist of following items: documentation a specication describes functionality (e.g., it does ) of a circuit and its inputs and what a block diagram is an informal pictorial of circuit's major functional description electrical components of system, ir and details about each ICchips. interconnections, diagram shows inputs, outputs, functional Block internal data paths, and important control modules, a bus is a collection of two or more signal lines. Note represents interconnection and data ow between It Chapter 5 Combinational Logic Design Practices e1 a timing diagram shows various logic signals Slide 3 as a function of time. appear in combinational circuits. Block Diagrams Slide 4 signals of a system. See Figure 5.1 for example. e2 outputs. two functional modules. modules and interconnections. a schematic diagram is a formal specication of

2 gate symbols will appear in schematic Dierent of a circuit. Standard gate symbols have been diagram Figures 5-3 and 5-4 show standard shapes introduced. commonly used gates. for a buer is a circuit that converts weak logic Note to strong ones. signals signal has an active level associated with it. Each is active high if it performs named action signal it is high. signal is active low if it performs when named action when it is low. signal is said to be if it is at its active level. signal is said to asserted negated if it is not activated. be naming conventions may be used to represent Dierent levels. See table 5-1. Figure 5-5 shows how to active active levels of input and output a represent circuit (as represented by a rectangular box). n logic bubble to indicate active low while inversion of a bubble to indicate an active high. absence a logic symbol for a digital circuit may lternatively, its pins labeled as active high or active low. have 5-14 and 5-15 show two dierent schematic Figure at and hierarchical. Figure 5-17 shows a structures: schematic digram for a circuit using a detailed Figure 5-18 shows pinouts for standard 74HCT00. ctive Levels (cont'd) Gate Symbols Slide 7 e5 ctive Levels Schematic Diagrams Slide 8 e6 74-series ICs.

3 timing diagram illustrates logical behaviors of in a digital circuit as a function of time. signals important information provided by a timing most is a specication of delay. See Fig Note diagram delay is subject to many factors and is often specied a a range between maximum and minimum delay or by is a combinational two level ND-OR device that PL be programmed to realize any sum of products can PL often has a maximum number of expression. outputs, and product terms. See gs inputs, See Fig for programmed PL. Note and ND and OR gates are programmable. both programmable logic device is Programmable nor Logic (PL), which has xed OR gates and only rray decoder is a multiple input and multiple output circuit that decodes coded input. It maps an logic code into an output code. number of inputs input usually fewer than that of output. decoder usually is a special input called enable. Itmust be contains before decoder can perform its normal asserted most common decoder is binary decoder where number of output is power of 2 of number input. For example, we have n to 2 n binary decoder, of n is number of input and 2 n is number where output. binary decoder is used when you need to of exactly one of 2 n outputs based on n inputs. activate Decoders Timing Diagrams e9 Slide 11 function. It is not counted as an input. See gure by a typical delay value. Programmable Logic rrays (PL) Binary Decoders 10 Slide 12 Note "don't care" notation in truth table. ND gates can be programmed.

4 5-4 gives truth table of a 2-to-4 binary Table logic symbol and logic diagram of a decoder. input codes are not limited to decimal numbers may represent any consecutive physical entities but not all outputs of a decoder may be used. For and see table 5-6. example, logic symbol for a decoder is drawn with input on left and output pins on right of pins active levels of input and output pins symbol. be specied. Each pin has two names: one need and one external name. For active high, y internal same. For active low, external name is are dual 2-to-4 decoder consists of two but identical 2-to-4 decoders, contained in independent single MSI (middle size integration) chip. It is a with active-low at outputs. Figure 5-35 gives designed logic diagram and logic symbol for decoder. truth table for half of dual 2-to-4 is shown in table 5-6. Note for both input and decoder top input and top output bit represent output LSB while bottom input bit and bottom bit represent MSB. output Binary Decoders (cont'd) Standard Binary Decoder ICs 2-to-4 binary decoder are shown in Figure Slide Dual 2-to-4 Decoder Logic Symbols for Decoders Slide suxed with L. See gures 5-33 and 5-34.

5 has three enable inputs and its outputs are active It ll three enable inputs must be asserted low. decoder can perform its function. Its logic before and logic symbol are shown in Figure diagram table is shown in Table 5-7. n output is Truth if only decoder is enabled and output asserted binary decoders can be combined in cascade Multiple decode larger code words. Figure 5-38 shows how to to two 3-8 decoders into a 4-to-16 decoder. combine 5-39 shows a 5-to-32 decoder constructed from Figure three state buer contains two inputs and one One of inputs is enable input. It must be output. before buer can function. three asserted buer can be inverting or non-inverting with state active highorlow enable input. See gure 5-53 eir example. for independent three state buers may be Several in a single SSI IC or MSI IC and packaged 126 each contains 4 three state buers (see gure contains 8 three state buers (see 5-56) MSI 3-to-8 Decoder Three State Buers Slide is selected (e.g., Y 5 L ). Standard 3 State Buers ICs Cascading Binary Decoders Slide gure 5-57) decoders and 1 2-to-4 decoder.

6 gure 5-54, use of three state buers allow to8 See of data to drive a single line at a time. sources multiplexer is a digital switch that determines which its n input data should be routed to output. It is a of device in any application where data must be useful from multiple sources to a destination source. switched example, multiplexer between processor's For and its arithmetic logic unit (LU). data registers one of registers must be routed to LU for from execution. n input data, each of which isb bit wide. n is 2,4,8,16. and b is 1,2, and 4. usually 151 selects among 8 1-bit inputs. It provides both 74 high and low output as shown in Figure active truth table is shown in Figure table Its two 4-bit inputs and 1 4-bit output. See Figure has Multiplexers (cont'd) input of a multiplexer consist of s selections inputs to determine which of n Use of 3 State Buers Slide sources to select. s = log 2 n. an enable input, which must be asserted for multiplexer to function. Output: one of n input data see gure Multiplexers Standard Multiplexers ICs Slide for its logic diagram and logic symbol.

7 logic symbols and truth tables for (2 See and 4 bit ) and (4 input 2-bit). inputs (exclusive-or) is a 2 input gate whose output is 1 XOR exactly one of its input is 1. if (exclusive-nor) is a 2 input gate whose output XNOR 1 if its input are same. is to gure 5-37 for logic diagrams and symbols for Refer and XNOR gates. XOR circuit that compares two binary inputs and if y are equal are called comparator. indicates denition, an XOR gate is a one-bit comparator. By XOR gates can be used to perform multiple Multiple comparator. For example, 4 XOR gates for a 4-bit bit is shown in Figure comparator adder performs arithmetic addition of two operands n addition table. n adder whose two using are 1-bit is called half-adder. n adder whose operands operands are more than 1 bit are called full adder. two Comparator Standard Multiplexers ICs Slide How to determine if two inputs are equal? XOR and XNOR gates dder 26 Slide SSI IC contains 4 XOR gates.

8 dder Half inputs and output of a half adder are: Inputs: two operands X and Y dder Full full adder handles one bit of binary addition. While bitwise addition, each bitwise addition has performing following inputs and outputs: ripple adder is a cascade of n full-adders, each of handles one bit. See Figure 5-87 for 4-bit ripple which Full dder (cont'd) Outputs: 29 S = X Y CIN 1) sum (S) Slide 31 COUT = X Y + X CIN + Y CIN 2) carry out (CO) see gure 5-86 for its logic diagram and symbol S = X Y CO = X Y Ripple dder Inputs: 30 Slide 32 input operands X and Y adder. It can perform 4-bit addition. carry in (CIN) Outputs: sum S carry out (CO)

9 can similarly build a n bit ripple subtractor by We n full subtractors as shown in gure cascading a full subtractor can be implemented with a full Note circuit plus inverters. adder Full Subtractor full subtractor handles 1 bit binary subtraction. Ripple Subtractor Inputs: operands X and Y 33 Slide 35 a borrow in(bin) Outputs: dierence (D) a borrow out (BOUT) Full Subtractor (cont'd) 34 D = X Y BIN BOUT = X 0 Y + X 0 BIN + Y BIN This is very similar to equations for full adder

Digital Circuits ECS 371

Digital Circuits ECS 371 Digital Circuits ECS 37 Dr. Prapun Suksompong prapun@siit.tu.ac.th Lecture 0 Office Hours: BKD 360-7 Monday 9:00-0:30, :30-3:30 Tuesday 0:30-:30 Announcement HW4 posted on the course web site Chapter 5: