Name Of The Experiment: Sequential circuit design Latch, Flip-flop and Registers

Transcription

1 EEE 304 Experiment No. 07 Name Of The Experiment: Sequential circuit design Latch, Flip-flop and Registers Important: Submit your Prelab at the beginning of the lab. Prelab 1: Construct a S-R Latch and a Gated S-R Latch circuit using NAND gate and NOR gate. Also draw the truth table for them. Prelab 2: Construct a Gated D Latch circuit using Universal gate and draw the truth table for them. Can you construct a Gated D Latch out of a Gated S-R Latch? Prelab 3: What is the problem of using edge triggered S-R flip flop? How is this problem solved in edge triggered J-K flip-flop and D type flip flop? Part A:Introduction to Latch and Flip- Flop: While gates had to be built directly from transistors, latches can be built from gates, and flip-flops can be built from latches. This fact will make it somewhat easier to understand latches and flip-flops. Both latches and flip-flops are circuit elements whose output depends not only on the current inputs, but also on previous inputs and outputs. The difference between a latch and a flip-flop is that a latch does not have a clock signal, whereas a flip-flop always does. How can we make a circuit out of gates that is not combinatorial? The answer is feed-back, which means that we create loops in the circuit diagrams so that output values depend, indirectly, on themselves. If such feed-back is positive then the circuit tends to have stable states, and if it is negative the circuit will tend to oscillate. A latch has positive feedback. Here is an example of a simple latch: This latch is called SR-latch, which stands for set and reset. Latches are asynchronous, which means that the output changes very soon after the input changes. Most computers today, on the other hand, are synchronous, which means that the outputs of all the sequential circuits change simultaneously to the rhythm of a global clock signal. On the other hand, Flip-flops are synchronous bistable devices. The term synchronous means the output changes state only when the clock input is triggered. That is, changes in the output occur in synchronization with the clock. In this experiment, the three basic categories of bistable elements are emphasized: edge-triggered flipflop, pulse-triggered (master-slave) flip-flop, and data lock-out flip-flop. Each type will be associated with both D and J-K configuration. Edge Triggered flipflop : If the Enabler node of a gated latch is fed with a clock pulse, then the effect of input change will show up at the output when the clock goes high. But the high time of clock is not a very short one. During this time, any change in input will go to the output. It may not always be desirable. To provide a very short 1

2 window for output state transition, we use the edge of the clock pulse. Flip Flops using this edge transition is known as edge triggered flipflop. An edge triggered flip flop changes state either at the positive edge (rising edge) or at the negative edge(falling edge) of the clock pulse and is sensitive to its inputs only at this transition of the clock. The three basic types are introduced here: S-R, J-K and D. The S-R, J-K and D inputs are called synchronous inputs because data on these inputs are transferred to the flip-flop's output only on the triggering edge of the clock pulse.on the other hand, the direct set (SET) and clear (CLR) inputs are called asynchronous inputs, as they are inputs that affect the state of the flipflop independent of the clock. For the synchronous operations to work properly, these asynchronous inputs must both be kept LOW. Edge-triggered S-R flip-flop : The basic operation is illustrated below, along with the truth table for this type of flip-flop. The operation and truth table for a negative edge-triggered flip-flop are the same as those for a positive except that the falling edge of the clock pulse is the triggering edge. Note that the S and R inputs can be changed at any time when the clock input is LOW or HIGH (except for a very short interval around the triggering transition of the clock) without affecting the output. This is illustrated in the timing diagram below: Edge-triggered J-K flip-flop : The J-K flip-flop works very similar to S-R flip-flop. The only difference is that this flip-flop has NO invalid state. The outputs toggle (change to the opposite state) when both J and K inputs are HIGH. The truth table is shown below. Edge-triggered D flip-flop : The operations of a D flip-flop is much more simpler. It has only one input addition to the clock. It is very useful when a single data bit (0 or 1) is to be stored. If there is a HIGH on the D input when a clock pulse is applied, the flip-flop SETs and stores a 1. If there is a LOW on the D input when a clock pulse is applied, the flip-flop RESETs and stores a 0. The truth table below summarize the operations of the 2

3 positive edge-triggered D flip-flop. As before, the negative edge-triggered flip-flop works the same except that the falling edge of the clock pulse is the triggering edge. Exercise 1: Construct a negative edge triggered D type flip flop using universal gate Exercise 2: Modify the circuit in exercise 1 to a positive edge triggered J-K flipflop with active low preset and clear Pulse-Triggered (Master-Slave) Flip-flops : The term pulse-triggered means that data are entered into the flip-flop on the rising edge of the clock pulse, but the output does not reflect the input state until the falling edge of the clock pulse. As this kind of flip-flops are sensitive to any change of the input levels during the clock pulse is still HIGH, the inputs must be set up prior to the clock pulse's rising edge and must not be changed before the falling edge. Otherwise, ambiguous results will happen. The three basic types of pulse-triggered flip-flops are S-R, J-K and D. Their logic symbols are shown below. Notice that they do not have the dynamic input indicator at the clock input but have postponed output symbols at the outputs. The truth tables for the above pulse-triggered flip-flops are all the same as that for the edge-triggered flip-flops, except for the way they are clocked. These flip-flops are also called Master-Slave flipflops simply because their internal construction are divided into two sections. The slave section is basically the same as the master section except that it is clocked on the inverted clock pulse and is controlled by the outputs of the master section rather than by the external inputs. The logic diagram for a basic master-slave S-R flip-flop is shown below. Data Lock-Out Flip-flops The data lock-out flip-flop is similar to the pulse-triggered (master-slave) flip-flop except it has a dynamic clock input. The dynamic clock disables (locks out) the data inputs after the rising edge of the clock pulse. Therefore, the inputs do not need to be held constant while the clock pulse is HIGH. The master section of this flip-flop is like an edge-triggered device. The slave section becomes a 3

4 pulse-triggered device to produce a postponed output on the falling edge of the clock pulse. The logic symbols of S-R, J-K and D data lock-out flip-flops are shown below. Notice they all have the dynamic input indicator as well as the postponed output symbol. Exercise 3: Construct a master slave J-K flip flop Frequency Division (application of flip-flop): When a pulse waveform is applied to the clock input of a J-K flip-flop that is connected to toggle, the Q output is a square wave with half the frequency of the clock input. If more flip-flops are connected together as shown in the figure below, further division of the clock frequency can be achieved. The Q output of the second flip-flop is one-fourth the frequency of the original clock input. This is because the frequency of the clock is divided by 2 by the first flip-flop, then divided by 2 again by the second flip-flop. If more flip-flops are connected this way, the frequency division would be 2 to the power n, where n is the number of flip-flops. Exercise 4: Construct a divide by 8 device using IC Part B : Introduction to registers: Shift registers are a type of sequential logic circuit, mainly for storage of digital data. They are a group of flip-flops connected in a chain so that the output from one flip-flop becomes the input of the next flip-flop. Most of the registers possess no characteristic internal sequence of states. All the flipflops are driven by a common clock, and all are set or reset simultaneously. In this chapter, the basic types of shift registers are studied, such as Serial In - Serial Out, Serial In - Parallel Out, Parallel In - Serial Out, Parallel In - Parallel Out, and bidirectional shift registers. A special form of counter - the shift register counter, is also introduced. Serial In - Serial Out Shift Registers : 4

5 A basic four-bit shift register can be constructed using four D flip-flops, as shown below. The operation of the circuit is as follows. The register is first cleared, forcing all four outputs to zero. The input data is then applied sequentially to the D input of the first flip-flop on the left (FF0). During each clock pulse, one bit is transmitted from left to right. Assume a data word to be The least significant bit of the data has to be shifted through the register from FF0 to FF3. In order to get the data out of the register, they must be shifted out serially. This can be done destructively or non-destructively. For destructive readout, the original data is lost and at the end of the read cycle, all flip-flops are reset to zero. To avoid the loss of data, an arrangement for a nondestructive reading can be done by adding two AND gates, an OR gate and an inverter to the system. The construction of this circuit is shown below. The data is loaded to the register when the control line is HIGH (ie WRITE). The data can be shifted out of the register when the control line is LOW (i. e READ). This is shown in the animation below Serial In - Parallel Out Shift Registers : For this kind of register, data bits are entered serially in the same manner as discussed in the last section. The difference is the way in which the data bits are taken out of the register. Once the data are stored, each bit appears on its respective output line, and all bits are available simultaneously. A construction of a four-bit serial in - parallel out register is shown below. Parallel In - Serial Out Shift Registers : A four-bit parallel in - serial out shift register is shown below. The circuit uses D flip-flops and NAND gates for entering data (ie writing) to the register. 5

6 D0, D1, D2 and D3 are the parallel inputs, where D0 is the most significant bit and D3 is the least significant bit. To write data in, the mode control line is taken to LOW and the data is clocked in. The data can be shifted when the mode control line is HIGH as SHIFT is active high. The register performs right shift operation on the application of a clock pulse Parallel In - Parallel Out Shift Registers For parallel in - parallel out shift registers, all data bits appear on the parallel outputs immediately following the simultaneous entry of the data bits. The following circuit is a four-bit parallel in - parallel out shift register constructed by D flip-flops. The D's are the parallel inputs and the Q's are the parallel outputs. Once the register is clocked, all the data at the D inputs appear at the corresponding Q outputs simultaneously. Exercise 5: A computer or microprocessor-based system commonly requires incoming data to be in parallel format. But frequently, these systems must communicate with external devices that send or receive serial data. Construct a circuit that converts a serial data into 3 bit parallel data(use IC 7474). Exercise 6: Construct a circuit that first read a 3 bit parallel data and then converts it to serial data. Reference: Digital Fundamentals- Floyd Your report should cover All circuit diagrams for the constructed circuits Truth Table Relevant discussions Reviewed By: Md. Imran Momtaz 6