Global Trigger Trigger meeting 27.Sept 00 A.Taurok

Transcription

1 Global Trigger Trigger meeting 27.Sept 00 A.Taurok

2 Global Trigger Crate GT crate VME 9U Backplane 4 MUONS parallel CLOCK, BC_Reset... READOUT _links PSB 12 PSB GT MU 6 GT MU PSB 12 PSB 12 PSB 12 PSB 12 GTL 32 GTL 32 8 TIM FDL TCS GTFE GTL PSB 12 PSB 12 Global Muon Trigger int.conn. Global Trigger GT-part of Trigger Control 3 standard VME slots; 24 ch ISO and MIP bits 8 RPC muons 4 DT muons 4 CSC muons 12 ISO+MIP 4 free 4 not used 4TAU 4 centrjet 4 fwdjet 4EG 4 Calo* 4IEG 4 Calo* = total-et, missing-et Nr_jetsA, Nr_jetsB TTC fibre EVM fibre DAQ fibre 32x L1_Acc, CMD/TYPE to TTCvi,EVM LVDS to Channel Link conversion GT Receiver Crate 6U FAST SIGNALS : Warning, Inhibit,......from Subsystems

3 Pipelined synchronizing buffer PSB GTFE FrontEnd Card GTFE Link ROP Readout processor RO Readoutbus Readout Request VME TIM 1 of 12 CHANNELs VME DPmem Ring Buffer Global Calo Trig 21 bit CHANNEL LINK SYNC CHIP 21 bit CHANNEL LINK GTL PIPELINE or FIFO DELAY CLK, BCRes Start TIM JTAG

4 PSB 6 channel prototype

5 Global Trigger Logic board GTL9U GTL Global Trigger Logic board VME interface Parallel Link 40MHz ALGORITHM AND-OR 140 CONDITION Parallel Link Chip 4 MUONs OUT 64 IN 6x70 4 EGs 128 Algorithms Pre-Algorithms CONDITION Chip 4 IEGs 4 central JETs OUT 64 IN 6x70 ALGORITHM AND-OR FPGA CONDITION Chip 4 forw.jets 4 tau-jets FPGA total&missing ET, jet numbers 4 free Front Panel connectors Channel Link Backplane

6 Final Decision Logic board FDL GTFE FrontEnd Card Data Readout + Global Monitoring GTFE Link ROP Readout processor RO-bus Readout Request VME interface TIM Local Monitoring + Tests DPM setup by VME DPM Monitoring COUNTERS GTL 128 ALGORITHM BITS 128 Prescalers Final OR logic 16x L1_ACCEPT(1..16) TCS Trigger Control JTAG

7 Status Global Trigger 09/00 FDL board: Definition of functions ongoing TCS board: Partitioning; definition of functions JTAG software from JTAG Technology infrastructure, interconnection, cluster tests done problems with programming of FPGAs by JTAG PSB module tested: 25% of connections can be tested BGA Solder station for Fine Line BGA (1mm grid) chips 256, 484 pins...ok; 672 pins...tests to find optimal solder parameters

8 Status Global Trigger 09/00 Custom Backplane, PSB input prototype exists GTL-prototype: 4 µ, 4x4 calo channels New structure of the prototype similar as on the final 9U board uniform structure, smaller latency, flexibility, but design more complicated Condition Chips : Each receives 66% of the input channels Conditions, Spatial conditions, Pre-Algorithms, Algorithms Algo Chips: Algorithms VHDL design ==> fixed VHDL code Predefined Templates, Condition types, IO-pins Setup and Placement Software ==> variable VHDL code Wiring of Input Channels and of algorithm bits to output pins Definition of Conditions //Condition types as building blocks. Definition of Algorithm-AND-OR logic // product terms, inversion aim for ===>Automated Chip design Event Generator Software Board layout: Placement, connectors...

9 GTL Condition Chip Design New algorithms change the FPGA logic ==> new FPGA design...every day, week... ==> automated design cycle ==> additional safety margin for latency Predefined TEMPLATES, CONDITIONS =fixed VHDL code ==> tested for worst case (time) Flexible AND-OR structure =variable VHDL code SETUP Program: delivers VHDL code, LUT contents, Output connections Graphic User Interface GUI to program new algorithms version in CVI-environment (National Instrument)

10 Setup- and Placement Program generates VHDL code for the Condition chips Wiring of input channels for 6U prototype boards

11 Event Generator Setup- and Placement Program

12 Condition to find 2 isolated electrons/photons with spatial correlation INPUT REGISTER for IEG1...4_(Et, phi, eta) LUT values for IEG templates: T1, T2, CORR_PHI, CORR_ETA <== Setup file IEG1_PHI IEG1_ETA IEG1_ET IEG1_PHI IEG2_PHI IEG1_ETA IEG2_ETA WCMP5 WCMP4 CMP6 SUB5 SUB4 AND T1 4+4=8 x T2 WCMP6 WCMP5 6 x 6 x intermediate REGISTER AND4_OR12 clock

13 Backplane 6U Prototype VME BUS SWITCH 5bit JTAG Bus 110F Addressable JTAG Port with JTAG Bridge Fairchild SCANPSC110F and Switch 1 loop / board L1 GLOBAL TRIGGER JTAG TESTS Cable from TAP Controller to Backplane JTAG Explorer PM3705/C Cable to Parallel Port JTAG TECHNOLOGY PF2171 Full Development Software

14 component JTAG CLUSTER Memory,.. JTAG component Memory cluster file.mcd FUNCTION Signal Definition file.sdf net name, col#, direction ad03 1 I ad02 2 I : : noe 9 I nwe 10 I Define in- and output signals of cluster Signal Level file.slf address data ctrl DDDD XXXX UU DDDD XXXX DU DDDD HLHL UU normal cluster test Define Function of cluster by test vectors Example: read CLUSTER TESTS

15 BSDL file.sel file data sheet files select components with BSC circuit net info file.nif file Altera, National, TexasInstr., Xilinx... nets locked on defined levels JTAG TEST VIP Manager INFRASTRUCTURE TEST INTERCONNECTION TEST EDIF netlist vl2jtag.net.pkg.wir package, wiring files ViewDraw PCB Schematic //..tests JTAG chain if all components connected //..tests nets between components containing a JTAG circuit.sdf.slf.mcd cluster definition files CLUSTER TEST //..tests nets between components containing a JTAG circuit and components without JTAG Technology SOFTWARE

16 Schedule 2001 GTL-prototype: VHDL design finished and prototype board produced delay Nov 2000 ==> Jan 2001 Software for Design and Tests until March FDL board: Functions defined and top-down design done until Nov FPGA chips designed and FDL board built until Nov GMT : Conceptual design until Nov 2000 define and simulate final algorithms JTAG software and tests: available until Dec 00...already working

17 Milestones 1999, D431 - June 1999 PSB_6U prototype production Status: Board tested. BACK6U design Status: done D432 Nov 1999 milestone changed BACK6U production Status: Board in use. D433 - June 2000 GTL_6U design Status: Delay due to redesign D434 Nov 2000 Trigger Logic Functions tested GTL_6U tested; Status: Delay FDL_9U design Combined logic test: Backplane + PSB + GTL Conceptual GlobalMuon Trigger design D435 - Nov 2001 Complete Logic Pipeline tested Combined Prototype test: Backplane + PSB + GTL+FDL D436 - June channel Global Trigger available D437- Nov 2003 Global Muon Trigger available D438 - Nov channel Global Trigger available

18 LATENCY

19 1/4-1/2 BC 81bx DPM GMT LATENCY min. MUON LATENCY 10 BC..without unit conversion 4DT-4bRPC 4CSC-4fRPC 91bx 160MHz GMT-IN PHASE FPGA Synchronisation MATCH LOGIC PAIR LOGIC MUON MERGER FINAL SORTER GT INPUT Register 4 DT,4 CSC, 8 RPC Muons SINGLE RANK TABLES GMT-LOGIC FPGA SorterFPGA MIP, ISO bits from GCT 75bx Chann Link LATENCY 8 BC PSB module Delay FIFO Ch Link 80MHz PROJ. TABLES Ch Link 83bx MIP, ISO bit ASSIGNMENT PROJECTION FPGA LATENCY 8 BC = combinatorial logic min. ISO/MIP bit LATENCY 16 BC 91bx

20 GT+GMT LATENCY 81 BX 91 BX 99 BX CSC, DT,RPC TRIGGER PARALLEL LINK GLOBAL MUON TRIGGER LATENCY 1 +9 BX SYNC LOGIC 9BX LOGIC + LUT Critical Path PARALLEL LINK Backplane GTL 1BX 1BX 1BX LATENCY 5 BX PARTICLE CONDITIONS 1BX 1BX AND-OR LOGIC CABLE PARALLEL LINK FDL LATENCY 3 BX FINAL OR- LOGIC PARALLEL LINK 85 BX PSB LATENCY 3 BX 88 BX 3 BX 128 ALGORITHMS Latency without Trigger Control System TCS. L1ACCEPT GCT PHASE SYNC PIPELINE DELAY CHANNEL LINK 80 MHz SYNCHRONISATION LOGIC Phase Sync: 1/4-3/4 BX CHANNEL LINK 80 MHz Muon input to L1Accept output: 18 BX Calo input to L1Accept output: 14 BX GCT data later than before ==>PIPELINE DELAY in PSB!!

21 Estimated FDL to TTCvx latency GT PROCESSOR BX=99 BX=100 XXX XXX XXX BX=104 FINAL OR- LOGIC 1 BX PARALLEL LINK Backplane 1 BX MUX TCS TTS Calibration 9 ns* 1 or 2 BX? PARALLEL LINK TP-CABLE <1.5m?7 ns*? TTCvi logic L1A A B 40MHz? MUX, O.L. Encoder 9U VME FDL 9U VME TCS 6U/4TE VME TTCvi 6U/4TE, PECL TTCvx *Driver: = 9 ns FPGA: clk2out 6 ns net on board: 1 ns fast LVDS driver 2ns *Receiver: =?7 ns fast LVDS receiver: 2ns net on board: 1 ns FPGA setup 3 ns 25-16=9ns ==> <1.5 m cable for 1bx transfer latency if CLK signals on TCS and TTCvi switch simultanously. CABLE < 1m DS90LV031A TP cable: 1.6 ns/ft=5.3 ns/m FDL to TTCvx latency