A low jitter clock and data recovery with a single edge sensing Bang-Bang PD

Transcription

1 LETTER IEICE Electronics Express, Vol.11, No.7, 1 6 A low jitter clock and data recovery with a single edge sensing Bang-Bang PD Taek-Joon Ahn, Sang-Soon Im, Yong-Sung Ahn, and Jin-Ku Kang a) Department of Electronics Engineering, Inha University, 253 Yonghyun dong, Nam Gu, Incheon, Korea a) jkang inha ac kr Abstract: This letter describes a low jitter clock and data recovery (CDR) circuit with a modified bang-bang phase detector (BBPD). The proposed PD senses the phase relationship using a single edge of input data to reduce ripples in the VCO control voltage. A 2.5 Gbps CDR circuit with a proposed BBPD has been designed and compared with conventional BBPD using 0.13 μm CMOS technology. Measured results reveal that proposed CDR shows the peak-to-peak jitter of 17 ps on PRBS input pattern compared to 26 ps with the CDR with a conventional BBPD. The proposed CDR can be best applied to 8B10B encoded input data. Power consumption can also be saved by about 3 mw with the proposed BBPD. Keywords: Bang-Bang PD (BBPD), CDR, Alexander PD, jitter, PRBS Classification: Integrated circuits References [1] J. Lee: IEEE J. Solid-State Circuits 39 [9] (2004) [2] D. Rennie and M. Sachdev: International Symposium on Quality Electronic Design (2007) 305. [3] D. Rennie and M. Sachdev: IEEE International Symposium on Circuits and Systems (2007) 185. [4] J.-W. Yoo, D.-K. Kim and J.-K. Kang: ETRI Journal 33 [5] (2011) 752. [5] A. Maxim: ESSCIRC (2002) 423. [6] H.-C. Chow and Z.-H. Hor: IEEE Asia Pacific Conference (2008) Introduction Clock and data recovery (CDR) circuits are used extensively in modern communication systems. The performance of the CDR circuit depends on the structure of the phase detector (PD) used in the CDR significantly. Different types of PDs have been suggested in the literature, and among them, the Alexander PD has been used widely in high-speed applications [1]. However, although the Alexander PD is suitable for high-speed operation, the bang bang characteristic of the binary PD causes the higher charge pump activities than those of linear phase detectors [2]. This results 1

2 in ripples on the VCO control line, even when CDR circuits are locked. The ripples directly translate into jitter at the VCO output. The jittery recovered clock also causes the recovered data signal to have jittery edges, which results in narrowing data eye. In this letter, in order to reduce the ripples on the VCO control line in CDR using a bang-bang PD (BBPD), a modified bang-bang PD is proposed. The proposed BBPD senses the phase relationship using a single edge of input data to reduce ripples in the VCO control voltage. 2 Proposed Bang-Bang Phase Detector A block diagram of a generic CDR circuit using a bang-bang phase detector (BBPD) is shown in Fig. 1 (a). The conventional binary phase detector used in CDR circuits is called as the Alexander BBPD [3]. The Alexander PD is categorized as a bang-bang PD because it only generates information as to whether the clock is leading or lagging the data without giving information about the magnitude of phase error. A block diagram of the conventional Alexander PD is shown in Fig. 1 (b). It is composed of four D flip-flops (DFFs) and two XOR gates [3]. The four DFFs are used to sample the data signal at three different timing points. The two XOR gates work on these samples to determine whether the data signal is leading or lagging behind the clock signal. The conventional BBPD uses three consecutive clock edges to sample the input data as shown in Fig. 1 (b). These samples (Q1, Q2, and Q4) are used to decide whether a data transition is present, and whether the clock signal leads or lags behind the data input. A CLKearly signal (Y1) is generated by the Q1 Q4 operation and a CLK-late signal (X1) is formed by the Q2 Q4 operation. The falling edge of the clock and the data transition edge are compared for early or late decision. Fig. 1. Block diagram of a generic CDR circuit with a bang-bang PD (a), and structure of a conventional Alexander type BBPD (b), and structure of proposed BBPD (c) 2

3 And Q4 is the retimed data signal. The proposed BBPD includes a data retiming mechanism as the Alexander PD. The structure of the proposed BBPD is shown in Fig. 1 (c). Two D flip-flops and one AND gate are used for edge detection and the last two latches serve as a decision circuit. The decision circuit tells whether the clock is leading (Y2) or lagging (X2). And the proposed BBPD generates the retimed data Q2. The proposed BBPD was realized with two latches in the second stage and removed two XOR gates compared to the conventional BBPD. Figure 2 (a) illustrates the operation of a conventional BBPD for a single pulsed data when the clock signal (CLK) is later or earlier than the data timing. The signals at node X1 and Y1 are generated for two clock periods after phase comparison. Fig. 2 (b) shows the timing diagrams of the proposed BBPD for a single pulsed data. As shown in Fig. 2 (b), if a data edge occurs while CLK is high (CLK-late case), the node A (output of AND gate) goes high during a half of the next clock period and the signal at node X2 is high for one clock period from falling edge of CLK. Similarly, if a data edge occurs while CLK is low (CLK-early case), the node A is high during half of the next clock period. Then the node Y2 is high for one clock period from rising edge of CLK. Fig. 2. The operation of (a) the conventional BBPD with a single pulsed data, (b) the proposed BBPD with a single pulsed data, (c) the conventional BBPD with a long consecutive identical data, and (d) the proposed BBPD with a long consecutive identical data As shown in Fig. 2 (a), the conventional BBPD compares the phase between the clock s falling edge and both the rising and falling edge of input data. Therefore, X1 or Y1 output stays high for two clock periods with a single pulsed input data. However, the proposed PD compares the clock s falling edge only with the rising edge of input data for CLK-late case and 3

4 only with the falling edge of input data for CLK-early case, respectively. Therefore X1 or Y1 output stays high for one clock period with a single pulsed input data as shown in Fig. 2 (b). The pulse widths of X2 and Y2 in the proposed BBPD are a half of the pulse widths of X1 and Y1 in the conventional BBPD. Figure 2 (c) and 2 (d) show the timing diagrams for a consecutive identical input data. In conventional BBPD, at X1 and Y1, the output pulse of one clock period occurs twice at the rising edge and the falling edge for a long run data as shown in Fig. 2 (c). In contrast in the proposed PD, at X2 and Y2, the output pulse of one clock period occurs only once either at falling edge or rising edge of input data as shown in Fig. 2 (d). As a result, the proposed PD reduces the PD output pulse width and the number of pulse occurring at the BBPD output and the CDR circuit with the proposed PD can reduce the ripples on the VCO control line when it is locked. Then the reduced control voltage variation will reduce jitter in CDR circuits. Since the proposed BBPD utilizes only a single edge of the data, jitter accumulation effect might be worsened on a long consecutive identical data (CID). In order to evaluate the jitter accumulation effect on the proposed CDR on CID, several different pseudorandom bit sequence (PRBS) input patterns were tested and the measured results are discussed in next section. 3 Measurement result For performance comparison between the conventional Alexander BBPD and the proposed BBPD, the 2.5 Gbps CDR circuits with two different BBPD s with the same charge pumping current are designed. The phase detectors are designed using current mode logic (CML) for supporting the 2.5 Gbps operating speed under 0.13 μm CMOS process. In the VCO delay cell, the load of the differential pair is composed of the PMOS [4]. A unity gain buffer is used to clamp the terminal voltages of the current sources during the zero-current pumping period in the charge pump circuit. This minimizes glitches that occur on the loop filter due to the charge sharing. Figure 3 (a) presents a microphotograph of the chip. Figure 3 (b) and Figure 3 (c) are the measured recovered clock jitter (peak-to-peak) and data eye for the CDR with the proposed BBPD and the conventional BBPD on PRBS pattern, respectively. Figure 3 (d) shows the measured peak-to-peak jitter variations on different PRBS patterns from 2 5 1to Under locked condition, the measured peak-to-peak jitter of the recovered clock is 26 ps on the CDR with conventional BBPD and 17 ps with the proposed BBPD on PRBS input data, respectively. Data eye patterns are also compared and show the better jitter performance on the proposed BBPD case. Since the proposed BBPD utilizes only a single data edge for generating the phase error depending on CLK-early or CLK-late case, jitter accumulation effect might worsen the jitter on a long consecutive identical data (CID). In order to investigate the CID effect on the jitter performance, several different PRBS patterns are applied to two CDR circuits and measured the jitter. The results are shown in Figure 3 (d). As shown the proposed BBPD has an advantage on the jitter performance until PRBS data pattern. This means the jitter accumulation effect devalues the proposed BBPD scheme starting from PRBS data pattern. Therefore the proposed BBPD is best fit for the 4

5 Fig. 3. Measured results: (a) Chip microphotograph (b) Measured recovered clock peak-to-peak jitter and data eye with conventional BBPD (2.5 GHz clock, PRBS pattern) (c) Measured recovered clock jitter and data eye with proposed BBPD (2.5 GHz clock, PRBS pattern) (d) Measured peak-to-peak jitter on different PRBS patterns 8B10B encoded data input for clock and data recovery since the 8B10B encoded data has the maximum 5 consecutive identical bits and is a popular encoded data format in many high-speed serial interface applications. The measured total power consumption of the 2.5 Gbps CDR circuit is about 20 mw with the conventional BBPD, about 17 mw with proposed BBPD with the same pumping current of 25 μa, respectively. 5

6 4 Conclusion In this letter, a novel bang-bang phase detector for CDR circuit is presented. The 2.5 Gbps CDR circuit with the proposed BBPD shows improvements in the jitter and power consumption compared to the CDR with the conventional BBPD on the random data up to PRBS data. Measured results show the CDR circuit using proposed BBPD shows that the peak-to-peak jitter was about 17 ps under PRBS input data, and the total power consumption was 17 mw compared to 26 ps jitter and 20 mw power consumption, respectively. The circuits were designed and fabricated with 0.13 μm CMOS technology. Acknowledgments This work was supported by NRF ( , 2013R1A2A2A ). Authors also thank the IDEC program. 6