Table LDCP codes used by the CLT {EPoC_PMD_Name} PCS for active CCDN

Transcription

1 0... FEC encoding process The {EPoC_PMD_Name} encodes the transmitted using a systematic Low-Density Parity-Check (LDPC) (F C, F P ) code. A LDPC encoder encodes F P information bits into a codeword c = ( i 0,... i FP p FP... p FC ) by adding F R parity bits Hc T = 0 obtained so that where H is an F R F C binary matrix containing mostly 0 and relatively few, called low-density paritycheck matrix. (see [] and []). The detailed description of such parity check matrices is given in 0... {to be included in informative references: [] R. G. Gallager, Low density parity check codes, IRE Trans. Inform. Theory, vol. IT-, pp., Jan..; [] T. Richardson and R. Urbanke, Modern Coding Theory," Cambridge University Press, 00} The CLT {EPoC_PMD_Name} PCS operating on active CCDN shall encode the transmitted using one of the LDPC (FC, FP) codes per Table 0, as selected using register TBD. The CNU {EPoC_PMD_Name} PCS operating on active CCDN shall encode the transmitted using one of the LDPC (FC, FP) codes per Table 0, as selected using register TBD. Table 0 LDCP codes used by the CLT {EPoC_PMD_Name} PCS for active CCDN Codeword F C [bits] p Fp...p FC Payload F P [bits] Annex 0A gives an example of LDPC (F C, F P ) FEC encoding. {we will need to select one of the codes from the family of codes we use in either downstream or upstream and then generate examples} 0... LDPC matrix definition Parity F R [bits] -bit blocks B Q Payload Padding bits B P -bit blocks C Q i 0...i FP Parity Parity bits in last block C PL Padding bits C P The low-density parity check matrix H for LDPC (F C, F P ) encoder can be divided into blocks of L submatrices. Its compact circulant form is represented by an m n block matrix: where the submatrix H i,j is an L L all-zero submatrix or a cyclic right-shifted identity submatrix. The last n m sub-matrix columns represent the parity portion of the matrix. Moreover, nl = F C, ml = F P and the code rate is (n m)/n = (F C F P )/F C. In this specification, the sub-matrix size L is called the lifting factor

2 Table 0 LDCP codes used by the CLT {EPoC_PMD_Name} PCS for active CCDN Codeword F C [bits] Payload F P [bits] Parity F R [bits] -bit blocks B Q Payload Padding bits B P -bit blocks C Q Parity Parity bits in last block C PL Padding bits C P In this specification, the sub-matrix H i,j is represented by a value in {-, 0,, L-}, where a -' value represents an all-zero submatrix, and the remaining values represent an L by L identity submatrix cyclically rightshifted by the specified value. Such representation of the parity-check matrix is called a base matrix. {The following matrices were extracted from as updated. This material with technical changes has not been yet adopted as baseline proposal.} Table 0 a through Table 0 c present a base matrix of the low-density parity-check matrix H for LDPC (00, 00) code listed in TABLE 0- for downstream and TABLE 0- for upstream, respectively. The lifting factor of the matrix is L=0. Row H = H H H H H H H H H Table 0 a LDPC (00, 00) code matrix, columns - Column... H n... H n... H n H m H m H m... H m n

3 Row Table 0 b LDPC (00, 00) code matrix, columns -0 Column Row Table 0 c LDPC (00, 00) code matrix, columns - Column Table 0 a through Table 0 c present a base matrix of the low-density parity-check matrix H for LDPC (0, ) code listed in TABLE 0- for upstream. The lifting factor of the matrix is L=0. Table 0 a LDPC (0, ) code matrix, columns - Row Column Table 0 a and Table 0 c present a 0 base matrix of the low-density parity-check matrix H for LDPC (0, ) code listed in TABLE 0- for upstream. The lifting factor of the matrix is L=

4 Table 0 b LDPC (0, ) code matrix, columns - Row Column Table 0 c LDPC (0, ) code matrix, columns - Row Column Table 0 a LDPC (0, ) code matrix, columns -0 Row Column LDPC encoding process within CLT (downstream) The process of padding FEC codewords and appending FEC parity octets in the {EPoC_PMD_Name} CLT transmitter is illustrated in Figure 0. The B/B encoder produces a stream of -bit blocks, which are then delivered to the FEC encoder. The FEC encoder accumulates B Q (see Table 0-) of these -bit blocks to form the payload of a FEC codeword, removing the redundant first bit (i.e., sync header bit <0>) in each -bit block received from the B/B encoder. The first bit <0> of the sync header in the -bit block in the transmit direction is guaranteed to be the complement of the second bit <> of the sync header see... for more details

5 Table 0 b LDPC (0, ) code matrix, columns -0 Row Column Next, the FEC encoder calculates CRC over the aggregated B Q -bit blocks, placing the resulting bits of CRC code prepended with one bit truncated sync header (with the binary value of ) immediately after the B Q -bit blocks, forming the payload of the FEC codeword. Finally, the FEC encoder prepends B P (see Table 0 ) padding bits (with the binary value of 0 ) to the payload of the FEC codeword as shown in Figure 0. This is then LDPC-encoded, resulting in the F R bits of parity. The first bits of parity are inserted into the -bit block carrying CRC code, complementing it. The remaining F R- bits of parity is then divided into C Q -bit blocks, each of which is then prepended with one bit sync header <> with the value of binary. The last -bit block of the parity contains C PL bits of parity, and the remaining C P bits are filled with padding (binary 0 )

6 TXD<0> sync header 0 first XGMII transfer Input for FEC encoder (F P bits) FEC parity Figure 0 PCS Transmit bit ordering within CLT (downstream) 0... LDPC codeword transmission order within CLT (downstream) TXD<> D0 D D D D D D D B/B Encoder C0 C C C C C C C C0 C C C C C C C -bit block -bit block -bit block FEC payload Aggregate B Q B-blocks & Calculate CRC -bit block B Q LDPC Encoder B W padding bits Once the process of calculating FEC parity is complete, the payload portion of the FEC codeword and the parity portion of the FEC codeword are then transferred towards the PMA across the PMA service interface, one -bit block at a time. Note that the B P padding bits used to generate the FEC codeword are not transmitted across the PMA service interface. The C P padding bits in the last parity codeword (block number C Q ) are transmitted to PMA, where they are the discarded prior to encoding into OFDM medium. TXD<0> PMA -bit block B Q- -bit block CRC parity second XGMII transfer -bit block B Q -bit block parity CRC TXD<> -bit block C Q parity pad CPL CP

7 0... LDPC encoding process within CNU (upstream) {the upstream FEC encoding for CNU will be described when we have a consistent proposal on how to mix three different FEC codes into a single transmission slot} 0... LDPC codeword transmission order within CNU (upstream) {the content of this subclause ought to be quite similar with the content of 0...} 0... State diagrams 0... Constants B Q C P C Q F P F R VALUE: see Table 0 for downstream FEC, Table 0 for upstream FEC This constant represents the number of -bit blocks within the payload portion of the FEC codeword. VALUE: see Table 0 for downstream FEC, Table 0 for upstream FEC This constant represents the number of padding bits within the last -bit block of the parity portion of the FEC codeword. VALUE: see Table 0 for downstream FEC, Table 0 for upstream FEC This constant represents the number of -bit blocks within the parity portion of the FEC codeword. VALUE: see Table 0 for downstream FEC, Table 0 for upstream FEC This constant represents the number of bits within the payload portion of the FEC codeword. VALUE: see Table 0 for downstream FEC, Table 0 for upstream FEC This constant represents the number of bits within the parity portion of the FEC codeword Variables blockcount TYPE: -bit unsigned integer This variable represents the number of blocks (either -bit or -bit blocks, depending on the state diagram). CLK TYPE: Boolean This Boolean is true on every negative edge of TX_CLK (see..) and represents instances of time at which a -bit block is passed from the output of the B/B encoder into the FEC encoder. This variable is reset to false upon read. Payload<F P -:0> TYPE: Bit array This array represents the payload portion of the FEC codeword, accounting for the necessary padding. It is initialized to the size of F P bits and filled with the binary value of 0. Parity<F R -+C P :0> TYPE: Bit array 0 0 0

8 This array represents the parity portion of the FEC codeword, accounting for the necessary padding. It is initialized to the size of F R + C P bits and filled with the binary value of 0. FIFO_FEC TYPE: Array of -bit blocks A FIFO array used to store tx_coded<:> blocks, inserted by the input process in the FEC encoder, while FEC parity is sent out towards PMA. loc TYPE: -bit unsigned integer This variable represents the position within the bit array, indicating how much is stored within the given bit array. rx_coded_in<:0> TYPE: -bit block This -bit block contains the input of the FEC decoder being received from PMA. The leftmost bit is rx_coded_out<0> and the right-most bit is rx_coded_out<>. sizefifo TYPE: -bit unsigned integer This variable represents the number of -bit blocks stored in FIFO_FEC. tx_coded<:0> TYPE: -bit block This -bit block contains B/B encoded. The format for this block is shown in Figure. The left-most bit in the figure is tx_coded<0> and the right-most bit is tx_coded<>. tx_coded_out<:0> TYPE: -bit block This -bit block contains the output of the FEC encoder being passed into PMA. The leftmost bit is tx_coded_out<0> and the right-most bit is tx_coded_out<> Functions calculatecrc ( ARRAY_IN ) This function calculates CRC for included in ARRAY_IN. calculateparity( ARRAY_IN ) This function calculates LDPC parity (for the code per Figure 0 or Figure 0 ) for included in ARRAY_IN. resetarray( ARRAY_IN ) This function resets the content of ARRAY_IN, setting all the elements in this array to the binary value of 0. removefifohead( FIFO_IN ) This function removes the first block in FIFO_IN and decrements the variable sizefifo by. removefifohead( FIFO_IN ) { FIFO_IN[0] = FIFO_IN[] FIFO_IN[] = FIFO_IN[]... FIFO_IN[sizeFifo-] = FIFO_IN[sizeFifo-] sizefifo -- } 0 0 0

9 0... Messages TBD 0... State diagrams The CLT PCS shall implement the LDPC encoding process, comprising the input process as shown in Figure 0 and the output process as shown in Figure 0. The CNU PCS shall implement the LDPC encoding process, comprising the input process as shown in Figure 0 and the output process as shown in Figure 0. In case of any discrepancy between state diagrams and the descriptive text, the state diagrams prevail. BEGIN WAIT_FOR_BLOCK AGGREGATE_BLOCK tx_coded<:0> * (tx_coded<:0> = SH_DATA + tx_coded<:0> = SH_CTRL) FIFO_FEC[sizeFifo] tx_coded<:> sizefifo ++ UCT INIT sizefifo 0 Figure 0 FEC encoder, input process state diagram 0 0 0

10 CLK * blockcount < BQ 0... FEC decoding process BEGIN RESET loc 0 blockcount 0 resetarray( Payload ) resetarray( Parity ) Figure 0 FEC encoder, output process state diagram (CLT) The {EPoC_PMD_Name} decodes the received using LDPC (F C, F P ) code. The CLT {EPoC_PMD_Name} PCS operating on active CCDN shall decode the received using one of the LDPC (F C, F P ) codes per Table 0, as selected using register TBD. The CNU {EPoC_PMD_Name} PCS oper- UCT CLK * blockcount = B Q Payload<loc+:loc> calculatecrc( Payload<loc-:0> ) Parity calculateparity( Payload ) tx_coded_out<:0> Payload<loc+:loc> tx_coded_out<:> Parity<:0> loc blockcount 0 CLK * blockcount < CQ INIT AGGREGATE_B Q _BLOCKS Payload<loc+:loc> FIFO_FEC_TX[0] tx_coded_out<:0> FIFO_FEC_TX[0] removefifohead( FIFO_FEC_TX ) loc += blockcount ++ CALCULATE_CRC_AND_PARITY SEND_PARITY CLK CLK tx_coded_out<:0> Parity<loc+:loc> tx_coded_out<:> loc += blockcount ++ CLK * blockcount = C Q 0 0 0

11 ating on active CCDN shall decode the received using one of the LDPC (F C, F P ) codes per Table 0, as selected using register TBD. Annex 0B gives an example of LDPC (F C, F P ) FEC decoding. {we will need to select one of the codes from the family of codes we use in either downstream or upstream and then generate examples} 0... LDPC decoding process within CLT (upstream) {the upstream FEC decoding for CLT will be described when we have a consistent proposal on how to mix three different FEC codes into a single transmission slot} 0... LDPC decoding process within CNU (downstream) The process of decoding FEC codewords in the {EPoC_PMD_Name} CNU receiver is illustrated in Figure 0-. {FEC codeword alignment needs to be tackled somewhere between the PMA and the bottom of the PCS we had some proposals on how to find FEC codeword lock in the downstream, but I am not sure we baselined anything with sufficient level of detail to actually put it into the draft} Once the alignment to FEC codeword is found, the {EPoC_PMD_Name} CNU receiver aggregates the total of B Q + + C Q -bit blocks received from the PMA, forming the FEC payload (blocks number to B Q, and bits <0> through <> from the following -bit block) and the FEC parity (bits <> through <> from the -bit block following payload portion of the FEC codeword and followed by blocks number to 0 0 0

12 C Q ) portions of the codeword. Note that the CP padding bits in the last parity codeword (block number C Q ) are locally generated within the PMA and transmitted to the PCS. TXD<0> sync header B W padding bits 0 first XGMII transfer TXD<> D0 D D D D D D D B/B Decoder C0 C C C C C C C C0 C C C C C C C B W padding bits -bit block -bit block -bit block FEC payload Verify CRC & Extract B Q B-blocks Input for FEC decoder (F P bits) -bit block B Q LDPC Decoder FEC parity Figure 0 PCS Transmit bit ordering within CLT (downstream) Next, each -bit block in the FEC parity portion of the codeword (blocks through C Q ) is stripped from the sync header by removing bit <>. Furthermore, the last -bit block of the FEC parity (block number C Q ) is truncated, removing bits <C PL > <>, forming a single FEC parity portion of the codeword with size F R (in bits). Then the FEC payload portion of the codeword is prepended with B P padding bits (with the binary value of 0 ) and subsequently fed into the FEC decoder for processing together with the stripped FEC parity portion of the codeword. TXD<0> -bit block CRC parity PMA second XGMII transfer -bit block B Q- -bit block parity -bit block B Q CRC TXD<> -bit block C Q parity pad CPL CP 0 0 0

13 The FEC decoder produces the FEC payload portion of the codeword with the size of F P (in bits), where bits <0> <B P -> contain padding (with the binary value of 0 ). Next, the CRC is calculated over the remaining blocks through B Q and then compared with the value of CRC retrieved from the received FEC codeword. If both CRC codes match, the decoded frame does not contain any detectable errors and it is treated as error-free. Otherwise, the decoded frame contains detected errors. The behavior of the FEC decoder in the presence of CRC code failure depends on status of the user-configurable option to indicate an uncorrectable FEC codeword. Finally, the FEC decoder prepends each of the B Q -bit blocks with bit <0> of the sync header containing the binary inverse of the value carried in bit <> of the sync header, producing -bit blocks. This also guarantees that properly decoded blocks meet the requirements of... The FEC decoder in the CNU shall provide a user-configurable option to indicate an uncorrectable FEC codeword (due to an excess of symbols containing errors) to higher layers. If this user-configurable option is enabled and the calculated value of CRC does not match the value of CRC retrieved from the received FEC codeword, the FEC decoder replaces bit <0> and <> in the sync headers in all B Q blocks with the binary value of 00. If this user-configurable option is disabled, the FEC decoder does not make any further changes to the sync headers in all B Q blocks. Each resulting -bit block is then fed into the B/B decoder, removing the sync header information (bit <0> and bit <>), which is used to generate control signaling for the XGMII. Finally, the resulting -bit block is then separated into two -bit portions, which are transmitted across the XGMII on two consecutive transfers, with the proper control signaling retrieved from the sync header information retrieved in the B/B decoder State diagrams 0... Constants B Q see 0... B W VALUE: see Table 0 for downstream FEC, Table 0 for upstream FEC This constant represents the number of padding bits within the payload portion of the FEC codeword. C Q see 0... IDLE TYPE: -bit vector This constant represents /I/ character with B/B encoding, as defined in Variables blockcount see 0... CLK see 0... Parity<:0> TYPE: Bit array This array represents the CRC. It is initialized to the size of bits and filled with the binary value of

14 In<F C +C P -:0> TYPE: Bit array This array represents the combination of the payload portion of the FEC codeword, the parity portion of the FEC codeword, CRC, and all the necessary padding. It is initialized to the size of F C +C P bits and filled with the binary value of 0. Out<F P -:0> TYPE: Bit array This array represents the combination of the payload portion of the FEC codeword, CRC, and all the necessary padding. It is initialized to the size of F P bits and filled with the binary value of 0. FIFO_FEC_RX TYPE: Array of -bit blocks A FIFO array used to store tx_coded<:0> blocks, inserted by the input process in the FEC decoder, while encoded is then sent to B/B decoder for processing and transmission towards the XGMII. loc see 0... rx_coded_in<:0> TYPE: -bit block This -bit block contains the input into the FEC decoder being passed from PMA. The leftmost bit is rx_coded_in<0> and the right-most bit is rx_coded_in<>. sizefifo syncfec see 0... TYPE: Boolean This variable indicates whether the FEC codeword alignment was found (value equal to true) or not (value equal to false). tx_coded<:0> see Functions calculatecrc ( ARRAY_IN ) see 0... decodefec( ARRAY_IN ) This function performs FEC decoding (for the code per Figure 0 or Figure 0 ) for included in ARRAY_IN. resetarray( ARRAY_IN ) see Messages TBD 0... State diagrams The CNU PCS shall implement the LDPC decoding process, comprising the input process as shown in Figure 0 and the output process as shown in Figure

15 In case of any discrepancy between state diagrams and the descriptive text, the state diagrams prevail. blockcount < BQ CLK * blockcount < (BQ+CQ+) BEGIN loc B W blockcount 0 resetarray( In ) resetarray( Out ) Out decodefec( In<F C+C P:0> ) Crc calculatecrc( Out<F P-:B W> ) loc 0 blockcount 0 Crc!= In<F P-:F P-> DECODE_FAIL tx_coded<:0> tx_coded<:> Out<B W+loc+:B W+loc+> FIFO_FEC_RX[sizeFifo] tx_coded<:0> sizefifo ++ loc += blockcount ++ decodefailure ++ sizefec 0 CLK * syncfec = true INIT RESET Figure 0 FEC decoder, input process state diagram (CNU) UCT AGGREGATE_B Q _C Q _BLOCKS In<loc+:loc> rx_coded_in<:0> loc += blockcount ++ DECODE_CALCULATE_CRC blockcount = B Q CLK * blockcount = (B Q+C Q+) Crc = In<F P-:F P-> DECODE_SUCCESS tx_coded<0:0>!out<b W+loc:B W+loc> tx_coded<:> Out<B W+loc+:B W+loc> FIFO_FEC_RX[sizeFifo] tx_coded<:0> sizefifo ++ loc += blockcount ++ blockcount = B Q blockcount < BQ 0 0 0

16 CLK * sizefec = 0 SEND_OUT_BLOCK tx_coded<:0> IDLE UCT BEGIN INIT WAIT_FOR_BLOCK UCT CLK * sizefec!= 0 SEND_OUT_BLOCK tx_coded<:0> FIFO_FEC_RX[0] removefifohead( FIFO_FEC_RX ) UCT Figure 0 FEC decoder, output process state diagram (CNU)