Exceeding the Limits of Binary Data Transmission on Printed Circuit Boards by Multilevel Signaling

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1 Exceeding the Limits of Binary Data Transmission on Printed Circuit Boards by Multilevel Signaling Markus Grözing, Manfred Berroth INT, in cooperation with Michael May Agilent Technologies, Böblingen Prof. Dr.-Ing. Manfred Berroth 1

2 Outline Motivation Backplane channel characteristics Multilevel penalty versus multilevel benefit Transmitter & receiver equalization Simulation of PAM 2 / PAM 4 transmission Conclusions & Outlook 2

3 Motivation Computer mass market, i.e. processor memory interface DDR3 ~ 1 Gbit/s FBDIMM 4.8 Gbit/s tomorrow: 7 to 20 Gbit/s Cables transmission length: 2 to 20 cm Backplanes, multi-chip modules, i.e. i.e. HDMI Gbit/s network cross connects, mainframes today: few Gbit/s tomorrow: > 10 Gbit/s transmission length: up to 1m Optical networks, i.e. LAN, MAN and WAN today: 2,5 to 10 Gbit/s tomorrow: 40 to 100 Gbit/s trans. length: 10 m to 1000 km 3

4 Backplane channel characteristics time & frequency domain 4

5 FR4 Backplane (Illustration similar to measured backplane) 10 GbE XAUI = 2x 4x Gbit/s 2x 2in (daughter card) + 30in (backplane) = 34in = 86cm Backplane-Illustration from Analysis of Backplanes, Stephen Anderson, Xilinx, Minneapolis, OIF-Contribution Number: OIF , Working Group: PLL 5

6 12-Port S-Parameters: Port Definition Differential ports Single ended ports Single ended ports Differential ports Illustration from: Minimizing Multiple Aggressor Differential Crosstalk in High Speed Interconnects using Measurement-based Modeling, Mike Resso, Agilent Technologies 6

7 6-Port differential S-Parameters of 86cm Traces Insertion Loss Return Loss FEXT NEXT 7

8 Transmission Characteristic of 86cm Trace m1: IL (1.67 GHz) = 8.9 db m2: IL (3.33 GHz) = 22.5 db m3: IL (5.00 GHz) = 27.1 db S 43 [db] m4: IL (6.67 GHz) = 54.6 db Frequency [GHz] 8

9 Unit Pulse (1V, 1T) -Response of 86 cm Trace T=300 ps 3.33 Gbaud voltage [mv] T=150ps 6.67 Gbaud T=75ps Gbaud time [ns] 9

10 Multilevel penalty versus Multilevel benefit 10

11 Multilevel Penalty Example: 20 Gbit/s, 0.5 V pp 50 ps 1/2 V PAM Signal Power Eye Area ps 1/6 V 4 Penalty 1 / db 2 / db Picture of PAM4-Eye-Measurement from Proposals for CEI25 Channels Based on lower-k Dielectric Materials for Backplanes and Daughterboards, Helmut Preisach, Alcatel Lucent, Stuttgart, OIF-Contribution Number: OIF , Working Group: PLL 11

12 Multilevel Benefit: Consider f Nyquist Gbit/s PAM4 = 10 Gbaud 20 Gbit/s PAM2 = 20 Gbaud S21 [db] Overall SNR gain Multilevel SNR loss (9,5 db) SNR gain due to reduced symbol rate -40 Noise Level SNR new SNR old NEXT FEXT Thermal Noise -50 0,0E+00 2,0E+09 4,0E+09 6,0E+09 8,0E+09 1,0E+10 frequency [Hz] 12

13 Transmitter & Receiver Equalization FIR-filter (FFE) in transmitter FIR FIR-filter in transmitter DFE in receiver FIR+DFE 13

14 Transmitter & Receiver Equalization FIR-filter transmitter electrical channel FIR-filter receiver DFE receiver data in FIR FIR DFE data out clock FIR FIR DFE T T T T T T T T c 0 c 0 c -1 c -1 c 1 digital domain c -2 analog domain c -2 c 2 digital domain 14

15 1 Re f 2 Example of Simulation Setup in ADS TRANSIENT Tran Tran2 StopTime=10.0 nsec MaxTimeStep=1.0 psec TRANSIENT Tran Tran1 StopTime=30.0 nsec MaxTimeStep=1.0 psec VtLFSR_DT SRC7 Vlow= -e_1 V Vhigh=e_1 V Rate=10 GHz Delay=0.5 nsec Taps= bin(" ") Seed= bin(" ") Rout=1 Ohm VtLFSR_DT SRC4 Vlow= -e_0 V Vhigh=e_0 V Rate=10 GHz Delay=0.4 nsec Taps= bin(" ") Seed= bin(" ") Rout=1 Ohm VtLFSR_DT SRC13 Vlow= -e3 V Vhigh=e3 V Rate=10 GHz Delay=0.1 nsec Taps= bin(" ") Seed= bin(" ") Rout=1 Ohm VtLFSR_DT SRC14 Vlow= -e4 V Vhigh=e4 V Rate=10 GHz Delay=0.0 nsec Taps= bin(" ") Seed= bin(" ") Rout=1 Ohm Var Eqn VAR VAR1 e_1= 0 e_0= 4.0 e1= 0 e2= 0 e3= 0 e4= 0 DT DT DT DT DT DT R R1 R=50 Ohm Var Eqn VAR VAR2 e_1= e_0= 4.0 e1= 0 e2= 0 e3= 0 e4= 0 L L1 L=0.25 nh R= VtLFSR_DT SRC6 Vlow=-e1 V Vhigh=e1 V Rate=10 GHz Delay=0.3 nsec Taps= bin(" ") Seed= bin(" ") Rout=1 Ohm VtLFSR_DT SRC8 Vlow=-e2 V Vhigh=e2 V Rate=10 GHz Delay=0.2 nsec Taps= bin(" ") Seed= bin(" ") Rout=1 Ohm InOrg Var Eqn VAR VAR3 e_1= e_0= 4.0 e1= e2= 0 e3= 0 e4= 0 C C2 C=0.35 pf Var Eqn VtPulse SRC18 Vlow= -1 V t Vhigh=1 V Delay=0.0 psec Edge= cosine Rise=1 psec Fall=1 psec Width=99 psec Period=10 nsec VAR VAR4 e_1= e_0= 4.0 e1= e2= e3= 0 e4= 0 VCVS SRC5 G=1 R1=50 Ohm R2=50 Ohm Var Eqn In VtPulse SRC21 Vlow=0 V Vhigh=e_0 V Delay=0.4 nsec Edge= cosine Rise=1 psec Fall=1 psec Width=99 psec Period=10 nsec VtPulse SRC23 Vlow=0 V Vhigh=e2 V Delay=0.2 nsec Edge= cosine Rise=1 psec Fall=1 psec Width=99 psec Period=10 nsec VtPulse SRC24 Vlow=0 V Vhigh=e4 V Delay=0.0 nsec Edge= cosine Rise=1 psec Fall=1 psec Width=99 psec Period=10 nsec VAR VAR5 e_1= e_0= 4.0 e1= e2= e3= e4= 0 S2P SNP1 File= "DD_2N" Var Eqn Var Eqn VAR VAR7 e_1= 0 e_0= 4.0 e1= e2= 0 e3= 0 e4= 0 Out VtPulse SRC22 Vlow=0 V t Vhigh=e_1 V Delay=0.5 nsec Edge= cosine Rise=1 psec Fall=1 psec t Width=99 psec Period=10 nsec VtPulse SRC20 Vlow=0 V t Vhigh=e1 V Delay=0.3 nsec Edge= cosine Rise=1 psec Fall=1 psec t Width=99 psec Period=10 nsec VtPulse SRC25 Vlow=0 V t Vhigh=e3 V Delay=0.1 nsec Edge= cosine Rise=1 psec Fall=1 psec t Width=99 psec Period=10 nsec VAR VAR6 e_1= e_0= 4.0 e1= e2= e3= e4= VSum R SUM1 R2 R=50 Ohm Vback Var Eqn VDFE VAR VAR8 e_1= 0 e_0= 4.0 e1= e2= e3= 0 e4= 0 VSum SUM6 Var Eqn SampleHoldSML SAMP5 Fnom=0 Hz Vhold SampleHoldSML SAMP1 Fnom=0 Hz VSum SUM2 VSum SUM4 VAR VAR9 r1=0.174 r2=0.076 r3=0.040 r4=0 r5=0 r6=0 r7=0 r8=0 r9=0 OutHold Clock Comparator CMP2 Vlow=0.0 V Vhigh=100 V VSum SUM3 VSum SUM5 Var Eqn VAR VAR10 r1=0.174 r2=0.076 r3=0.040 r4=0.013 r5=0.022 r6=0.012 r7=0 r8=0 r9=0 V_DC SRC16 Vdc=0.5 V VMult MULT1 VMult MULT2 VMult MULT3 VMult MULT4 VMult MULT5 VMult MULT6 VtPulse SRC17 Vlow=0 V Vhigh=1 V Delay=81.1 psec Edge= cosine Rise=1 psec Fall=1 psec Width=50 psec Period=100 psec VCVS SRC15 G=2 V_DC SRC26 Vdc=-r1 V V_DC SRC27 Vdc=-r2 V V_DC SRC28 Vdc=-r3 V V_DC SRC32 Vdc=-r4 V V_DC SRC31 Vdc=-r5 V V_DC SRC30 Vdc=-r6 V VtPulse SRC29 Vlow=1 V Vhigh=0 V Delay=81.1 psec Edge= cosine Rise=1 psec Fall=1 psec Width=50 psec Period=100 psec Vback3 Vcomp Vback1 Vback2 t t SampleHoldSML SAMP2 Fnom=0 Hz SampleHoldSML SAMP3 Fnom=0 Hz SampleHoldSML SAMP4 Fnom=0 Hz SampleHoldSML SAMP8 Fnom=0 Hz SampleHoldSML SAMP7 Fnom=0 Hz SampleHoldSML SAMP6 Fnom=0 Hz 15

16 Transmitter Swing Limit Peak voltage at transmitter is limited T T T c 0 c -1 c -2 k c = i i= 0 V max Peak voltage at transmitter set to ± 1 V in all simulations (1-norm of FFE equalization vector = 2) 16

17 Simulation of PAM 2 / PAM 4 transmission with FIR / FIR+DFE 3.33 Gbit/s 6.67 Gbit/s Gbit/s Gbit/s 17

18 Eye Quality Measures Eye Area [in pvs] A ~ ½ * T open * V open µ H (~ integrated charge on decision latch input ) V open T open µ L Eye Quality factor (= signal-to-noise ratio at optimum sampling time) BER estimation from Q-factor (assuming Gaussian distribution of sampled voltage, is too conservative in most cases) Q = µ σ H H BER = µ + σ e L L Q 2 2 Q 2π 18

19 Transmission Characteristic of 86cm Trace m1: IL (1.67 GHz) = -8.9 db m2: IL (3.33 GHz) = db Insertion Loss [db] m3: IL (5.00 GHz) = db m4: IL (6.67 GHz) = db Frequency [GHz] 19

20 86 cm 3.33 Gbit/s PAM2 (no equalization) horizontal eye opening vertical eye opening eye area eye quality factor Q estimated optimum BER UI mv pvs x

21 86 cm 3.33 Gbit/s PAM2 FIR (0 Pre-, 1 Post-FIR-Tap) Preemphasis horizontal eye opening vertical eye opening eye area eye quality factor Q estimated optimum BER UI mv pvs x

22 Summary 3.33 Gbit/s 86 cm Quality Measure V open T open A open Q EQ Taps PAM [mv] [ps] [pvs] FIR 1 post

23 86 cm 6.67 Gbit/s PAM2 FIR (no equalization) horizontal eye opening vertical eye height eye quality factor Q estimated optimum BER UI mv

24 86 cm 6.67 Gbit/s PAM2 FIR (0 Pre-, 1 Post-FIR-Tap) Preemphasis horizontal eye opening vertical eye opening eye area eye quality factor Q estimated optimum BER UI mv pvs x

25 86 cm 6.67 Gbit/s PAM2 FIR (1 Pre-, 1 Post-FIR-Taps) horizontal eye opening vertical eye opening eye area eye quality factor Q estimated optimum BER UI mv pvs x

26 86 cm 6.67 Gbit/s PAM2 FIR (2 Pre-, 3 Post-FIR-Taps) horizontal eye opening vertical eye opening eye area eye quality factor Q estimated optimum BER UI mv pvs x

27 86 cm 6.67 Gbit/s PAM2 FIR+DFE (2 Pre-FIR-, 4 DFE-T.) horizontal eye opening vertical eye opening eye area eye quality factor Q estimated optimum BER UI mv pvs x

28 86 cm 6.67 Gbit/s PAM2 FIR+DFE (3 Pre-FIR, 9 DFE-T.) horizontal eye opening vertical eye opening eye area eye quality factor Q estimated optimum BER UI mv pvs x

29 86 cm 6.67 Gbit/s PAM4 FIR (no equalization) horizontal eye opening vertical eye height eye quality factor Q estimated optimum BER UI mv

30 86 cm 6.67 Gbit/s PAM4 FIR (1 Pre-, 1 Post-FIR-Tap) horizontal eye opening vertical eye opening eye area eye quality factor Q estimated optimum BER UI mv pvs x

31 86 cm 6.67 Gbit/s PAM4 FIR (2 Pre-, 3 Post-FIR-Taps) horizontal eye opening vertical eye opening eye area eye quality factor Q estimated optimum BER UI mv pvs x

32 86 cm 6.67 Gbit/s PAM4 FIR+DFE (2 Pre-FIR-, 4 DFE-T.) horizontal eye opening vertical eye opening eye area eye quality factor Q estimated optimum BER UI mv pvs x

33 86 cm 6.67 Gbit/s PAM4 FIR+DFE (3 Pre-FIR-, 9 DFE-T.) horizontal eye opening vertical eye opening eye area eye quality factor Q estimated optimum BER UI mv pvs x

34 Summary 6.67 Gbit/s 86 cm Quality Measure V open T open A open EQ Taps PAM [mv] [ps] [pvs] FIR 1 pre post FIR 2 pre post FIR DFE FIR DFE Q

35 86 cm Gbit/s PAM2 FIR (2 Pre-, 4 Post-FIR-Taps) horizontal eye opening vertical eye height eye quality factor Q estimated optimum BER UI mv x

36 86 cm Gbit/s PAM2 FIR+DFE (4 Pre-FIR-, 9 DFE-T.) horizontal eye opening vertical eye height eye quality factor Q estimated optimum BER UI mv x

37 86 cm Gbit/s PAM4 FIR (2 Pre-, 3 Post-FIR-Taps) horizontal eye opening vertical eye opening eye area eye quality factor Q estimated optimum BER UI mv pvs x

38 86 cm Gbit/s PAM4 FIR+DFE (3 Pre-FIR-, 9 DFE-T.) horizontal eye opening vertical eye opening eye area eye quality factor Q estimated optimum BER UI mv pvs x

39 Summary Gbit/s 86 cm Quality Measure V open T open A open EQ Taps PAM [mv] [ps] [pvs] FIR 2 pre 4 post FIR 2 pre 3 post FIR 4 +DFE FIR 3 +DFE Q

40 34 in Gbit/s PAM2 FIR (19 FIR-Taps) horizontal eye opening vertical eye height eye quality factor Q estimated optimum BER ps mv x

41 86 cm Gbit/s PAM2 FIR+DFE (4 Pre-FIR-, 9 DFE-T.) horizontal eye opening vertical eye height eye quality factor Q estimated optimum BER UI mv x

42 86 cm Gbit/s PAM4 FIR (2 Pre-, 3 Post-FIR-Taps) horizontal eye opening vertical eye opening eye area eye quality factor Q estimated optimum BER UI mv pvs x

43 86 cm Gbit/s PAM4 FIR+DFE (3 Pre-FIR-, 9 DFE-T.) horizontal eye opening vertical eye opening eye area eye quality factor Q estimated optimum BER UI mv pvs x

44 EQ FIR Summary Gbit/s 86 cm Quality Measure V open T open A open Taps PAM [mv] [ps] [pvs] Q 2.3 FIR FIR +DFE FIR +DFE 2 pre 3 post

45 Summary PAM X / EQ versus Bit Rate Bit Rate [Gbit/s] f bit /2 [db] Modul. EQ-Meth. none +/ PAM 2 FIR FIR+DFE + Overkill PAM 4 FIR FIR+DFE Overkill Overkill

46 Conclusion: Multilevel Benefit! Insertion f bit /2: ~ 10 db: PAM 2 w/o any equalization PAM 2 with FIR (1-tap, preemphasis) ~ 20 db: PAM 2 with FIR, PAM 2 with FIR+DFE PAM 4 with FIR PAM 4 with FIR+DFE ~ 30 db: PAM 4 with FIR PAM 4 with FIR+DFE ~ 40 db: PAM 4 with FIR+DFE Benefit 1: for low loss channels f bit /2 < ~25 db PAM 4 offers better eye opening with less equalization effort Benefit 2: for high loss channels f bit /2 > ~25 db transmission only possible with PAM 4 46

47 Summary Residual ISI after limited/non-ideal equalization is the most important limiting factor for the possible backplane transmission throughput Equalization is a MUST for PAM4-transmission, too, but the EQ-effort may be lower than for PAM2 PAM4 clearly offers the potential for an increase in transmission throughput FFE+DFE PAM4 offers the largest throughput Main challenges for real-world-implementation: PAM4-DFE-circuit implementation at high speed PAM4 needs transmission-amplitude dependant decision levels 47

48 48

49 BACK UP Decision Latch Sensitivity 49

50 90 nm CMOS Decision Flip-Flop Layout _V CLK I Bias V D Q D Q in,d A=1 V out,d CLK _CLK _V in V out V in _V out V CLK V SS 50

51 90nm CMOS Flip-Flop: Measured Phase Margin mv Single-ended input voltage swing as parameter phase margin [degrees] mv 50 mv 100 mv 35 mv decision latch requires ~ 2.5 pvs diff,pp input eye area for error-free operation 400 mv 300 mv f Toggle = f 5, 10 Gbit/s. f Toggle = ¼ f 20, 30, 40 Gbit/s Phase margin 10 GHz: 200 mv input bit rate [Gbit/s] 50 mv 51

52 BACK UP Simulations with Crosstalk 52

53 Differential NEXT & FEXT w/4-port VNA Modified illustration from Minimizing Multiple Aggressor Differential Crosstalk in High Speed Interconnects using Measurement-based Modeling, Mike Resso, Agilent Technologies 53

54 86 cm 6.67 Gbit/s FFE PAM2 +NEXT w NEXT w/o NEXT horizontal eye opening UI vertical eye height mv eye quality factor Q estimated optimum BER 1 x x

55 86cm 6.67 Gbit/s FFE+DFE PAM2 +NEXT w NEXT w/o NEXT horizontal eye opening UI vertical eye height mv eye quality factor Q estimated optimum BER 1 x x

56 86cm 13.3 Gbit/s FFE+DFE PAM4 +NEXT w NEXT w/o NEXT horizontal eye opening UI vertical eye height mv eye quality factor Q estimated optimum BER 8 x x

57 Back UP Channel capacity limiting factors 57

58 Channel Capacity Limiting Factors 1. Residual ISI after limited, non-ideal equalization 2. Crosstalk near-end (NEXT) and far-end (FEXT) 3. Circuit deficiencies duty cycle distortion, resolution and offset of deciders 4. Timing jitter transmitter and receiver 5. Thermal noise transmitter & receiver circuitry, termination resistors 58

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