SATA-IO Interoperability and Technical Training November 15, 2010

Transcription

1 SATA-IO Interop and Technical Training SATA-IO Interoperability and Technical Training November 15, 2010 Join us for food, drinks, and demos from our sponsors after the training ends. Sponsored by: 1

2 IW #9 & Plugfest #14 Event Overview & What s New With The UTD ? November 15, 2010 Tim Mostad Logo Workgroup Technical Program Manager 2

3 Welcome 9th Interoperability Workshop &14th Plugfest put on by SATA-IO 44 attendees 30 companies (22 total PF test teams, 8 IW products) 13 roaming test teams 9 stationary test suites Our sponsors: 3

4 Agenda Event Timeline Logo Definitions Overviews of the IW and Plugfest What s New With UTD ? IW Product Handling Rules General Reminders After the IW 4

5 Event Timeline Monday, November 15, :00 a.m. - 9:30 a.m. Name badges and schedules 9:00 a.m. - 12:00 p.m. Technical training 12:00 p.m. - 1:00 p.m. Hosted Lunch 1:00 a.m. - 3:30 p.m. Technical training continued 3:30 p.m. SATA-IO hosted reception (free drinks and appetizers!) Plugfest : Testing Tue-Wed 60-min timeslots Tuesday, November 16 8:00 a.m. - 12:00 p.m. Test Sessions (IW only) 9:00 a.m. - 12:00 p.m. Plugfest Test Sessions 12:00 p.m. - 1:00 p.m. Hosted Lunch 1:00 p.m. - 5:00 p.m. Test Sessions Wednesday, November 17 8:00 a.m. - 12:00 p.m. Test Sessions (IW only) 9:00 a.m. - 12:00 p.m. Plugfest Sessions 12:00 p.m. - 1:00 p.m. Lunch (not hosted) 1:00 p.m. - 5:00 p.m. Test Sessions 5:00 p.m. Pack-up & shipping (Plugfest only) Thursday, November 18 8:00 a.m. - 12:00 p.m. Test Sessions (IW only) 12:00 p.m. - 1:00 p.m. Lunch (not hosted) 1:00 p.m. - 5:00 p.m. Test Sessions (IW only) 5:00 p.m. Pack-up & shipping (IW only) Interop Workshop : Testing M-Th 2 hr timeslots 5

6 IW / Logo Definitions Interop - Interoperability Program Logo Workgroup (WG) SATA-IO group that develops the Interoperability Program and Tests Organizes / staffs the IW test suites IW Interoperability Workshop IL Integrators List A list of end products that have passed testing at either a IW or Certified Test Lab 6

7 IW / Logo Definitions Continued UTD Unified Test Description Describes all the tests executed as part of the Interoperability Program, including references to SATA specification requirements as appropriate MOI Method of Implementation Vendor unique (by tool model(s) or tool revision) test procedures for each test Test Types Normative Tests which are required for IL listing Informative Tests that are in development Pass is NOT required to be placed on the IL Optional Not present on all products (Pwr Mgmt, NCQ, etc) If implemented on a product then a PASS is required for IL listing VTM Management company contracted by SATA-IO 7

8 IW Overview What is an Interoperability Workshop (IW)? A structured testing event where all testing conforms to approved or proposed test requirements in the UTD and by MOI procedures Results are collected and analyzed to verify results consistency Test suite staff & schedule are driven by SATA-IO All testing is done by Test ID (TID) 8

9 Plugfest Overview What is a Plugfest? Participant defined testing SATA-IO collects no results Test suites staffed by individual manufacturers, Testing as 1-on-1 vendor interactions under NDA How / Why are they different? Early product tested at Plugfest Final product tested at IW or Test Lab 9

10 Overview of Plugfest Testing Your company signed a Non-Disclosure Agreement You may be exposed to pre-release release product information of Participants. You agree to treat the test activities, the test results, and the pre-release release product information as confidential information ( Confidential Information ) and to refrain from disseminating or disclosing the same to others, except to your employees having a need to know Stationary vs Roaming Roaming teams: devices, cables, add-in hosts Stationary teams: host controllers/motherboards, systems, test tools Stationary schedules posted outside testing suites Be courteous cancel if not interested Make contact with the company 55 min test slots - Stop testing at 5 minutes of the hour 10

11 What s New with UTD Rev ? IW #9: Performing UTD Rev Testing Same Testing as IW #8 with a few relatively minor changes UTD changes OOB-03 and OOB-05 have increased timing margins OOB-03 : For the interests of the Interoperability Program, the measured value (T) will be compared against the minimum and maximum values of a multiple of UI OOB in nanoseconds, where T (+1% Larger than Spec Limit). OOB-5: For the interests of the Interoperability Program, the measured value (T) will be compared against the minimum and maximum values of a multiple of UI OOB in nanoseconds, where (-1% smaller than Spec Limit) T

12 What s New with UTD Rev ? (cont) Same Change to IPM-01 and IPM-09 Was: Host : Confirm Partial wake sequence completion and ALIGN timing of being within 10us of COMWAKE receipt from device/emulator/tool (use trace to analyze timings) Is Now: Host : Confirm Partial wake sequence completion and appearance of D10.2 characters being within 10us of COMWAKE receipt from device/emulator/tool (use trace to analyze timings) 12

13 IW Product handling rules 2 product samples + 1 backup Identical except s/n Exact same hardware Exact same firmware and features Exact same capacity Marked with TID labels DO NOT REMOVE Allows parallel test execution during the IW Once testing starts: NO hardware updates allowed NO firmware updates allowed NO configuration changes allowed (via software, f/w or jumpers) 13

14 General Reminders Registration information Badges / Schedules Feedback forms IW : Product Info Sheets Morning & afternoon snacks in Sponsor Suite Room 501 Free wireless internet Hospitality suite for questions/issues Room 502 Plugfest on 5 th floor, testing completed COB Wednesday IW on 4 th floor, testing completed Thursday 14

15 Before you leave the event Drop off necessary items to Hospitality Suite: Return monitors or borrowed equipment Please turn in your feedback forms for the event (Interop only) Drop off a single sample of your product 15

16 SATA-IO Interop and Technical Training Out Of Bound Signaling Physical Layer Measurements David Woolf 16

17 SATA-IO Logo Program OOB Tests Interop Workshop #8 November 11, 2010 David Woolf UNH-IOL 17

18 SATA Phy OOB Requirements Agenda What is OOB, why is it Important? SATA-IO Logo OOB Tests Signal Detection Threshold Tests UI During OOB Signaling Tests Transmit Burst Length Tests Transmit Gap Length Tests Gap Detection Window Tests 18

19 SATA Phy OOB Requirements What is OOB? Out-Of-Band Signals A A series of bursts and gaps used to communicate before SATA devices have performed speed negotiation Bursts made from D24.3 characters Gaps are made from electric idle 19

20 SATA Phy OOB Requirements What is OOB? 20

21 SATA Phy OOB Requirements What is OOB? Proper OOB detection critical for devices to properly initialize, or wake up from low power states. 3 3 OOB signals in SATA COMINIT (sent by Device only) COMRESET (sent by Host only) COMRESET Signal is the same as COMINIT Signal, but is referred to as COMRESET when transmitted by a Host. COMWAKE (Sent by Host or Device) 21

22 SATA Phy OOB Requirements OOB Signals Detection of COMINIT/RESET or COMWAKE determined by different Gap times COMINIT/RESET and COMWAKE have the same burst time OOB Signals Meaureed in OOBI (Out Of Band Interval) Equivalent to the Gen1 SATA UI UI = Unit Interval, time for 1 bit ps < t < ps 22

23 SATA Phy OOB Requirements COMINIT / COMRESET COMWAKE 23

24 SATA Phy OOB Requirements Agenda What is OOB, why is it Important? SATA-IO Logo OOB Tests Signal Detection Threshold Tests UI During OOB Signaling Tests Transmit Burst Length Tests Transmit Gap Length Tests Gap Detection Window Tests 24

25 SATA Phy OOB Requirements Signal Detection Threshold Tests OOB-01 Determines whether a product properly ignores OOB signals that are too small, and that a product properly detecst OOB signals that are properly sized. 25

26 SATA Phy OOB Requirements Signal Detection Threshold Tests: OOB-01 Gen 1 (1.5 Gbps) Product 26

27 SATA Phy OOB Requirements Signal Detection Threshold Tests: OOB-01 Gen 1 (1.5 Gbps) Product 27

28 SATA Phy OOB Requirements Signal Detection Threshold Tests: OOB-01 Gen 1 (1.5 Gbps) Product 28

29 SATA Phy OOB Requirements Signal Detection Threshold Tests: OOB-01 Gen 1 (1.5 Gbps) Product 29

30 SATA Phy OOB Requirements Signal Detection Threshold Tests: OOB-01 Gen 2 (3 Gbps) or 3 (6Gbps) Product 30

31 SATA Phy OOB Requirements Signal Detection Threshold Tests: OOB-01 Gen 2 (3 Gbps) or 3 (6Gbps) Product 31

32 SATA Phy OOB Requirements Signal Detection Threshold Tests: OOB-01 Gen 2 (3 Gbps) or 3 (6Gbps) Product 32

33 SATA Phy OOB Requirements Signal Detection Threshold Tests: OOB-01 Gen 2 (3 Gbps) or 3 (6Gbps) Product 33

34 SATA Phy OOB Requirements Agenda What is OOB, why is it Important? SATA-IO Logo OOB Tests Signal Detection Threshold Tests UI During OOB Signaling Tests Transmit Burst Length Tests Transmit Gap Length Tests Gap Detection Window Tests 34

35 SATA Phy OOB Requirements UI During OOB Signaling Tests OOB-02 Determines that a product transmits OOB bursts using the proper UI (unit interval / bit time) of : ps < t < ps 35

36 SATA Phy OOB Requirements UI During OOB Signaling Tests 36

37 SATA Phy OOB Requirements UI During OOB Signaling Tests 37

38 SATA Phy OOB Requirements Agenda What is OOB, why is it Important? SATA-IO Logo OOB Tests Signal Detection Threshold Tests UI During OOB Signaling Tests Transmit Burst Length Tests Transmit Gap Length Tests Gap Detection Window Tests 38

39 SATA Phy OOB Requirements Transmit Burst Length Tests OOB-03 Determines that a burst within any OOB signal is the proper length (160 OOBI): ns < t < ps 39

40 SATA Phy OOB Requirements Transmit Burst Length Tests 40

41 SATA Phy OOB Requirements Transmit Burst Length Tests 41

42 SATA Phy OOB Requirements Agenda What is OOB, why is it Important? SATA-IO Logo OOB Tests Signal Detection Threshold Tests UI During OOB Signaling Tests Transmit Burst Length Tests Transmit Gap Length Tests Gap Detection Window Tests 42

43 SATA Phy OOB Requirements Transmit Gap Length Tests OOB-04 Determines that a Gap within a COMINIT/RESET signal is the proper length (480 OOBI) : ns < t < ps OOB-05 Determines that a Gap within a COWAKE signal is the proper length (160 OOBI): ns < t < ps 43

44 SATA Phy OOB Requirements Transmit Gap Length Tests COMINIT/RESET 44

45 SATA Phy OOB Requirements Transmit Gap Length Tests COMINIT/RESET 45

46 SATA Phy OOB Requirements Transmit Gap Length Tests COMWAKE 46

47 SATA Phy OOB Requirements Transmit Gap Length Tests COMWAKE 47

48 SATA Phy OOB Requirements Agenda What is OOB, why is it Important? SATA-IO Logo OOB Tests Signal Detection Threshold Tests UI During OOB Signaling Tests Transmit Burst Length Tests Transmit Gap Length Tests Gap Detection Window Tests 48

49 SATA Phy OOB Requirements Gap Detection Window Tests COMWAKE OOB-06 Determines that a Product responds to COMWAKE signals with a Gap Length of 155 OOBI and 165 OOBI. Determines that a Product ignores COMWAKE signals with a Gap Length of 45 OOBI and 266 OOBI. 49

50 SATA Phy OOB Requirements Gap Detection Window Tests COMWAKE 50

51 SATA Phy OOB Requirements Gap Detection Window Tests COMWAKE 51

52 SATA Phy OOB Requirements Gap Detection Window Tests COMWAKE 52

53 SATA Phy OOB Requirements Gap Detection Window Tests COMWAKE 53

54 SATA Phy OOB Requirements Gap Detection Window Tests COMINIT/RESET OOB-07 Determines that a Product responds to COMINIT/RESET signals with a Gap Length of 459 OOBI and 501 OOBI. Determines that a Product ignores COMINIT/RESET signals with a Gap Length of 259 OOBI and 791 OOBI. 54

55 SATA Phy OOB Requirements Gap Detection Window Tests COMINIT/RESET 55

56 SATA Phy OOB Requirements Gap Detection Window Tests COMINIT/RESET 56

57 SATA Phy OOB Requirements Gap Detection Window Tests COMINIT/RESET 57

58 SATA Phy OOB Requirements Gap Detection Window Tests COMINIT/RESET 58

59 SATA Phy OOB Requirements Agenda What is OOB, why is it Important? SATA-IO Logo OOB Tests Questions? Signal Detection Threshold Tests UI During OOB Signaling Tests Transmit Burst Length Tests Transmit Gap Length Tests Gap Detection Window Tests 59

60 SATA-IO PHY Measurements John Calvin, Tektronix SATA-IO Logo Work Group Chair 60

61 PHY (Clock Stability, SSC Properties) 61

62 PHY (Clock Stability, SSC Properties) 62

63 PHY (Clock Stability, SSC Properties) 63

64 PHY (Clock Stability, SSC Properties) 6 11/14/

65 PHY (Clock Stability, SSC Properties) Tektronix Innovation Forum 65

66 PHY (Clock Stability, SSC Properties) 66

67 PHY (Clock Stability, SSC Properties) dfdt (delta Frequency/delta Time) or SSC Slew-rate Pilot measurements, coming to the next version 1.42 version of the SATA UTD, possibly normative in 2011 aqt IW#10. 67

68 SATA-IO Interop and Technical Training Transmitter AC Parametric and Jitter measurements Min-Jie Chong 68

69 SATA-IO Interoperability Workshop TSG: Transmitter AC Parametric and Jitter Measurements Min-Jie Chong Storage Product Manager Agilent Technologies 69

70 Summary of Transmitter Signal Quality PHY-01 : Unit Interval PHY-02 : Frequency Long Term Stability PHY-03 : SSC Modulation Frequency PHY-04 : SSC Modulation Deviation TSG-01 : Differential Output Voltage TSG-02 : Rise/Fall Time TSG-03 : Differential Skew TSG-04 : AC Common Mode Voltage TSG-05 : Rise/Fall Imbalance TSG-06 : Amplitude Imbalance TSG-09 : Gen1 (1.5Gb/s) TJ TSG-10 : Gen1 (1.5Gb/s) DJ TSG-11 : Gen2 (3Gb/s) TJ TSG-12 : Gen2 (3Gb/s) TSG-13 : Gen3 (6Gb/s) Transmit Jitter TSG-14 : Gen3 (6Gb/s) Max Diff Vamp TSG-15 : Gen3 (6Gb/s) Min Diff Vamp TSG-16 : Gen3 (6Gb/s) AC Com Mode Voltage OOB-01 : OOB Signal Detection Threshold OOB-02 : UI During OOB Signaling OOB-03 : COMINIT/RESET/WAKE Burst Length OOB-04 : COMINIT/RESET Transmit Gap Length OOB-05 : COMWAKE Transmit Gap Length OOB-06 : COMWAKE Gap Detection Windows OOB-07 : COMINIT/RESET Gap Detection Windows PHY TSG OOB 70

71 SATA TSG TEST PATTERN 71

72 Basic Test Pattern Requirement HFTP (High Frequency Test Pattern) D10.2 D10.2 MFTP (Mid Frequency Test Pattern) D24.3 D24.3 LFTP (Low Frequency Test Pattern) D30.3 D30.3 LBP (Lone Bit Pattern) 72

73 Test Pattern Requirement for PHY/TSG Tests Gen1 no SSC Gen 1 SSC Gen 2 no SSC Gen 2 SSC Gen 3 no SSC Gen 3 SSC PHY-01 : Unit Interval HFTP HFTP Both Rate HFTP Both Rate HFTP ALL Rate HFTP ALL Rate HFTP PHY-02 : Freq Stability PHY-03 : SSC Freq PHY-04 : SSC Deviation HFTP HFTP HFTP HFTP HFTP HFTP HFTP HFTP HFTP TSG-01 : Diff Output Voltage Min Voltage test is required. HFTP/ MFTP LBP/ LFTP HFTP/ MFTP LBP/ LFTP HFTP/ MFTP LBP/ LFTP Both Rate HFTP/ MFTP LBP/ LFTP Both Rate TSG-02 : Rise/Fall Time LFTP LFTP Both Rate LFTP Both Rate LFTP ALL Rate LFTP ALL Rate LFTP TSG-03 : Differential Skew TSG-04 : AC Common Voltage TSG-05 : Tr/Tf Imbalance TSG-06 : Amp Imbalance TSG-09 : Gen1 TJ TSG-10 : Gen1 DJ TSG-11 : Gen2 TJ TSG-12 : Gen2 DJ TSG-13 : Gen3 Jitter TSG-14: Gen3 Diff Voltage TSG-15: Gen3 Diff Voltage min TSG-16: Gen3 common Voltage HFTP/ MFTP HFTP/ LBP HFTP/ LBP HFTP/ MFTP HFTP/ LBP HFTP/ LBP HFTP/ MFTP MFTP ----(obsolete) ----(obsolete) HFTP/ LBP HFTP/ LBP HFTP/ LBP HFTP/ LBP HFTP/ MFTP MFTP ----(obsolete) ----(obsolete) HFTP/ LBP HFTP/ LBP HFTP/ LBP HFTP/ LBP HFTP/ MFTP HFTP/ LBP HFTP/ LBP HFTP/ LBP HFTP/ LBP H/M/L/ LBP MFTP LBP HFTP HFTP/ MFTP HFTP/ LBP HFTP/ LBP HFTP/ LBP HFTP/ LBP H/M/L/ LBP MFTP LBP HFTP 73

74 Device Test Mode for Pattern Generation BIST-L: Far End Retimed Loop Back (Spec Mandatory) Receive pattern from PPG and retransmit the same pattern with PUT s own clock BIST-L Required Test Pattern Pulse Pattern Generator Rx PUT Tx BIST-TSA: Vendor configure PUT s to transmit required test pattern (Spec Mandatory) BIST-TSA Required Test Pattern T: Transmit Only (Even without Rx signal) S: Scramble Bypass (No scramble) A: ALIGN Bypass (No ALIGN primitives inserted) PUT Tx * PUT: Product Under Test (SATA term) Page 74 SATA / SAS Test Challenges 74 Agilent Restricted

75 SATA GEN3 MEASUREMENT REQUIREMENT AND UPDATES 75

76 SATA Gen3 Specification Changes and Updates New reference clock definition clarification for jitter testing Jitter Transfer Function requirement for jitter measuring devices Rise/Fall Time measured with LFTP at all data rates 6Gb/s Jitter & amplitude measured after worst-case channel Model defined as Compliance Interconnect Channel (CIC) ECN #39 Gen3i Jitter Compliance Mask AC Common Mode Voltage frequency-domain measurement TSG-05 and TSG-06 Imbalance Tests are obsolete 76

77 What is Jitter Transfer Function? Jitter Frequency Response of the CDR of Jitter Measurement Devices (JMD) Method: Sweep SJ Freq with Fixed Jitter (Example 0.3 UI value with JBERT) Plot how much Jitter UIs observed on Scope Jitter analysis Jitter amplitude 0.3UI Input Jitter Low Freq Jitter No Jitter seen. Tracked by CDR High Freq Jitter CDR cannot Track 0dB db -3dB Measured Jitter on a Scope Jitter Frequency peaking JTF: Measured Jitter/Input Jitter 30kHz JTF Jitter Frequency 77

78 Why Jitter Value Vary by Different Setup? Because of different Jitter Transfer Function (JTF) To resolve this issue, defined a JTF regulation range. Unified JTF = Better Jitter Measurement correlation (SATA-IO ECN#008) Jitter amplitude JTF Qualified JTF Jitter in ABS value Jitter Frequency Measured Jitter Jitter Frequency Non Qualified JTF Measured Jitter Jitter Frequency 78

79 SATA 1.5Gb/s & 3Gb/s Reference Clock Definition TSG09-12 : New CDR method is used for Jitter Measurement. It is called JTF (Jitter Transfer Function) from ECN 008. The -3 db corner frequency of the JTF shall be 2.1 MHz +/- 1 MHz. The magnitude peaking of the JTF shall be 3.5 db maximum. The attenuation at 30 KHz +/- 1% shall be 72 db +/- 3 db. Agilent New CDR setting for 1.5Gb/s and 3.0Gb/s is 2 nd Order PLL: 2.1MHz Loop BW: Damping Factor = dB -3dB SATA Data SATA Data -69dB -72dB -75dB 1.1MHz 3.1MHz LPF VCO Recovered Clock used for TIE Jitter Measurements 30kHz 2.1MHz 79

80 SATA 6Gb/s Reference Clock Definition TSG13 : New CDR method is used for Jitter Measurement. It is called JTF (Jitter Transfer Function) from ECN 008. The -3 db corner frequency of the JTF shall be 4.2 MHz +/- 2 MHz. The magnitude peaking of the JTF shall be 3.5 db maximum. The attenuation at 420 KHz +/- 1% shall be 38.2 db +/- 3 db. Agilent New CDR setting for 6.0Gb/s is 2 nd Order PLL: 4.20 MHz Loop BW: Damping Factor = dB -3dB SATA Data SATA Data -35.2dB -38.2dB -41.2dB 2.2MHz 6.2MHz LPF VCO Recovered Clock used for TIE Jitter Measurements 420kHz 4.2MHz 80

81 Rise and Fall Time Measurement with LFTP LFTP Pattern Gen3 Specification: Waiver is available for 1.5Gb/s and 3Gb/s devices which have rise/fall time faster than the minimum limits. 81

82 Gen3i CIC Definition for Jitter and Amplitude This could represent the 1-meter internal cable length. Before CIC After CIC Page 82 SATA / SAS Test Challenges 82 Agilent Restricted

83 Embedding Gen3i CIC Channel + Tx - EQ Txp Txn Test Fixture TP0 Scope CIC TP1 Embed the Gen3i CIC channel and then make jitter and amplitude measurements to simulate the worst case channel interconnect. Page 83 Minimum Differential Voltage Jitter Measurement SATA / SAS Test Challenges 83 Agilent Restricted

84 6Gb/s Differential Voltage Measurement The Gen3i minimum voltage is measured using statistical eye opening at the recovered clock location using the LBP pattern. The amplitude distribution is statistically measured at 1E-1212 BER. The Gen3i maximum voltage is measured as the peak-peak amplitude of the MFTP pattern over 500 averages. Minimum Differential Voltage Maximum Differential Voltage 84

85 ECN #39 Gen3i Jitter Compliance Mask Dominated by Deterministic Jitter (DJ) Dominated by Random Jitter (RJ) The spec has been updated to constrain RJ and DJ with TJ(1E-12) and TJ(1E-6) 85

86 Gen3i AC Common Mode Voltage Measurement 86

87 Gen3i AC Common Mode Voltage Measurement An oscilloscope with 50-ohm inputs for TX+ and TXcan measure common mode voltage directly. RBW = Scope Sample Rate / Scope Memory Depth In order to make the AC common mode voltage measurement in the frequency domain, the positive and negative signal is first summed and divided by 2. Then, this signal is converted into frequency domain through FFT. Since the spec requires a resolution bandwidth (RBW) of 1MHz, the scope is set to 40GSa/s and 40k points of memory depth achieves this. 87

88 Gen3i AC Common Mode Voltage Measurement At 3GHz, dBm = 15.28dBmV At 6GHz, dBm = -0.06BmV The scope s FFT reading is in power (dbm) and can be converted to a voltage ratio (dbmv) by adding to the dbm reading for a 50-ohm system (100-ohm differential. Resolution Bandwidth (RBW) can be precisely controlled by adjusting the scope s memory depth. RBW = Scope Sample Rate / Scope Memory Depth 88

89 Imbalance Test Obsolescence Rise/Fall Time Imbalance and Amplitude Imbalance tests are removed from the Unified Test Document 1.4 because the LOGO committee has decided that the tests are not predictor for system interoperability. Driver imbalance testing is typically intended as an ASIC-level analysis criteria to try to identify possible issues of electromagnetic interference (EMI) radiation during the design phase of a product, not as a system interoperability criteria that rejects product at the industry level. The tests are originally designed to screen out device which causes EMI radiation but there are proof that device failing the tests would pass the FCC regulations. 89

90 SATA-IO Interop and Technical Training Receiver Test Measurements 90

91 SATA-IO RSG 91

92 PHY Receive Signal Requirements RSG Initiation of Far-end Retimed Loopback Test Points for RSG Setup Calibration Influence of Test Adapters Test Parameters (RSG01, RSG02 and RSG03) Data Rate Offset (RSG05) Spread Spectrum Clock (RSG06) 92

93 Initiation of Far-end Retimed Loopback UTD1.4 Section 2.17 Clearly States: Products must support BIST L at all supported data rates. 93

94 Allow Product to Complete OOB 94

95 BIST Field Definitions 95

96 Decoding, Descrambling and Aligns 7.6 Elasticity Buffer Management 96

97 Loop Back the Data Lots of text on the previous slide. In short: Remove the incoming Align primitives You can descramble and decode, but then you must scramble and 8b/10b code before returning the data. Insert Align primitives every 254 DWords and follow disparity rules the way you normally do. Return the data. It is OK that the disparity may be the opposite of the incoming stream. 97

98 Test points for RSG setup calibration The reference plane for all RSG calibrations is at the end of the 50 Ohms SMA or equivalent cables at TP1 or TP2. 98

99 Test points for RSG setup calibration The reference plane for RSG calibrations is the same as the Lab Source Signal Compliance Point in the SATA specification. 99

100 Influence of Test Adapters The UTD reference plane for RSG calibrations does not include the SATA Adapter. You are therefore best off using the: Most Repeatable/Reliable Lowest Insertion Loss Least Crosstalk Best Impedance Matched Highest Quality SATA adapter you can get. 10 0

101 PHY Receive Signal Requirements Test Parameters (RSG01, RSG02 and RSG03) Rise/ Fall time Random Jitter (Rj) Sinusoidal Jitter (Sj) Compliance Interconnect Channel (CIC) Total Jitter (Tj) Amplitude Pattern and Test Time Data Rate Offset (RSG05) Spread Spectrum Clock (RSG06) 10 1

102 General Serial ATA does not yet use or specify pre-emphasis emphasis for the compliance tests: Clean clock rather than Jitter Transfer Functions (JTF) or Clock Data Recovery (CDR) is used for the calibration since the test signals come from a well known Lab Source and therefore can be programmed and measured to accommodate JTF if desired. 10 2

103 Rise/ Fall Time The first parameter to calibrate is the Ris/Fall Time, which is the only parameter measured with the Low Frequency Transition Pattern (LFTP): 10 3

104 Random Jitter (Rj) Random Jitter is measured using the Medium Frequency Transition Pattern (MFTP) at TP1: 10 4

105 Sinusoidal Jitter (Sj) Sinusoidal Jitter (Sj) is typically measured as the delta between two Total Jitter measurements with MFTP: 10 5

106 Compliance Interconnect Channel (CIC) The Gen3i Compliance Interconnect Channel or TCTF is defined in of SATA 3.0 as follows: 10 6

107 Compliance Interconnect Channel (CIC) The Gen3i CIC can be measured as the absolute magnitude of S21 using time-domain step response or vector network analysis. The Data Dependent Inter Symbol Interference (ISI) Jitter can be measured using averaged waveforms or the delta between Tj from MFTP and LBP measurements. Example of SATA Compliance Interconnect Channel db Return Loss Insertion Loss MHz 10 7

108 Total Jitter (Tj) Total Jitter at TP2 is verified using the Framed COMP including the Lone Bit Pattern (LBP). The LBP section generally generates the entire Tj including the Data Dependent Jitter (DDJ) from the channel: 10 8

109 Amplitude Eye Height is measured or projected at 1E-1212 BER using the LBP section of the Framed COMP. 10 9

110 Amplitude Maximum Amplitude is measured as peak-to-peak on an averaged waveform. The maximum amplitude limit is set to assure that the Lab Source test signals do not exceed the maximum voltage of a SATA signal at the receiver. 11 0

111 Test Time and Pattern The 6 Gb/s test pattern and time are defined in the UTD as follows (Framed COMP Pattern with two Aligns for 2 minutes and 30 seconds): The test patterns for 1.5 Gb/s, 3 Gb/s and 6 Gb/s are the same as above, but the time for 1.5 Gb/s and 3 Gb/s are respectively 10 minutes and 5 minutes per Sj frequency because it takes longer to receive the same number of bits at the lower data rate. 11 1

112 Data Rate Offset (RSG05) RSG06 tests the asynchronous behavior of the receiver during data rate offsets. This is done by: Setting the Lab Source data rate +350 ppm above the nominal Gen1i/m data rate, i.e. at 1, Mb/s. Injecting the receiver stress signal as calibrated for RSG01 with Sj set to 62 MHz. Measuring that there are no frame errors during at least 18 repetitions of the Framed COMP. This is obviously met is there are no bit errors. Note: If conducted over more than 18 repetitions then the test pass if the Frame Error Ratio is less than 8.2E

113 Spread Spectrum Clock (RSG06) The receiver stress test with Spread Spectrum Clock (SSC) is currently informative. Set the data rate -350 ppm relative to the nominal Gen1i/m rate, i.e. at 1, Mb/s, with ideal 5000 ppm down spread triangular SSC at 33 khz modulation frequency. Inject the receiver stress signal as calibrated for RSG01 with Sj set to 62 MHz. Measure that there are no frame errors during at least 18 repetitions of the Framed COMP. This is obviously met is there are no bit errors. Note: If conducted over more than 18 repetitions then the test pass if the Frame Error Ratio is less than 8.2E

114 Asynchronous Receiver Test Example Lab Source data rate with ideal down spread triangular SSC Retimed Data Rate from Product Under Test Bit Error Ratio 11 4

115 RSG04 is Reserved for Gen4 I skipped RSG04 as it is reserved for Gen4. Which may likely include: Pre-emphasis F/2 Jitter also called Long-Bit-Short-Bit Jitter And many other fun things Perhaps even Real World SSC Profiles (Host SSC rarely goes from 0 ppm to ppm in real implementations but takes upon smaller ppm at positive ppm offset for storage or swings that never reaches 0 ppm for mobile platforms. Good Luck. 11 5

116 SATA-IO Cable Measurements 11 6

117 SATA SI Tests (Informative for esata) SI-01 - Mated Connector Impedance SI-02 - Cable Absolute Differential Impedance SI-03 - Cable Pair Matching SI-04 - Common Mode Impedance SI-05 - Differential Rise Time SI-06 - Intra-Pair Skew SI-07 - Insertion Loss SI-08 - Differential to Differential Crosstalk: NEXT SI-09 Inter Symbol Interference /14/2010 Confidential 11 7

118 SATA SI Manual Test Setups SI01-SI07, SI09 tests SI08 tests Instrumentation: DSA8200 with 80E04 sampling modules 80SICON - S-parameters, impedance profile, and eye diagram. SATA test adaptors and SMA cables /14/2010 Confidential 11 8

119 SI-01 - Mated Connector Impedance Pair Differential Impedance should be between 85 and 115 Ohms /14/2010 Confidential 11 9

120 SI-02 - Cable Absolute Differential Impedance Absolute Differential Impedance should be between 90 and 110 Ohms /14/2010 Confidential 12 0

121 SI-03 - Cable Pair Matching Pair Matching (Z max, Z min ) should be within 5 Ohms. (Z max = Z J4max Z J5max and Z min = ZJ 4min Z J4min ) /14/2010 Confidential 12 1

122 SI-04 - Common Mode Impedance Common Mode Impedance should be within Ohm limits /14/2010 Confidential 12 2

123 SI-05 - Differential Rise Time Differential Rise time should be faster than 85ps (20-80%) /14/2010 Confidential 12 3

124 SI-06 - Intra-Pair Skew Intra-pair skew should be less than 10ps /14/2010 Confidential 12 4

125 SI-07 - Insertion Loss Max insertion loss should be less then -6dB /14/2010 Confidential 12 5

126 SI-08 - Differential to Differential Crosstalk: NEXT NEXT should be better than -26dB /14/2010 Confidential 12 6

127 SI-09 Inter Symbol Interference ISI should be less than 50ps /14/2010 Confidential 12 7

128 TekExpress SATA SI Automated Test Setup /14/

129 SATA Cable testing Summary Purpose is to ensure that the cable does not cause a interoperability issue Test is comprised of three areas, Impedance, Timing, Frequency content Two methods manual or automated MOI available on SATA IO site or 12 9

130 Lunch Please join us for lunch in the Yong He Ballroom 13 0

131 SATA-IO Interop and Technical Training Mechanical Dimension Validation Denis Chang 13 1

132 Mechanical Dimension Validation Agenda Equipment Cable Assembly Device Usual error 13 2

133 Mechanical Dimension Validation (a) device signal plug segment or connector (b) device power plug segment or connector (c) signal cable receptacle connector (d) power cable receptacle connector (e) signal cable receptacle connector (f) the host signal plug connector 13 3

134 Equipment Dimension-Using the optic system 13 4

135 Equipment Insertion/ removal force- Using the Nominal Plug Gage 13 5

136 Cable Assembly Cable Assembly MCI-01 : Visual and Dimensional Inspections MCI-02 : Insertion Force (Latching and Non-Latching) MCI-03 : Removal Force (Non-Latching) MCI-04 : Removal Force (Latching) MCX-05 : Cable Pull-out 13 6

137 Cable Assembly MCI-01 : Visual and Dimensional Inspections D. E. C. The A. B. width height The of height width of the the cable slot of of slot the for for retention slot the the shall device feature be be plug plug 1.40 (bump) key key + shall / shall be be mm 1.31 be / -+ / / mm mm mm D C A BE 13 7

138 Cable Assembly MCI-01 : Visual and Dimensional Inspections F. For a latching cable the distance from the slot to the top surface of the receptacle shall be mm F 13 8

139 Cable Assembly MCI-02 : Insertion Force (Latching and Non-Latching) MCI-03 : Removal Force (Non-Latching) For Serial ATA Interoperability Program testing a total of 20 insertion/removal force cycles shall be used for this measurement. Insertion Force : 45 N Max. Removal Force : 10 N Min. through 20 cycles 13 9

140 Cable Assembly MCI-04 : Removal Force (Latching ) No damage and no disconnect with 25N static load applied after 20 mating cycles MCX-05 : Cable Pull-out No physical damage visible with 40N static load applied for at least 1 minute The change in resistance shall not be greater than 1.0 Ohm 14 0

141 Cable Assembly Test Measurement Latching Non-Latching Height of slot Width of slot Height of key slot Width of key slot MCI-01 : Visual and Dimensional Inspections Cable retention bump width Slot to top surface MCI-02 : Insertion Force Cycle rate:12.5 mm/minute MCI-03 : Removal Force (Non-Latching) Cycle rate:12.5 mm/minute MCI-04 : Removal Force (Latching) 25N static load applied after 20 mating cycles. MCI-05 : Cable Pull-Out 40N static load applied for 1 minute. The change of resistance ( R) 14 1

142 Device Dimension Device type 12.7mm Slimline optical device 9.5 mm Slimline optical device 7mm Slimline optical device 5.25 optical device 5.25 non-optical device 3.5 side mounted device 3.5 bottom mounted 2.5 side mounted device 2.5 bottom mounted device 1.8 HDD 14 2

143 Device Dimension Device MDI-01 : Connector Location MDI-02 : Visual and Dimensional Inspections MDP-01: Visual and Dimensional Inspections 14 3

144 Device Dimension MDI-01 : Connector Location (3.5 bottom mounted ) A. B. From Parallelism the bottom of the surface top of the of the tongue drive of to the the SATA top of plug the vs. tongue the bottom of the SATA surface plug of shall the drive be 3.50 shall +-be mm mm. B A 14 4

145 Device Dimension MDI-01 : Connector Location (3.5 bottom mounted ) D. C. From the centerline of the bottom drive to mounting the centerline holes of to the the SATA base of the plug tongue shall of be the SATA + plug / shall mm be / mm C D 14 5

146 Device Dimension MDI-02 : Visual and Dimensional Inspections (3.5 bottom mounted ) A. The thickness of the device plug tongue shall be / mm B. The distance from the device plug tongue to the Optional Wall shall be / mm A B 14 6

147 Device dimension MDI-02 : Visual and Dimensional Inspections (3.5 bottom mounted ) C. The combined width of the power and signal segments shall be / mm D. The separation between the power and signal segments shall be / mm D C 14 7

148 Device dimension MDP-01 : Visual and Dimensional Inspections (3.5 bottom mounted ) A. The thickness of the device plug tongue shall be / mm B. The distance from the device plug tongue to the Optional Wall shall be / mm A B Device - Power Connector 14 8

149 Usual Error Connector dimensions are in specification, but device dimensions aren t pass. Connector mounted location is error C Centerline of device D Centerline of connector MDI-01 : Connector Location (3.5 bottom mounted ) 14 9

150 Mechanical Dimension Validation Thanks for your attention! 15 0

151 SATA-IO System Interoperability Test Training Johnson Tan Granite River Labs 15 1

152 Outline Background Test setup Test description Test operation 15 2

153 Background Objectives To test the interoperability between a SATA Device and the SATA Host system Can be used for testing either Device or Host DUT s History Developed by Jeff Wolford from HP and released in 11/06 MOI document can be found in

154 Test Setup For Gen 1 and 2 Devices One Gen 1 or 2 or 3 Host with SSC turned on One Gen 1 or 2 or 3 Host One Gen 1 or 2 or 3 Host One Gen 1 or 2 or 3 Host One Gen 1 or 2 or 3 Host Hosts must be from 3 different SATA PHY IP sources 15 4

155 Test Setup For Gen 3 Devices One Gen 3 Host with SSC turned on One Gen 3 Host One Gen 1 or 2 or 3 Host One Gen 1 or 2 Host One Gen 1 or 2 Host Hosts must be from 3 different SATA PHY IP sources 15 5

156 Test Setup DOS Tool in Bootable Media on SATA Host USB bootable flash drive (recommended) or DOS tool can be downloaded from SATO IO website Need to make USB drive bootable and load required MS- DOS tools Bootable floppy disk, CD, or HDD alternatives to USB drive but not recommended due to slow speed or setup difficulty Optical test disk for ODD testing DUT is the only Device connected to SATA Host and BIOS must be set to boot media with DOS tool 15 6

157 Test Description Source binary files that are created from the SATA-IO composite pattern reverse scrambled and encoded to match 2K Dword (8KB) out of SATA bus Size of the source binary files was varied to strike a balance between guaranteed being 8K aligned and increased data throughput through larger file sizes Smaller file sizes have a high likelihood of being cached, thus achieving higher burst transfer rates Larger files increase Host media access interactions File sizes: 8KB, 64KB, 256KB, 1MB, and 16MB 15 7

158 Test Description For the HDD test, each of the source binary files is copied to the HDD, and then copied 39 more times generationally, so that only the last file needs to be validated to verify all 40 copies were correct File validation using MD5 128-bit checksum with stored md5 signature For the ODD test, only read tests are performed, and each of the source binary files is read and validated using the md5 signature tool multiple times Test runs for 9-10 minutes and if an error is detected, the test will pause 15 8

159 Test Operation For HDD testing, boot Host system using USB boot drive and run DOS SATA test script For ODD testing, boot Host system with USB boot drive and run DOS SATA test script with optical test disk in ODD Test passes if DUT is recognized by Host system and DOS SATA test script completes successfully For the entire interop test to pass, the DUT must pass 4 out of the 5 host systems 15 9

160 Host Testing Similar to Drive testing but 5 drives must be chosen from the SATA IO Integrators List For Gen 1 and 2 Hosts One Gen 1 or 2 or 3 Device with SSC turned on One Gen 1 or 2 or 3 Device One Gen 1 or 2 or 3 Device One Gen 1 ODD with SSC turned on One Gen 1 ODD Hosts must be from 3 different SATA PHY IP sources 16 0

161 Host Testing For Gen 3 Hosts One Gen 3 Device with SSC turned on One Gen 3 Device One Gen 2 Device One Gen 1 ODD with SSC turned on One Gen 1 ODD Hosts must be from 3 different SATA PHY IP sources If Host does not support Device type, this needs to be indicated on Product info sheet 16 1

162 SATA-IO Interop and Technical Training Plugfest & Interop Workshop dynamics; how to get the most out of the testing events John Calvin 16 2

163 SATA-IO Plugfest vs- Interop 16 3

164 Plugfest vs- Interop The Interoperability event (IW) allows mature products to undergo a highly structured and rigorous set of tests to verify its ability to interoperate and its eligibility for the "SATA-IO Certified" Logo. These tests are performed by multiple test stations allowing customers to walk away with the comprehensive test reports from multiple instrument vendors and if they pass, they are eligible for Integrators list ranking. It's also the single best opportunity to sit with the test providers and ask questions or receive special training on topics where these specialists can offer product and test insights not available elsewhere. 16 4

165 Plugfest vs- Interop The Plugfest event (PF) offers the largest range of systems to perform interoperability testing against and makes up for the less detailed analysis compared to the IW venue, by offering shorter but greater number of test slots to allow the greatest breadth of plug and play opportunities with all host and device vendors present. T&M tool providers are available to provide ad-hoc testing services to plugfest attendees as well. This offers the best forum for less mature designs or with products with known problems where attendees can consult with experts in the field to gain insights to solutions. 16 5

166 Plugfest vs- Interop Experimental products >> Plugfest Systems which a piloting new silicon, or FPGA based IP Reference designs Products which don t support BIST-L (not SATA spec) General debug and discovery. First Look compatibility Testing Soon to be released products >> Interop Building Block components New Systems, Devices, Hosts Seeking official certification. 16 6

167 Join us for food and drinks, as well as technology demos from our sponsors Thank you for coming! 16 7