Low Cost Fault Detector Guided by Permanent Faults at the End of FPGAs Life Cycle Victor Manuel Gonçalves Martins

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1 Universidade Federal de Santa Catarina Dept. de Automação e Sistemas, CTC Low Cost Fault Detector Guided by Permanent Faults at the End of FPGAs Life Cycle (Victor Martins, Frederico Ferlini, Djones Lettnin and Eduardo Bezerra) Victor Manuel Gonçalves Martins <Victor.Martins@eel.ufsc.br>

2 Agenda -Introduction -Main objectives - BIST in a nutshell -Proposed BIST for FPGAs -Experimental results -Conclusions & future work 2

3 Introduction Faults and Errors in FPGAs Single Event Effects (SEEs) in the FPGAs world is an actual concern. These events (or errors) can be divided in two broad categories: soft errors (no physical damage) -can be recovered; hard errors (physical damage) - originated from permanent faults, not recoverable. Hard errors are less usual than soft errors, and may result in permanent FPGAsystem failure. 3

4 Introduction Some System Features Usually,asystem module is independent from others, giving the opportunity to test parts of the system in separate. All modules should be tested, but may have different requirements: more or less critical, meaning different time intervals between tests and different scheduling; different behaviour, implying different testing approaches for each module (e.g. different seeds for the test vectors generator). 4

5 Main Objectives -To propose an FPGA self-test strategy with negligible hardware increment; -Periodic test to look for faults (specially the permanent ones) until the end of the FPGA s life cycle; -Module oriented test -no need to shut the whole system down in order to perform the test; -Afunctional test (only test the resources that are used by the modules); -Toprovide the flexibility to manage all test processes (how many times, when, priority,etc ) 5

6 BIST in a nutshell Built-In Self-Test: Architecture o TPG:Test Pattern Generator (Linear Feedback Shift Register -LFSR); o CUT:Circuit UnderTesting (with ascan chain); o CRC: Cyclic Redundancy Check (ortest Data Sink); o BIST Control: Small state machine that control all testing activities. 6

7 BIST in a nutshell Built-In Self-Test: CUT o Scan Chain: Amultiplexer is added to all flip-flop inputs. When scan chain is enabled, all flip-flops are connected in series; o Normal Service: When scan chain is disabled the circuit works as there was no BIST. 7

8 Proposed BIST for FPGA Adapting BIST for FPGAs» BIST with Virtual Scan Chain: o TPG /CRC: Piece of software running on an embedded microprocessor; o CUT:Register elements are accessed by Internal Configuration Access Port (ICAP), providing access to the FPGAconfiguration memory; o BIST Control:All algorithms are also written in software. 8

9 Proposed BIST for FPGA FPGA configuration facilities Partial Reconfiguration (throughout ICAP): o Xilinx synthesis tools for partial reconfiguration add partition pins (primitive LUT1) at each input and output of a reconfigurable partition; o GCAPTURE -assigns flip-flops values to the FPGA configuration memory (used to read flip-flops state); o GRESTORE -implements aglobal Set Reset (GSR) that initializes flip-flops with correspondent FPGA configuration memory data (used to write flip-flops state); o Mask GSR capability to apply the GRESTORE command to only asection of FPGAresources(flip-flops). 9

10 Proposed BIST for FPGA Software features 10

11 Proposed BIST for FPGA Hardware features 11

12 Experimental Results Testing environment FPGA: Virtex-5 XC5VLX50T Tools: EDK 14.4 MicroBlaze based system, with some modules connected by OPB Bus. Four modules are selected to apply the new approach: -GPIO interface with 8bits; -Serial Port RS232 module; -SRAM controller; -Timer module. 12

13 Experimental Results Pre-processed modules parameters These parameters will directly affect memory and processing features. 13

14 Experimental Results Module 3 has more flip-flops and nputs, needing more memory and more processing. Alone, in the worst case (Module 3), MCODE is about 2/3 of total. The necessary memory for all four modules (including all permanent data memory row) is 18,346 bytes (50% -50%). Extra Hardware: 103 flip-flops; 54 LUTs; 4primitives BUFGCTRL 14

15 Conclusions & Future Work q It is possible to test modules implemented in FPGAs almost with no need for additional hardware. q The test is slower than traditional BISTs, but it provides the designer with the flexibility to decide the best testing strategy. q As a result of the slower performance, when comparing to traditional BIST,the best TPG sequence must be defined previously, in order to try to decrease the number of necessary test vectors. 15

16 Conclusions & Future Work q The WHICAP driver should be replaced by amore efficient one, as the code memory is asubstantial part of the available storage. q The number of module inputs has an important influence in memory usage and runtime. For the proposed approach it is recommended to select a bus or a NoC with less I/O lines requirements. q Develop atool (or mechanism) to make the modules simulation offline, to help found the best TPG algorithms to analysis and obtain areasonable fault coverage. 16

17 The End Obrigado (Gracias) América Latina 17