A new Interlock Design for the TESLA RF System

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1 A new Interlock Design for the TESLA RF System H. Leich 1, A. Kretzschmann 1, S. Choroba 2, T. Grevsmühl 2, N. Heidbrook 2, J. Kahl 2, 1 (DESY Zeuthen) 2 (DESY Hamburg) The Problem The Interlock Architecture Implementation Status of the Project 1/29/2007 Holger Leich, DESY Zeuthen 1 Main Task of the Interlock Sytem --> to prevent any damage from the cost expensive components of the RF station --> also to prevent any damage from other environment Sources of Interlock Error Signals hard component failures (non-reversible hardware malfunction) --> broken cable or damaged contact, dead sensor,... soft errors (e.g. sparks in the klystron or wave guide system, temperature above a threshold,...) error conditions caused by transient noise from the RF station itself 1/29/2007 Holger Leich, DESY Zeuthen 2 1

2 Klystron interlock Low level RF PITZ Clear, Clock, Dout RF- leak 1&2 enable Klystron 1&2 Clock... Din all input signals internal states output signals 12 gun signals separate enable RF Control system all input signals internal states output signals masks to BIS enable shutter1 1&2 Interlock Subsystems safety & person IL o.k. laser pulse length laser rep. Rate enable RF enable alig.laser Person interlock enable BIS 1&2 enable magnets 1 & 2 Magnets Laser interlock PM Gun fast Gun IL o.k. reset gun interlock laser shutter Beam inhibit system solenoid supply o.k. ADCs 9 analog signals Gun interlock Profibus 1/29/2007 Holger Leich, DESY Zeuthen 3 Architecture of the existing Interlock Strictly digital hierarchical Interlock Process Analysis Output to Process Analog Process Input Digital Process Input Analog Output Digital Output Sensor Sensor Adapter Unit Adapter Unit Klystron, RF Station 1/29/2007 Holger Leich, DESY Zeuthen 4 2

3 Klystron Interlock Inputs Digital Inputs - Oil levels - Cooling water flow - Vacuum pump current Analog Inputs - Oil temperature - Cooling water temperature - Heater current - Solenoid current - SF6 gas pressure 1/29/2007 Holger Leich, DESY Zeuthen 5 Klystron Interlock Inputs / Outputs Preprocessed Inputs - Person interlock o.k - RF leakage detector - Modulator ready - Gun interlock o.k. - RF system ready Interlock Outputs - Modulator on - Heater power supply on - Solenoid power supply on - RF enable 1/29/2007 Holger Leich, DESY Zeuthen 6 3

4 Response Times Ultra Fast (UF): R t < 1 µs Fast (F): R t = µs Slow (SL): R t > 5 µs --> Actual implementation only SL and F --> ca. 40 signals to process 1/29/2007 Holger Leich, DESY Zeuthen 7 Overview over the new Interlock Design Master Control System Component Characteristics Predefined Curve Data Measured Characteristic Interlock Logic implemented based on a Microcontroller (Processor Core) User programmable ASIC (FPGA) Time discrete digital data Analog Process Input Digital Process Input Analog/Digital Process Output Sensor Sensor Adapter Unit Klystron, RF Station 1/29/2007 Holger Leich, DESY Zeuthen 8 4

5 Implementation Constraints The Implementation limited space in TESLA-tunnel Other, DESY defined constraints combine Control & Interlock Functions into only one crate per RF-station perform communication between modules via backplane ( no extra cable for communication) process-i/o with no cables to the front side of the crate; all cables from rear site use a standard with stable, fast enough & easy to implement bus interface use a standard that gives flexibility at the level of system integration ( definition of backplane-ressources : standard bus, user defined bus, ) use a standard that saves investment over longer time scale use a standard to have the option to buy commercial available products (CPU`s, DAQ components, piggy pack, e.g. IP modules,...) use a standard that offers the option of additional boardspace (rear transition option) 1/29/2007 Holger Leich, DESY Zeuthen 9 Implementation Details DESY decision: Use a VME64x system - VME64x introduces 5 row (160 pins) connectors J1/J2 and an optional 95pin-connector J0 415 pins Total = 210 pins VME System pins User Defined => enough pin resources per slot and per backplane to build a compact interlock/control system VME is a stable, fast enough and easy to implement bus and instrumentation system mixed use of VME and VME64x devices possible rear transition board option easy system integration DESY: 205 pins User Defined: 64 pins per slot used for rear transition 141 pins across the backplane to implement a fast user bus 1/29/2007 Holger Leich, DESY Zeuthen 10 5

6 DESY-VME64x-Backplane ( slot-pin configuration ) 1 z a b c d J1 J e d c b a 19 1 z a b c d J2 per Slot per Slot pin User Defined Bus (GTL) Rear I/O Connections: 64 pins VME64x Standard 1/29/2007 Holger Leich, DESY Zeuthen 11 Interlock / Control Crate VME-CPU (VME-Controller) HD Profibus Reserve Interlock Master / Sequencer Up to 16 I/O-Modules Control- / Monitoring Interlock 1/29/2007 Holger Leich, DESY Zeuthen 12 6

7 Interlock / Control Crate (Side view) Front Boards (160 mm) VMEbus Interface Interlock / Master Logic I/O resources User Bus Interface J1 J0 Rear Boards (160 mm) Rear Transition Signals Additional I/O-functions Signal conditioning J2 VME64x Backplane, 160pin-J1/J2, 95pin-J0 (with J0 full & J2-pins rows z,d bussed) 1/29/2007 Holger Leich, DESY Zeuthen 13 Structure of the DESY User Defined Bus Sytem Master / Sequencer 110 lines connected: 22 Time-Mux-Bus 34 Control-Bus 16 Event-Bus 2 BusInit, BusClock 4 Reserve BusControl 32 Reserve (bi-directional) (all lines GTL) BusInit, BusClock Time-Multiplex-Bus Control-Bus Event-Bus Reserve I/O-Module & other Modules 31 lines spare at backplane for free use by other (future) components / systems Event-Bus and/or Reserve could be defined as LAM (Emergency Line) for Interlock Signals with very high priority 1/29/2007 Holger Leich, DESY Zeuthen 14 7

8 Time Mux Bus Bus Timing BCLK Init_l ADDR Data D(0) 0 D(0) 1 D(1) 2 D(2) 3 D(3) Control Bus BCLK STRB_l WE_l Address Data ADDRi Data Out ADDRj Data In BCLK SRVRQ_l Event Bus 1/29/2007 Holger Leich, DESY Zeuthen 15 Architecture of the Interlock Master / Sequencer Interlock I/O Boards ACEX EP1K100 FC484 Ctrl Out Ctrl In Interlock Logic (Sequencer/ Controller) Data Out Data In Ack Req Ack Req VME Access Control VME Interrupt Control Req Data Mux Ack ROM Access Arbiter & Address Mux ROM 512 x 16 DPM Access Control Address Mux Req Ack CS CE WE Data Bus Address Bus AM[5..0], AS, DS[1..0], Write, `ABT2244 LWord, Iack, IackIn Dtack, Berr, IRQ[7..4], IackOut `F38 `ABT Data Bus DB[15..0] Address Bus A[23..1] `ABT2244 VME Bus Nonvolatile SRAM 64K x 16 (4 x U634H256CSK25) 1/29/2007 Holger Leich, DESY Zeuthen 16 8

9 Other Modules under Construction Digital Input Module Digital Output normal Digital Output ultrafast Analog IO fast Digital IO LWL (Rear Module) 1/29/2007 Holger Leich, DESY Zeuthen 17 Status of the Project Architecture definition finished Backplane design & manufacturing finished Master/Sequencer design finished/assembled/tested I/O Module design DigiIn: assembled, not yet tested DigiOut, DigiOutFast: layout process Analog I/O: design not yet finished Digital IO LWL: not yet designed Firmware design ongoing 1/29/2007 Holger Leich, DESY Zeuthen 18 9

10 Existing RF Interlock System 1/29/2007 Holger Leich, DESY Zeuthen 19 VME64x-Crate with DESY VME64x Backplane 1/29/2007 Holger Leich, DESY Zeuthen 20 10

11 Interlock Master / Sequencer Module 1/29/2007 Holger Leich, DESY Zeuthen 21 11

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