Sequential Logic. Sequential Circuits. ! Timing Methodologies " Cascading flipflops for proper operation " Clock skew

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1 equential Logic! equential Circuits " imple circuits with feedback " Latches " Edgetriggered flipflops! Timing Methodologies " Cascading flipflops for proper operation " Clock skew! Basic egisters " hift registers " Counters C 5  pring 27 Lec. #5 equential Logic  equential Circuits! Circuits with Feedback " Outputs = f(inputs, past inputs, past outputs) " Basis for building "memory" into logic circuits " oor combination lock is an example of a sequential circuit # tate is memory # tate is an "output" and an "input" to combinational logic # Combination storage elements are also memory value C C2 C3 multiplexer comparator mux control new equal reset comb. logic state clock equal open/closed C 5  pring 27 Lec. #5 equential Logic  2
2 Circuits with Feedback! How to control feedback? " What stops values from cycling around endlessly X X2 Xn switching network Z Z2 Zn C 5  pring 27 Lec. #5 equential Logic  3 implest Circuits with Feedback! Two inverters form a static memory cell " Will hold value as long as it has power applied "" "" "stored value"! How to get a new value into the memory cell? " electively break feedback path " Load new value into cell "remember" "data" "load" "stored value" C 5  pring 27 Lec. #5 equential Logic  4
3 Memory with Crosscoupled Gates! Crosscoupled NO gates " imilar to inverter pair, with capability to force output to (reset=) or (set=)! Crosscoupled NAN gates " imilar to inverter pair, with capability to force output to (reset=) or (set=) ' ' ' ' ' ' C 5  pring 27 Lec. #5 equential Logic  5 Timing Behavior ' eset Hold et eset et ace \ C 5  pring 27 Lec. #5 equential Logic  6
4 tate Behavior of  latch! Truth table of  latch behavior hold unstable ' ' ' ' C 5  pring 27 Lec. #5 equential Logic  7 Theoretical  Latch Behavior = =! tate iagram " tates: possible values " Transitions: changes based on inputs possible oscillation between states and ' = = = = = = = ' ' = = = = ' = = = C 5  pring 27 Lec. #5 equential Logic  8
5 Observed  Latch Behavior! Very difficult to observe  latch in the  state " One of or usually changes first! Ambiguously returns to state  or  " A socalled "race condition" " Or nondeterministic transition = = ' = = = = ' = = = = = ' = = C 5  pring 27 Lec. #5 equential Logic Latch Analysis! Break feedback path (t) ' (t+!) (t) (t+!) X X hold reset set not allowed (t) X X characteristic equation (t+!) = + (t) C 5  pring 27 Lec. #5 equential Logic 
6 Gated  Latch! Control when and inputs matter " Otherwise, the slightest glitch on or while enable is low could cause change in value stored ' enable' ' ' et eset ' ' enable' ' C 5  pring 27 Lec. #5 equential Logic  Clocks! Used to keep time " Wait long enough for inputs (' and ') to settle " Then allow to have effect on value stored! Clocks are regular periodic signals " Period (time between ticks) " utycycle (time clock is high between ticks  expressed as % of period) duty cycle (in this case, 5%) period C 5  pring 27 Lec. #5 equential Logic  2
7 Clocks (cont d)! Controlling an  latch with a clock " Can't let and change while clock is active (allowing and to pass) " Only have half of clock period for signal changes to propagate " ignals must be stable for the other half of clock period ' clock' ' ' stable changing stable changing stable ' and ' clock C 5  pring 27 Lec. #5 equential Logic  3 Cascading Latches! Connect output of one latch to input of another! How to stop changes from racing through chain? " Need to control flow of data from one latch to the next " Advance from one latch per clock period " Worry about logic between latches (arrows) that is too fast ' ' clock C 5  pring 27 Lec. #5 equential Logic  4
8 Masterlave tructure! Break flow by alternating clocks (like an airlock) " Use positive clock to latch inputs into one  latch " Use negative clock to change outputs with another  latch! View pair as one basic unit " masterslave flipflop " twice as much logic " output changes a few gate delays after the falling edge of clock but does not affect any cascaded flipflops master stage slave stage ' P' ' P C 5  pring 27 Lec. #5 equential Logic  5 The s Catching Problem! In first  stage of masterslave FF "  glitch on or while clock is high "caught" by master stage " Leads to constraints on logic to be hazardfree master stage P' ' slave stage ' P P' ' et eset s catch Master Outputs lave Outputs P C 5  pring 27 Lec. #5 equential Logic  6
9 FlipFlop! Make and complements of each other " Eliminates s catching problem " Can't just hold previous value (must have new value ready every clock period) " Value of just before clock goes low is what is stored in flipflop " Can make  flipflop by adding logic to make = + ' master stage slave stage ' P' ' ' P gates C 5  pring 27 Lec. #5 equential Logic  7 EdgeTriggered FlipFlops! More efficient solution: only 6 gates " sensitive to inputs only near edge of clock signal (not while high) Clk= holds ' when clock goes low C 5  pring 27 Lec. #5 equential Logic  8 holds when clock goes low negative edgetriggered flipflop (FF) 45 gate delays must respect setup and hold time constraints to successfully capture input characteristic equation (t+) =
10 EdgeTriggered FlipFlops (cont d)! tepbystep analysis Clk= Clk= when clock goes hightolow data is latched new new " old C 5  pring 27 Lec. #5 equential Logic  9 when clock is low data is held EdgeTriggered FlipFlops (cont d)! =, Clk High Act as inverters Clk= Hold state C 5  pring 27 Lec. #5 equential Logic  2
11 EdgeTriggered FlipFlops (cont d)! =, Clk High # # Clk= # C 5  pring 27 Lec. #5 equential Logic  2 # EdgeTriggered FlipFlops (cont d)! =, Clk LOW Act as inverters Clk= # # # C 5  pring 27 Lec. #5 equential Logic  22
12 EdgeTriggered FlipFlops (cont d)! Positive edgetriggered " Inputs sampled on rising edge; outputs change after rising edge! Negative edgetriggered flipflops " Inputs sampled on falling edge; outputs change after falling edge pos pos' neg neg' positive edgetriggered FF negative edgetriggered FF C 5  pring 27 Lec. #5 equential Logic  23 Negative Edge Trigger FF in Verilog module d_ff (q, q_bar, data, clk); input data, clk; output q, q_bar; reg q; assign q_bar = ~q; clk) begin q <= data; end endmodule C 5  pring 27 Lec. #5 equential Logic  24
13 Announcements! Cancel Lab ection Tu 2 PM starting next week " Young assigned to Th 58 PM lab " Allen assigned to W 58 PM lab (3 TAs!)! Homework #2 Bug " Problem 7(b) revised and posted to the web! tarting Thursday, lecture meets in 59 Mulford C 5  pring 27 Lec. #5 equential Logic  25 Timing Methodologies! ules for interconnecting components and clocks " Guarantee proper operation of system when strictly followed! Approach depends on building blocks used for memory elements " Focus on systems with edgetriggered flipflops # Found in programmable logic devices " Many custom integrated circuits focus on levelsensitive latches! Basic rules for correct timing: " () Correct inputs, with respect to time, are provided to the flipflops " (2) No flipflop changes state more than once per clocking event C 5  pring 27 Lec. #5 equential Logic  26
14 Timing Methodologies (cont d)! efinition of terms " clock: periodic event, causes state of memory element to change; can be rising or falling edge, or high or low level " setup time: minimum time before the clocking event by which the input must be stable (Tsu) " hold time: minimum time after the clocking event until which the input must remain stable (Th) input T su T h data clock there is a timing "window" around the clocking event during which the input must remain stable and unchanged in order to be recognized clock data clock stable changing C 5  pring 27 Lec. #5 equential Logic  27 Comparison of Latches and FlipFlops positive edgetriggered flipflop edge G transparent (levelsensitive) latch latch behavior is the same unless input changes while the clock is high C 5  pring 27 Lec. #5 equential Logic  28
15 Comparison of Latches and FlipFlops (cont d) Type When inputs are sampled When output is valid unclocked always propagation delay from input change latch levelsensitive clock high propagation delay from input change latch (Tsu/Th around falling or clock edge (whichever is later) edge of clock) masterslave clock high propagation delay from falling edge flipflop (Tsu/Th around falling of clock edge of clock) negative clock hitolo transition propagation delay from falling edge edgetriggered (Tsu/Th around falling of clock flipflop edge of clock) C 5  pring 27 Lec. #5 equential Logic  29 Typical Timing pecifications! Positive edgetriggered flipflop " etup and hold times " Minimum clock width " Propagation delays (low to high, high to low, max and typical) Tsu 2ns Th 5ns Tsu 2ns Th 5ns Tw 25ns Tplh 25ns 3ns Tphl 4ns 25ns all measurements are made from the clocking event that is, the rising edge of the clock C 5  pring 27 Lec. #5 equential Logic  3
16 Cascading Edgetriggered FlipFlops! hift register " New value goes into first stage " While previous value of first stage goes into second stage " Consider setup/hold/propagation delays (prop must be > hold) IN OUT IN C 5  pring 27 Lec. #5 equential Logic  3 Cascading Edgetriggered FlipFlops! hift register " New value goes into first stage " While previous value of first stage goes into second stage " Consider setup/hold/propagation delays (prop must be > hold) IN OUT elay Clk IN Clk C 5  pring 27 Lec. #5 equential Logic  32
17 Cascading Edgetriggered FlipFlops (cont d)! Why this works " Propagation delays exceed hold times " Clock width constraint exceeds setup time " This guarantees following stage will latch current value before it changes to new value In T su 4ns T p 3ns T su 4ns T p 3ns timing constraints guarantee proper operation of cascaded components assumes infinitely fast distribution of the clock T h 2ns T h 2ns C 5  pring 27 Lec. #5 equential Logic  33 Clock kew! The problem " Correct behavior assumes next state of all storage elements determined by all storage elements at the same time " ifficult in highperformance systems because time for clock to arrive at flipflop is comparable to delays through logic (and will soon become greater than logic delay) " Effect of skew on cascaded flipflops: In is a delayed version of original state: IN =, =, = due to skew, next state becomes: =, =, and not =, = C 5  pring 27 Lec. #5 equential Logic  34
18 ummary of Latches and FlipFlops! evelopment of FF " Levelsensitive used in custom integrated circuits # can be made with 4 switches " Edgetriggered used in programmable logic devices " Good choice for data storage register! Historically JK FF was popular but now never used " imilar to  but with  being used to toggle output (complement state) " Good in days of TTL/I (more complex input function: = J' + K' " Not a good choice for PLAs as it requires two inputs " Can always be implemented using FF! Preset and clear inputs are highly desirable on flipflops " Used at startup or to reset system to a known state C 5  pring 27 Lec. #5 equential Logic  35 FlipFlop Features! eset (set state to ): " ynchronous: new = ' old (when next clock edge arrives) " Asynchronous: doesn't wait for clock, quick but dangerous! Preset or set (set state to : (or sometimes P) " ynchronous: new = old + (when next clock edge arrives) " Asynchronous: doesn't wait for clock, quick but dangerous! Both reset and preset " new = ' old + (setdominant) " new = ' old + ' (resetdominant)! elective input capability (input enable/load): L or EN " Multiplexer at input: new = L' + L old " Load may/may not override reset/set (usually / have priority)! Complementary outputs:! and ' C 5  pring 27 Lec. #5 equential Logic  36
19 egisters! Collections of flipflops with similar controls and logic " tored values somehow related (e.g., form binary value) " hare clock, reset, and set lines " imilar logic at each stage! Examples " hift registers " Counters OUT OUT2 OUT3 OUT4 "" IN IN2 IN3 IN4 C 5  pring 27 Lec. #5 equential Logic  37 hift egister! Holds samples of input " tore last 4 input values in sequence " 4bit shift register: OUT OUT2 OUT3 OUT4 IN C 5  pring 27 Lec. #5 equential Logic  38
20 hift egister Verilog module shift_reg (out4, out3, out2, out, in, clk); output out4, out3, out2, out; input in, clk; reg out4, out3, out2, out; clk) begin out4 <= out3; out3 <= out2; out2 <= out; out <= in; end endmodule C 5  pring 27 Lec. #5 equential Logic  39 hift egister Verilog module shift_reg (out, in, clk); output [4:] out; input in, clk; reg [4:] out; clk) begin out <= {out[3:], in}; end endmodule C 5  pring 27 Lec. #5 equential Logic  4
21 Universal hift egister! Holds 4 values " erial or parallel inputs " erial or parallel outputs " Permits shift left or right " hift in new values from left or right output left_in left_out clear s s input right_out right_in clock clear sets the register contents and output to s and s determine the shift function s s function hold state shift right shift left load new input C 5  pring 27 Lec. #5 equential Logic  4 esign of Universal hift egister! Consider one of the four flipflops " New value at next clock cycle: Nth cell to Nth cell to N+th cell clear s s new value output output value of FF to left (shift right) output value of FF to right (shift left) input [N] (left) CLEA s and s 2 3 control mux Input[N] [N+] (right) C 5  pring 27 Lec. #5 equential Logic  42
22 Universal hift egister Verilog module univ_shift (out, lo, ro, in, li, ri, s, clr, clk); output [3:] out; output lo, ro; input [3:] in; input [:] s; input li, ri, clr, clk; reg [3:] out; assign lo = out[3]; assign ro = out[]; clk or clr) begin if (clr) out <= ; else case (s) 3: out <= in; 2: out <= {out[2:], ri}; : out <= {li, out[3:]}; : out <= out; endcase end endmodule C 5  pring 27 Lec. #5 equential Logic  43 hift egister Application! Paralleltoserial conversion for serial transmission parallel outputs parallel inputs serial transmission C 5  pring 27 Lec. #5 equential Logic  44
23 Pattern ecognizer! Combinational function of input samples " In this case, recognizing the pattern on the single input signal OUT OUT OUT2 OUT3 OUT4 IN C 5  pring 27 Lec. #5 equential Logic  45 Counters! equences through a fixed set of patterns " In this case,,,, " If one of the patterns is its initial state (by loading or set/reset) OUT OUT2 OUT3 OUT4 IN! Mobius (or Johnson) counter " In this case,,,,,,,, OUT OUT2 OUT3 OUT4 IN C 5  pring 27 Lec. #5 equential Logic  46
24 Binary Counter! Logic between registers (not just multiplexer) " XO decides when bit should be toggled " Always for loworder bit, only when first bit is true for second bit, and so on OUT OUT2 OUT3 OUT4 "" C 5  pring 27 Lec. #5 equential Logic  47 Binary Counter Verilog module shift_reg (out4, out3, out2, out, clk); output out4, out3, out2, out; input in, clk; reg out4, out3, out2, out; clk) begin out4 <= (out & out2 & out3) ^ out4; out3 <= (out & out2) ^ out3; out2 <= out ^ out2; out <= out ^ b ; end endmodule C 5  pring 27 Lec. #5 equential Logic  48
25 Binary Counter Verilog module shift_reg (out4, out3, out2, out, clk); output [4:] out; input in, clk; reg [4:] out; clk) out <= out + ; endmodule C 5  pring 27 Lec. #5 equential Logic  49 Fourbit Binary ynchronous UpCounter! tandard component with many applications " Positive edgetriggered FFs w/ sync load and clear inputs " Parallel load data from, C, B, A " Enable inputs: must be asserted to enable counting " CO: ripplecarry out used for cascading counters # high when counter is in its highest state # implemented using an AN gate (2) CO goes high (3) High order 4bits are incremented () Low order 4bits = EN C B A LOA CL CO C B A C 5  pring 27 Lec. #5 equential Logic  5
26 Offset Counters! tarting offset counters use of synchronous load " e.g.,,,,,,,,,,,...! Ending offset counter comparator for ending value " e.g.,,,,...,,,! Combinations of the above (start and stop value) C 5  pring 27 Lec. #5 equential Logic  5 "" "" "" "" "" "" "" "" "" "" "" EN CO C C B B A A LOA CL EN CO C C B B A A LOA CL equential Logic ummary! Fundamental building block of circuits with state " Latch and flipflop "  latch,  master/slave, master/slave, edgetriggered FF! Timing methodologies " Use of clocks " Cascaded FFs work because prop delays exceed hold times " Beware of clock skew! Basic registers " hift registers " Pattern detectors " Counters C 5  pring 27 Lec. #5 equential Logic  52
! Two inverters form a static memory cell " Will hold value as long as it has power applied
equential Logic! equential Circuits " imple circuits with feedback " Latches " Edgetriggered flipflops! Timing Methodologies " Cascading flipflops for proper operation " Clock skew! Basic egisters "
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