Digital Design, Kyung Hee Univ. Chapter 5. Synchronous Sequential Logic


 Ralph George
 11 months ago
 Views:
Transcription
1 Chapter 5. Synchronous Sequential Logic 1
2 5.1 Introduction Electronic products: ability to send, receive, store, retrieve, and process information in binary format Dependence on past values of inputs Sequential circuit act as storage elements and have memory FIGURE 5.1 Block diagram of sequential circuit 2
3 5.2 Sequential Circuits Output: a function of inputs and the present state of the storage elements Next state of the storage elements: a function of external inputs and the present state A sequential circuit is specified by a time sequence of inputs, outputs, and internal states vs. Combinational circuit depends on the present values of the inputs Classification (timing of signals) Asynchronous sequential circuit: at any instant of time and order Timedelay devices Internal propagation delay of logic gate Combinational circuit with feedback Unstable at times Synchronous sequential circuit= clocked sequential circuit: at discrete instants of time 3
4 Synchronous Sequential Circuit Signals affect the storage elements at only discrete instants of time Synchronization (by a timing device = clock generator, periodic train of clock pulses: Clock, Clk) Flipflop Storage elements used in clocked sequential circuits Capable of storing one bit of information FIGURE 5.2 Synchronous clocked sequential circuit 4 Considering propagation delay Occurring transition only at predetermined intervals dictated by the clock pulses
5 5.3 Storage elements: Latches Maintain a binary state indefinitely until directed by an input signal to switch states Various types of storage elements: number of inputs, manner affecting the binary state Level sensitive devices: Latch (operate with signal levels) For asynchronous sequential circuits Edgesensitive devices: Flipflops (controlled by a clock transition) For synchronous sequential circuits 5
6 SR Latch A circuit with two crosscoupled NOR gates or two crosscoupled NAND gates Two inputs: S for set and R for reset 00 : remain, latch 11 : unpredictable / undefined state / metastable state FIGURE 5.3 SR latch with NOR gates 6
7 S R Latch FIGURE 5.4 SR latch with NAND gates FIGURE 5.5 SR latch with control input 7
8 D Latch (Transparent Latch) To eliminate the undesirable condition of the indeterminate state in SR latch FIGURE 5.6 D latch FIGURE 5.7 Graphic symbols for latches 8
9 5.4 Storage Elements: FlipFlops Switched the state of a latch or flipflop by a change in the control input Momentary change = trigger the flipflop Employ a common clock Trigger it only during a signal transition Positive edge / negative edge Flipflop Employ two latches Trigger only during a signal transition of the synchronizing signal FIGURE 5.8 Clock response in latch and flipflop 9
10 EdgeTriggered D FlipFlop Two D latches and an inverter Sampling D input and changing its output at the negative edge of the synchronizing or controlling clock Output value stored in the master stage immediately before the negative edge occurred (1) the output may change only once (2) a change in the output is triggered by the negative edge of the clock (3) the change may occur only during the clock s negative level FIGURE 5.9 Master slave D flipflop 10
11 EdgeTriggered D Flipflop Used three SR latches When Clk=0, S=R=1 (no change) When Clk changes from 0 to 1, If D=0, R=0 (Reset state) If D=1, S=0 (Set state) T2 FIGURE 5.10 Dtype positiveedgetriggered flipflop Clk D X 0 1 X 1 0 T T S R Q T1 11
12 Setup time: minimum time of D input maintained at a constant value prior to the occurrence of the clock transition Hold time: minimum time of D input maintained at a constant value after the clock transition Propagation delay time: interval between the trigger edge and the stabilization of the output to a new state Dynamic indicator(>) Edgetriggered D flipflop: the most economical and efficient FIGURE 5.11 Graphic symbol for edgetriggered D flipflop 12
13 JK FlipFlop Operations Set as 1 (J=1, K=0) Reset as 0 (J=0, K=1) Complement its output (J=K=1) Unchanged (J=K=0) Q(t+1)=JQ +K Q 13 FIGURE 5.12 JK flipflop
14 T FlipFlop D=TQ +T Q FIGURE 5.13 T flipflop Q(t+1)=D Q(t+1)=TQ +T Q 14
15 Characteristic Tables / Equations Characteristic table Logical properties of a flipflop by describing its operation in tabular form A function of the inputs and the present state Characteristic equation Express algebraically D F/F: Q(t+1)=D JK F/F: Q(t+1)=JQ +K Q T F/F: Q(t+1)=TQ +T Q Direct Inputs Asynchronous inputs to force the flipflop to a particular state independently of the clock Preset/Direct set: set F/F as 1 Clear/Direct reset: clear F/F as 0 Set all flipflops in the system to a known starting state prior to the clocked operation 15
16 FIGURE 5.14 D flipflop with asynchronous reset
17 5.5 Analysis of Clocked Sequential Circuits Analysis: behavior of a given circuit under certain operating conditions Clocked sequential circuit including flipflops is determined from the inputs, the outputs, and the internal state of its F/F Representation Algebraic representation State table State diagram Time sequence of inputs, outputs, and internal states 17
18 State Equations (Transition Equation) The next state as a function of the present state and inputs D F/F: Q(t+1)=D A(t+1)=A(t)x(t)+B(t)x(t) B(t+1)=A (t)x(t) y(t)=[a(t)+b(t)]x (t) Zerodetector FIGURE 5.15 Example of sequential circuit 18
19 State Table Enumerate time sequence of inputs, outputs, and internal F/F states in a state table (a transition table) A(t+1)=Ax+Bx B(t+1)=A x y=ax +Bx m flipflops n inputs 2^(m+n) rows in the state table Next states: m columns for each 19
20 State Diagram State: circle Transitions between states (directed lines) State of F/F (binary number in the circle) Input/output Circuit diagram Equations State table State diagram 0/0 1/0 0/ /1 1/0 0/1 1/ /0
21 FlipFlop Input Equations 21
22 Analysis with DF/F State equation = input equation FIGURE 5.17 with D flipflop Sequential circuit 22
23 1.Determine the flipflop input equations in terms of the present state and input variables 2.List the binary values of each input equation 3.Use the corresponding flipflop characteristic table to determine the next state values in the state table FIGURE 5.18 Sequential circuit with JK flipflop 23
24 24
25 Input equation 1. Determine the flipflop input equations in terms of the present state and input variables 2. Substitute the input equations into the flipflop characteristic equation to obtain the state equations 3. Use the corresponding state equation to determine the next state values in the state table Q(t+1)=JQ +K Q Characteristic equation State equation FIGURE 5.19 of Fig State diagram of the circuit 25
26 26
27 Analysis with T F/F Characteristic equation Output equation State equation Input equation FIGURE 5.20 Sequential circuit with T flipflops (Binary Counter) 27
28 Mealy and Moore Models of FSM Moore model: outputs are synchronized with clock Mealy model: value presented immediately before the active edge of the clock FIGURE 5.21 Block diagrams of Mealy and Moore state machines 28
29 5.7 State Reduction and Assignment Analysis: a circuit diagram state table or diagram Design(synthesis): a set of specifications logic diagram Simplify a design by reducing the number of gates and F/Fs State reduction To find ways of reducing the number of states in a sequential circuit without altering the inputoutput relationships Important only inputoutput sequences State a a b c d e f f g f g a Input output
30 State Reduction Two states are said to be equivalent if, for each member of the set of inputs, they give exactly the same output and send the circuit either to the same state or to an equivalent state 30
31 State a a b c d e f f g f g a Input output
32 State Assignment Transition table 32
33 5.8 Design Procedure Manal design method using D, JK, and T F/F Start from a set of specifications and culminate in a logic diagram (or list of Boolean functions) 1 st step: obtain a state table or a state diagram Synchronous sequential circuit = F/F + combinational gates 1. From the word description and specifications of the desired operation, derive a state diagram for the circuit 2. Reduce the number of states if necessary 3. Assign binary values to the states 4. Obtain the binarycoded state table 5. Choose the type of flipflops to be used 6. Derive the simplified flipflop input equations and output equations 7. Draw the logic diagram Steps 4~7: welldefined procedure=synthesis 33
34 Example: How obtained a state diagram Detect a sequence of three or more consecutive 1 s in a string of bits coming through an input line FIGURE 5.27 State diagram for sequence detector 34
35 Synthesis using D F/F Need to assign binary codes to the states and list the state table Choose two D F/F to represent the four states 35
36 FIGURE 5.29 Logic diagram of a Mooretype sequence detector 36
37 Excitation Tables Necessary to derive a functional relationship between the state table and the input equations (JK and T F/F) Excitation table: list the required inputs for a given change of state 37
38 Synthesis using JK F/F Input equations derived from the excitation table FIGURE 5.30 Maps for J and K input equations 38
39 FIGURE 5.31 Logic diagram for sequential circuit with JK flipflops 39
40 Synthesis using T F/F Binary counter (0 to 2 n 1) 40
41 FIGURE 5.34 Logic diagram of threebit binary counter 41
Chapter 5: Synchronous Sequential Logic
Chapter 5: Synchronous Sequential Logic NCNU_2016_DD_5_1 Digital systems may contain memory for storing information. Combinational circuits contains no memory elements the outputs depends only on the inputs
More informationChapter 5 Synchronous Sequential Logic
EEA051  Digital Logic 數位邏輯 Chapter 5 Synchronous Sequential Logic 吳俊興國立高雄大學資訊工程學系 December 2005 Chapter 5 Synchronous Sequential Logic 51 Sequential Circuits 52 Latches 53 FlipFlops 54 Analysis of
More informationDigital Logic Design Sequential Circuits. Dr. Basem ElHalawany
Digital Logic Design Sequential Circuits Dr. Basem ElHalawany Combinational vs Sequential inputs X Combinational Circuits outputs Z A combinational circuit: At any time, outputs depends only on inputs
More informationCHAPTER1: Digital Logic Circuits
CS224: Computer Organization S.KHABET CHAPTER1: Digital Logic Circuits 1 Sequential Circuits Introduction Composed of a combinational circuit to which the memory elements are connected to form a feedback
More informationCHAPTER 4: Logic Circuits
CHAPTER 4: Logic Circuits II. Sequential Circuits Combinational circuits o The outputs depend only on the current input values o It uses only logic gates, decoders, multiplexers, ALUs Sequential circuits
More information`COEN 312 DIGITAL SYSTEMS DESIGN  LECTURE NOTES Concordia University
`OEN 32 IGITL SYSTEMS ESIGN  LETURE NOTES oncordia University hapter 5: Synchronous Sequential Logic NOTE: For more eamples and detailed description of the material in the lecture notes, please refer
More informationCombinational / Sequential Logic
Digital Circuit Design and Language Combinational / Sequential Logic Chang, Ik Joon Kyunghee University Combinational Logic + The outputs are determined by the present inputs + Consist of input/output
More informationELCT201: DIGITAL LOGIC DESIGN
ELCT201: DIGITAL LOGIC DESIGN Dr. Eng. Haitham Omran, haitham.omran@guc.edu.eg Dr. Eng. Wassim Alexan, wassim.joseph@guc.edu.eg Lecture 6 Following the slides of Dr. Ahmed H. Madian ذو الحجة 1438 ه Winter
More informationOther FlipFlops. Lecture 27 1
Other FlipFlops Other types of flipflops can be constructed by using the D flipflop and external logic. Two flipflops less widely used in the design of digital systems are the JK and T flipflops.
More informationExperiment 8 Introduction to Latches and FlipFlops and registers
Experiment 8 Introduction to Latches and FlipFlops and registers Introduction: The logic circuits that have been used until now were combinational logic circuits since the output of the device depends
More informationECE 25 Introduction to Digital Design. Chapter 5 Sequential Circuits ( ) Part 1 Storage Elements and Sequential Circuit Analysis
EE 25 Introduction to igital esign hapter 5 Sequential ircuits (5.15.4) Part 1 Storage Elements and Sequential ircuit Analysis Logic and omputer esign Fundamentals harles Kime & Thomas Kaminski 2008 Pearson
More informationECE 341. Lecture # 2
ECE 341 Lecture # 2 Instructor: Zeshan Chishti zeshan@pdx.edu October 1, 2014 Portland State University Announcements Course website reminder: http://www.ece.pdx.edu/~zeshan/ece341.htm Homework 1: Will
More informationLecture 8: Sequential Logic
Lecture 8: Sequential Logic Last lecture discussed how we can use digital electronics to do combinatorial logic we designed circuits that gave an immediate output when presented with a given set of inputs
More informationSequential Circuits: Latches & FlipFlops
Sequential Circuits: Latches & FlipFlops Overview Storage Elements Latches SR, JK, D, and T Characteristic Tables, Characteristic Equations, Eecution Tables, and State Diagrams Standard Symbols FlipFlops
More informationCHAPTER 1 LATCHES & FLIPFLOPS
CHAPTER 1 LATCHES & FLIPFLOPS 1 Outcome After learning this chapter, student should be able to; Recognize the difference between latches and flipflops Analyze the operation of the flip flop Draw the output
More informationUnit 9 Latches and FlipFlops. Dept. of Electrical and Computer Eng., NCTU 1
Unit 9 Latches and FlipFlops Dept. of Electrical and Computer Eng., NCTU 1 9.1 Introduction Dept. of Electrical and Computer Eng., NCTU 2 What is the characteristic of sequential circuits in contrast
More informationYEDITEPE UNIVERSITY DEPARTMENT OF COMPUTER ENGINEERING. EXPERIMENT VIII: FLIPFLOPS, COUNTERS 2014 Fall
YEDITEPE UNIVERSITY DEPARTMENT OF COMPUTER ENGINEERING EXPERIMENT VIII: FLIPFLOPS, COUNTERS 2014 Fall Objective:  Dealing with the operation of simple sequential devices. Learning invalid condition in
More informationLAB #4 SEQUENTIAL LOGIC CIRCUIT
LAB #4 SEQUENTIAL LOGIC CIRCUIT OBJECTIVES 1. To learn how basic sequential logic circuit works 2. To test and investigate the operation of various latch and flip flop circuits INTRODUCTIONS Sequential
More informationIntroduction. NAND Gate Latch. Digital Logic Design 1 FLIPFLOP. Digital Logic Design 1
2007 Introduction BK TP.HCM FLIPFLOP So far we have seen Combinational Logic The output(s) depends only on the current values of the input variables Here we will look at Sequential Logic circuits The
More informationIntroduction to Microprocessor & Digital Logic
ME262 Introduction to Microprocessor & Digital Logic (Sequential Logic) Summer 2 Sequential Logic Definition The output(s) of a sequential circuit depends d on the current and past states of the inputs,
More information1. Convert the decimal number to binary, octal, and hexadecimal.
1. Convert the decimal number 435.64 to binary, octal, and hexadecimal. 2. Part A. Convert the circuit below into NAND gates. Insert or remove inverters as necessary. Part B. What is the propagation delay
More informationEngr354: Digital Logic Circuits
Engr354: igital Circuits Chapter 7 Sequential Elements r. Curtis Nelson Sequential Elements In this chapter you will learn about: circuits that can store information; Basic cells, latches, and flipflops;
More informationFinal Exam review: chapter 4 and 5. Supplement 3 and 4
Final Exam review: chapter 4 and 5. Supplement 3 and 4 1. A new type of synchronous flipflop has the following characteristic table. Find the corresponding excitation table with don t cares used as much
More informationMore on FlipFlops Digital Design and Computer Architecture: ARM Edition 2015 Chapter 3 <98> 98
More on FlipFlops Digital Design and Computer Architecture: ARM Edition 2015 Chapter 3 98 Review: Bit Storage SR latch S (set) Q R (reset) Levelsensitive SR latch S S1 C R R1 Q D C S R D latch Q
More information6. Sequential Logic FlipFlops
ection 6. equential Logic FlipFlops Page of 5 6. equential Logic FlipFlops ombinatorial components: their output values are computed entirely from their present input values. equential components: their
More informationSolution to Digital Logic )What is the magnitude comparator? Design a logic circuit for 4 bit magnitude comparator and explain it,
Solution to Digital Logic 2067 Solution to digital logic 2067 1.)What is the magnitude comparator? Design a logic circuit for 4 bit magnitude comparator and explain it, A Magnitude comparator is a combinational
More informationChapter 4. Logic Design
Chapter 4 Logic Design 4.1 Introduction. In previous Chapter we studied gates and combinational circuits, which made by gates (AND, OR, NOT etc.). That can be represented by circuit diagram, truth table
More informationELE2120 Digital Circuits and Systems. Tutorial Note 7
ELE2120 Digital Circuits and Systems Tutorial Note 7 Outline 1. Sequential Circuit 2. Gated SR Latch 3. Gated Dlatch 4. EdgeTriggered D FlipFlop 5. Asynchronous and Synchronous reset Sequential Circuit
More informationThe basic logic gates are the inverter (or NOT gate), the AND gate, the OR gate and the exclusiveor gate (XOR). If you put an inverter in front of
1 The basic logic gates are the inverter (or NOT gate), the AND gate, the OR gate and the exclusiveor gate (XOR). If you put an inverter in front of the AND gate, you get the NAND gate etc. 2 One of the
More informationLogic Design II (17.342) Spring Lecture Outline
Logic Design II (17.342) Spring 2012 Lecture Outline Class # 05 February 23, 2012 Dohn Bowden 1 Today s Lecture Analysis of Clocked Sequential Circuits Chapter 13 2 Course Admin 3 Administrative Admin
More informationObjectives. Combinational logics Sequential logics Finite state machine Arithmetic circuits Datapath
Objectives Combinational logics Sequential logics Finite state machine Arithmetic circuits Datapath In the previous chapters we have studied how to develop a specification from a given application, and
More informationUNIT3: SEQUENTIAL LOGIC CIRCUITS
UNIT3: SEQUENTIAL LOGIC CIRCUITS STRUCTURE 3. Objectives 3. Introduction 3.2 Sequential Logic Circuits 3.2. NAND Latch 3.2.2 RS FlipFlop 3.2.3 D FlipFlop 3.2.4 JK FlipFlop 3.2.5 Edge Triggered RS FlipFlop
More informationCSE115: Digital Design Lecture 23: Latches & FlipFlops
Faculty of Engineering CSE115: Digital Design Lecture 23: Latches & FlipFlops Sections 7.17.2 Suggested Reading A Generic Digital Processor Building Blocks for Digital Architectures INPUT  OUTPUT Interconnect:
More informationProblems with DLatch
Problems with Latch If changes while is true, the new value of will appear at the output. The latch is transparent. If the stored value can change state more than once during a single clock pulse, the
More informationDepartment of CSIT. Class: B.SC Semester: II Year: 2013 Paper Title: Introduction to logics of Computer Max Marks: 30
Department of CSIT Class: B.SC Semester: II Year: 2013 Paper Title: Introduction to logics of Computer Max Marks: 30 Section A: (All 10 questions compulsory) 10X1=10 Very Short Answer Questions: Write
More informationSequential Logic and Clocked Circuits
Sequential Logic and Clocked Circuits Clock or Timing Device Input Variables State or Memory Element Combinational Logic Elements From combinational logic, we move on to sequential logic. Sequential logic
More informationSEQUENTIAL LOGIC. Satish Chandra Assistant Professor Department of Physics P P N College, Kanpur
SEQUENTIAL LOGIC Satish Chandra Assistant Professor Department of Physics P P N College, Kanpur www.satish0402.weebly.com OSCILLATORS Oscillators is an amplifier which derives its input from output. Oscillators
More informationReview of FlipFlop. Divya Aggarwal. Student, Department of Physics and AstroPhysics, University of Delhi, New Delhi. their state.
pp. 49 Krishi Sanskriti Publications http://www.krishisanskriti.org/jbaer.html Review of FlipFlop Divya Aggarwal Student, Department of Physics and AstroPhysics, University of Delhi, New Delhi Abstract:
More informationEKT 121/4 ELEKTRONIK DIGIT 1
EKT 121/4 ELEKTRONIK DIGIT 1 Kolej Universiti Kejuruteraan Utara Malaysia Bistable Storage Devices and Related Devices Introduction Latches and flipflops are the basic singlebit memory elements used
More information3 FlipFlops. The latch is a logic block that has 2 stable states (0) or (1). The RS latch can be forced to hold a 1 when the Set line is asserted.
3 FlipFlops Flipflops and latches are digital memory circuits that can remain in the state in which they were set even after the input signals have been removed. This means that the circuits have a memory
More informationDigital Fundamentals: A Systems Approach
Digital Fundamentals: A Systems Approach Counters Chapter 8 A System: Digital Clock Digital Clock: Counter Logic Diagram Digital Clock: Hours Counter & Decoders Finite State Machines Moore machine: One
More informationLogic. Andrew Mark Allen March 4, 2012
Logic Andrew Mark Allen  05370299 March 4, 2012 Abstract NAND gates and inverters were used to construct several different logic gates whose operations were investigate under various inputs. Then the
More informationFlipFlops and Sequential Circuit Design
FlipFlops and Sequential Circuit Design ECE 52 Summer 29 Reading ssignment Brown and Vranesic 7 FlipFlops, Registers, Counters and a Simple Processor 7.5 T FlipFlop 7.5. Configurable FlipFlops 7.6
More informationDIGITAL SYSTEM FUNDAMENTALS (ECE421) DIGITAL ELECTRONICS FUNDAMENTAL (ECE422) LATCHES and FLIPFLOPS
COURSE / CODE DIGITAL SYSTEM FUNDAMENTALS (ECE421) DIGITAL ELECTRONICS FUNDAMENTAL (ECE422) LATCHES and FLIPFLOPS In the same way that logic gates are the building blocks of combinatorial circuits, latches
More informationCHAPTER 6 COUNTERS & REGISTERS
CHAPTER 6 COUNTERS & REGISTERS 6.1 Asynchronous Counter 6.2 Synchronous Counter 6.3 State Machine 6.4 Basic Shift Register 6.5 Serial In/Serial Out Shift Register 6.6 Serial In/Parallel Out Shift Register
More informationPRE J. Figure 25.1a JK flipflop with Asynchronous Preset and Clear inputs
Asynchronous Preset and Clear Inputs The SR, JK and D inputs are known as synchronous inputs because the outputs change when appropriate input values are applied at the inputs and a clock signal is applied
More informationDIGITAL SYSTEM DESIGN UNIT I (2 MARKS)
DIGITAL SYSTEM DESIGN UNIT I (2 MARKS) 1. Convert Binary number (111101100) 2 to Octal equivalent. 2. Convert Binary (1101100010011011) 2 to Hexadecimal equivalent. 3. Simplify the following Boolean function
More informationASYNCHRONOUS COUNTER CIRCUITS
ASYNCHRONOUS COUNTER CIRCUITS Asynchronous counters do not have a common clock that controls all the Hipflop stages. The control clock is input into the first stage, or the LSB stage of the counter. The
More informationChapter 6 Registers and Counters
EEA051  Digital Logic 數位邏輯 Chapter 6 Registers and Counters 吳俊興國立高雄大學資訊工程學系 January 2006 Chapter 6 Registers and Counters 61 Registers 62 Shift Registers 63 Ripple Counters 64 Synchronous Counters
More informationESE 570 STATIC SEQUENTIAL CMOS LOGIC CELLS. Kenneth R. Laker, University of Pennsylvania, updated 25Mar15
ESE 570 STATIC SEQUENTIAL CMOS LOGIC CELLS 1 Classes of Logic Circuits two stable op. pts. Latch level triggered. FlipFlop edge triggered. one stable op. pt. Oneshot single pulse output no stable op.
More informationLast time, we saw how latches can be used as memory in a circuit
FlipFlops Last time, we saw how latches can be used as memory in a circuit Latches introduce new problems: We need to know when to enable a latch We also need to quickly disable a latch In other words,
More informationReview of digital electronics. Storage units Sequential circuits Counters Shifters
Review of digital electronics Storage units Sequential circuits ounters Shifters ounting in Binary A counter can form the same pattern of 0 s and 1 s with logic levels. The first stage in the counter represents
More informationELE2120 Digital Circuits and Systems. Tutorial Note 8
ELE2120 Digital Circuits and Systems Tutorial Note 8 Outline 1. Register 2. Counters 3. Synchronous Counter 4. Asynchronous Counter 5. Sequential Circuit Design Overview 1. Register Applications: temporally
More informationEECS150  Digital Design Lecture 19  Finite State Machines Revisited
EECS150  Digital Design Lecture 19  Finite State Machines Revisited April 2, 2013 John Wawrzynek Spring 2013 EECS150  Lec19fsm Page 1 Finite State Machines (FSMs) FSM circuits are a type of sequential
More informationComputer Architecture and Organization
A1 Appendix A  Digital Logic Computer Architecture and Organization Miles Murdocca and Vincent Heuring Appendix A Digital Logic A2 Appendix A  Digital Logic Chapter Contents A.1 Introduction A.2 Combinational
More informationELEN Electronique numérique
ELEN0040  Electronique numérique Patricia ROUSSEAUX Année académique 20142015 CHAPITRE 5 Sequential circuits design  Timing issues ELEN0040 5228 1 Sequential circuits design 1.1 General procedure 1.2
More informationP U Q Q*
ECE 27 Learning Outcome 3   Practice Exam / Solution LEARNING OUTCOME #3: an ability to analyze and design sequential logic circuits. Multiple Choice select the single most appropriate response for each
More informationReport on 4bit Counter design Report 1, 2. Report on D Flipflop. Course project for ECE533
Report on 4bit Counter design Report 1, 2. Report on D Flipflop Course project for ECE533 I. Objective: REPORTI The objective of this project is to design a 4bit counter and implement it into a chip
More informationWINTER 15 EXAMINATION Model Answer
Important Instructions to examiners: 1) The answers should be examined by key words and not as wordtoword as given in the model answer scheme. 2) The model answer and the answer written by candidate
More informationExperiment # 9. Clock generator circuits & Counters. Digital Design LAB
Digital Design LAB Islamic University Gaza Engineering Faculty Department of Computer Engineering Fall 2012 ECOM 2112: Digital Design LAB Eng: Ahmed M. Ayash Experiment # 9 Clock generator circuits & Counters
More informationDigital Principles and Design
Digital Principles and Design Donald D. Givone University at Buffalo The State University of New York Grauu Boston Burr Ridge, IL Dubuque, IA Madison, Wl New York San Francisco St. Louis Bangkok Bogota
More informationUNIT 1: DIGITAL LOGICAL CIRCUITS What is Digital Computer? OR Explain the block diagram of digital computers.
UNIT 1: DIGITAL LOGICAL CIRCUITS What is Digital Computer? OR Explain the block diagram of digital computers. Digital computer is a digital system that performs various computational tasks. The word DIGITAL
More informationSt. MARTIN S ENGINEERING COLLEGE
St. MARTIN S ENGINEERING COLLEGE Dhulapally, Kompally, Secunderabad500014. Branch Year&Sem Subject Name : Electronics and Communication Engineering : II B. Tech I Semester : SWITCHING THEORY AND LOGIC
More informationR13 SET  1 '' ''' '' ' '''' Code No: RT21053
SET  1 1. a) What are the characteristics of 2 s complement numbers? b) State the purpose of reducing the switching functions to minimal form. c) Define half adder. d) What are the basic operations in
More informationName Of The Experiment: Sequential circuit design Latch, Flipflop and Registers
EEE 304 Experiment No. 07 Name Of The Experiment: Sequential circuit design Latch, Flipflop and Registers Important: Submit your Prelab at the beginning of the lab. Prelab 1: Construct a SR Latch and
More information10.1 Sequential logic circuits are a type of logic circuit where the output of the circuit depends not only on
CALIFORNIA STATE UNIVERSITY LOS ANGELES Department of Electrical and Computer Engineering EE2449 Digital Logic Lab EXPERIMENT 10 INTRODUCTION TO SEQUENTIAL LOGIC EE 2449 Experiment 10 nwp & jgl 1/1/18
More informationFE REVIEW LOGIC. The AND gate. The OR gate A B AB A B A B 0 1 1
FE REVIEW LOGIC The AD gate f A, B AB The AD gates output will achieve its active state, ACTIVE HIGH, when BOTH of its inputs achieve their active state, ACTIVE E HIGH. A B AB f ( A, B) AB m (3) The OR
More informationDIGITAL TECHNICS II. Dr. Bálint Pődör. Óbuda University, Microelectronics and Technology Institute
26.3.9. DIGITAL TECHNICS II Dr. Bálint Pődör Óbuda University, Microelectronics and Technology Institute 5. LECTURE: ANALYSIS AND SYNTHESIS OF SYNCHRONOUS SEQUENTIAL CIRCUITS 2nd (Spring) term 25/26 5.
More informationEKT 121/4 ELEKTRONIK DIGIT 1
EKT 2/4 ELEKTRONIK DIGIT Kolej Universiti Kejuruteraan Utara Malaysia Sequential Logic Circuits  COUNTERS  LATCHES (review) SR R Latch SR R Latch ActiveLOW input INPUTS OUTPUTS S R Q Q COMMENTS Q
More informationDIGITAL ELECTRONICS MCQs
DIGITAL ELECTRONICS MCQs 1. A 8bit serial in / parallel out shift register contains the value 8, clock signal(s) will be required to shift the value completely out of the register. A. 1 B. 2 C. 4 D. 8
More informationOutline. CPE/EE 422/522 Advanced Logic Design L03. Review: Clocked D FlipFlop with Risingedge Trigger. Sequential Networks
Outline PE/EE 422/522 Advanced Logic Design L3 Electrical and omputer Engineering University of Alabama in Huntsville What we know ombinational Networks Analysis, Synthesis, Simplification, Buiing Blocks,
More informationCS6201 UNIT I PARTA. Develop or build the following Boolean function with NAND gate F(x,y,z)=(1,2,3,5,7).
VALLIAMMAI ENGINEERING COLLEGE SRM Nagar, Kattankulathur603203 DEPARTMENT OF COMPUTER SCIENCE AND ENGINEERING Academic Year: 201516 BANK  EVEN SEMESTER UNIT I PARTA 1 Find the octal equivalent of hexadecimal
More informationDALHOUSIE UNIVERSITY Department of Electrical & Computer Engineering Digital Circuits  ECED 220. Experiment 4  Latches and FlipFlops
DLHOUSIE UNIVERSITY Department of Electrical & Computer Engineering Digital Circuits  ECED 0 Experiment  Latches and FlipFlops Objectives:. To implement an RS latch memory element. To implement a JK
More information11.1 As mentioned in Experiment 10, sequential logic circuits are a type of logic circuit where the output
EE 2449 Experiment JL and NWP //8 CALIFORNIA STATE UNIVERSITY LOS ANGELES Department of Electrical and Computer Engineering EE2449 Digital Logic Lab EXPERIMENT SEQUENTIAL CIRCUITS Text: Mano and Ciletti,
More informationBachelor Level/ First Year/ Second Semester/ Science Full Marks: 60 Computer Science and Information Technology (CSc. 151) Pass Marks: 24
2065 Computer Science and Information Technology (CSc. 151) Pass Marks: 24 Time: 3 hours. Candidates are required to give their answers in their own words as for as practicable. Attempt any TWO questions:
More informationSection I: Digital System Analysis and Review
Section I: Digital System Analysis and Review CEG 36/56; EE 45/65 Digital System Design Dr. Travis Doom, Assistant Professor Department of Computer Science and Engineering Wright State University Thanks
More informationSequential Circuit Design: Part 1
Sequential Circuit esign: Part 1 esign of memory elements Static latches Pseudostatic latches ynamic latches Timing parameters Twophase clocking Clocked inverters James Morizio 1 Sequential Logic FFs
More informationRegisters & Counters. Logic and Digital System Design  CS 303 Erkay Savaş Sabanci University
Registers & ounters Logic and igital System esign  S 33 Erkay Savaş Sabanci University Registers Registers like counters are clocked sequential circuits A register is a group of flipflops Each flipflop
More informationChapter 9. Design of Counters
Chapter 9 Design of Counters 9.0 Introduction Counter is another class of sequential circuits that tally a series of input pulses which may be regular or irregular in nature. Counter can be divided into
More informationEE 121 June 4, 2002 Digital Design Laboratory Handout #34 CLK
EE 2 June 4, 22 igital esign Laboratory Handout #34 Midterm Examination #2 Solutions Open book, open notes. Time limit: 75 minutes. (2 points) Setup and hold times. The flipflops below have setup time
More informationCMOS Latches and FlipFlops
CMOS Latches and FlipFlops João Canas Ferreira University of Porto Faculty of Engineering 20160504 Topics 1 General Aspects 2 Circuits based on positive feedback 3 Circuits based on charge storage João
More informationVU Mobile Powered by S NO Group
Question No: 1 ( Marks: 1 )  Please choose one A 8bit serial in / parallel out shift register contains the value 8, clock signal(s) will be required to shift the value completely out of the register.
More informationCH 11 Latches and FlipFlops
CH Latches and FlipFlops Flops Lecturer : 吳安宇 Date : 25.2.2 Ver.. ACCESS IC LAB v. Introduction v.2 SetReset Latch v.3 Gated D Latch Outline v.4 EdgeTriggered D FlipFlop v.5 SR FlipFlop v.6 JK FlipFlop
More informationLogic Circuits. A gate is a circuit element that operates on a binary signal.
Logic Circuits gate is a circuit element that operates on a binary signal. Logic operations typically have three methods of description:. Equation symbol 2. Truth table 3. Circuit symbol The binary levels
More informationDigital System Design
Digital System Design by Dr. Lesley Shannon Email: lshannon@ensc.sfu.ca Course Website: http://www.ensc.sfu.ca/~lshannon/courses/ensc350 Simon Fraser University Slide Set: 8 Date: February 9, 2009 Timing
More informationa) (A+B) (C+D) b) AB+CD c) AC+BD d) (A+D) (B+C)
1. Implement XNOR gate using NAND. 2. The output of the following circuit is a) (A+B) (C+D) b) AB+CD c) AC+BD d) (A+D) (B+C) 3. Which of the following memory element can have possible race condition. a)
More informationEECS 3201: Digital Logic Design Lecture 9. Ihab Amer, PhD, SMIEEE, P.Eng.
EECS 3201: Digital Logic Design Lecture 9 Ihab Amer, PhD, SMIEEE, P.Eng. Progress so far 2 Digital Logic Classification Digital Logic Combinational o/p s depend on i/p s only E.g. Logic Gates Sequential
More informationcs281: Introduction to Computer Systems Lab07  Sequential Circuits II: Ant Brain
cs281: Introduction to Computer Systems Lab07  Sequential Circuits II: Ant Brain 1 Problem Statement Obtain the file ant.tar from the class webpage. After you untar this file in an empty directory, you
More informationPart 4: Introduction to Sequential Logic. Basic Sequential structure. Positiveedgetriggered D flipflop. Flipflops classified by inputs
Part 4: Introduction to Sequential Logic Basic Sequential structure There are two kinds of components in a sequential circuit: () combinational blocks (2) storage elements Combinational blocks provide
More informationSynchronous sequential circuits
8.6.5 Synchronous sequential Table of content. Combinational circuit design. Elementary combinatorial for data transmission. Memory structures 4. Programmable logic devices 5. Algorithmic minimization
More informationSequential Logic Circuit
Prof.Manoj avedia ( 98674297 ) (urallalone@yahoo.com) ` 4 Sequential Logic ircuit hapter4(hours : Marks: )(269 Principle of Digital Electronics) SEUENTIL LOGI IRUIT 4. Introduction to Sequential Logic
More informationModule for Lab #16: Basic Memory Devices
Module for Lab #16: Basic Memory evices evision: November 14, 2004 LAB Overview This lab introduces the concept of electronic memory. Memory circuits store the voltage present on an input signal (LHV or
More information11. Sequential Elements
11. Sequential Elements Jacob Abraham Department of Electrical and Computer Engineering The University of Texas at Austin VLSI Design Fall 2017 October 11, 2017 ECE Department, University of Texas at Austin
More informationEXPERIMENT: 1. Graphic Symbol: OR: The output of OR gate is true when one of the inputs A and B or both the inputs are true.
EXPERIMENT: 1 DATE: VERIFICATION OF BASIC LOGIC GATES AIM: To verify the truth tables of Basic Logic Gates NOT, OR, AND, NAND, NOR, ExOR and ExNOR. APPARATUS: mention the required IC numbers, Connecting
More informationModule 4:FLIPFLOP. Quote of the day. Never think you are nothing, never think you are everything, but think you are something and achieve anything.
Module 4:FLIPFLOP Quote of the day Never think you are nothing, never think you are everything, but think you are something and achieve anything. Albert Einstein Sequential and combinational circuits
More informationFlipFlops and Registers
The slides included herein were taken from the materials accompanying Fundamentals of Logic Design, 6 th Edition, by Roth and Kinney, and were used with permission from Cengage Learning. FlipFlops and
More informationDecade Counters Mod5 counter: Decade Counter:
Decade Counters We can design a decade counter using cascade of mod5 and mod2 counters. Mod2 counter is just a single flipflop with the two stable states as 0 and 1. Mod5 counter: A typical mod5
More informationDr. Shahram Shirani COE2DI4 Midterm Test #2 Nov 19, 2008
Page 1 Dr. Shahram Shirani COE2DI4 Midterm Test #2 Nov 19, 2008 Instructions: This examination paper includes 13 pages and 20 multiplechoice questions starting on page 3. You are responsible for ensuring
More informationFig11 2bit asynchronous counter
Digital electronics 1Sequential circuit counters Such a group of flip flops is a counter. The number of flipflops used and the way in which they are connected determine the number of states and also
More informationFor Teacher's Use Only Q Total No. Marks. Q No Q No Q No
FINALTERM EXAMINATION Spring 2010 CS302 Digital Logic Design (Session  4) Time: 90 min Marks: 58 For Teacher's Use Only Q 1 2 3 4 5 6 7 8 Total No. Marks Q No. 9 10 11 12 13 14 15 16 Marks Q No. 17 18
More information