Lecture 11: Sequential Circuit Design

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1 Lecture 11: Sequential Circuit esign

2 Outline q Sequencing q Sequencing Element esign q Max and Min-elay q Clock Skew q Time Borrowing q Two-Phase Clocking 2

3 Sequencing q Combinational logic output depends on current inputs q Sequential logic output depends on current and previous inputs Requires separating previous, current, and future events Called state or tokens Examples: FSM, pipeline in CL out CL CL Finite State Machine Pipeline 3

4 Sequencing Cont. q If tokens moved through pipeline at constant speed, no sequencing elements would be necessary q Example: fiber-optic cable Light pulses (tokens) are sent down cable Next pulse sent before first reaches end of cable No need for hardware to separate pulses But dispersion sets minimum time between pulses q This is called wave pipelining in circuits q In most circuits, dispersion is high elay fast tokens so they don t catch slow ones 4

5 Sequencing Overhead q Use flip-flops to delay fast tokens so they move through exactly one stage each cycle q Inevitably adds some delay q Makes circuit slower than just the logic delay Called sequencing overhead q Some people call this clocking overhead But it applies to asynchronous circuits too Inevitable side effect of maintaining sequence 5

6 Sequencing Elements q q q Latch: Level sensitive a.k.a. transparent latch, latch Flip-flop: edge triggered a.k.a. master-slave flip-flop, flip-flop, register Timing iagrams Transparent Opaque Edge-trigger Latch Flop (latch) (flop) 6

7 Latch esign q Pass Transistor Latch q Pros + Tiny + Low clock load q Cons V t drop nonrestoring backdriving output noise sensitivity dynamic diffusion input Used in 1970 s 7

8 Latch esign q Transmission gate + No V t drop - Requires inverted clock 8

9 Latch esign q Inverting buffer + Restoring + No backdriving + Fixes either X Output noise sensitivity Or diffusion input Inverted output 9

10 Latch esign q Tristate feedback + Static Backdriving risk X q Static latches are now essential because of leakage 10

11 Latch esign q Buffered input + Fixes diffusion input + Noninverting X 11

12 Latch esign q Buffered output + No backdriving X q Widely used in standard cells + Very robust (most important) - Rather large - Rather slow (1.5 2 FO4 delays) - High clock loading 12

13 Latch esign q atapath latch + smaller + faster - unbuffered input X 13

14 Flip-Flop esign q Flip-flop is built as pair of back-to-back latches X X 14

15 Enable (Clock Gating) q Enable: ignore clock when en = 0 Mux: increase latch - delay Clock Gating: increase enable setup time, skew Symbol Multiplexer esign Clock Gating esign en Latch 1 0 Latch Latch en en en Flop 1 0 en Flop Flop en 15

16 Reset q Force output low when reset asserted q Synchronous vs. asynchronous Symbol Latch Flop reset reset Synchronous Reset Asynchronous Reset reset reset reset reset reset reset 16

17 Set / Reset q Set forces output high when enabled q Flip-flop with asynchronous set and reset reset set reset set 17

18 Sequencing Methods q Flip-flops q 2-Phase Latches q Pulsed Latches Flip-Flops Flop T c Combinational Logic Flop 2-Phase Transparent Latches Pulsed Latches 1 2 p Latch t pw p Latch T c /2 Combinational Logic t nonoverlap Latch Combinational Logic Combinational Logic Half-Cycle 1 Half-Cycle 1 t nonoverlap Latch p Latch 18

19 Timing iagrams Contamination and Propagation elays t pd Logic Prop. elay A Combinational Logic Y A Y t cd t pd t cd t pcq t ccq Logic Cont. elay Latch/Flop Clk-> Prop. elay Latch/Flop Clk-> Cont. elay Flop t setup t hold t pcq t pdq Latch -> Prop. elay t ccq t cdq t setup t hold Latch -> Cont. elay Latch/Flop Setup Time Latch/Flop Hold Time Latch t setup t hold t t ccq pcq t cdq t pdq 19

20 Max-elay: Flip-Flops ( setup ) tpd Tc t + tpcq sequencing overhead F1 1 Combinational Logic 2 F2 T c t pcq t setup 1 t pd 2 20

21 Max elay: 2-Phase Latches ( 2 ) tpd = tpd1+ tpd 2 Tc tpdq 123 sequencing overhead Combinational 2 2 Combinational 3 Logic 1 Logic 2 L1 L2 L T c 1 t pdq1 1 t pd1 2 t pdq2 2 t pd2 3 21

22 Max elay: Pulsed Latches ( setup ) tpd Tc max tpdq, tpcq + t tpw sequencing overhead 1 p L1 1 Combinational Logic 2 p L2 2 T c 1 t pdq (a) t pw > t setup 1 t pd 2 p (b) t pw < t setup 1 2 t pcq T c t pw tpd tsetup 22

23 Min-elay: Flip-Flops 1 t t t CL cd hold ccq F1 2 F2 1 t ccq t cd 2 t hold 23

24 Min-elay: 2-Phase Latches t t t t t cd1, cd 2 hold ccq nonoverlap 1 L1 1 CL Hold time reduced by nonoverlap 2 2 L2 Paradox: hold applies twice each cycle, vs. only once for flops. 1 2 t nonoverlap 1 t ccq t cd But a flop is made of two latches! 2 t hold 24

25 Min-elay: Pulsed Latches tcd thold tccq + t 1 pw CL p L1 Hold time increased by pulse width 2 p L2 p t pw t hold 1 t ccq t cd 2 25

26 Time Borrowing q In a flop-based system: ata launches on one rising edge Must meet setup time before next rising edge If it arrives late, system fails If it arrives early, time is wasted Flops have hard edges q In a latch-based system ata can pass through latch while transparent Long cycle of logic can borrow time into next cycle As long as each loop completes in one cycle 26

27 Time Borrowing Example (a) Latch Combinational Logic Latch Combinational Logic Latch Borrowing time across half-cycle boundary Borrowing time across pipeline stage boundary 1 2 (b) Latch Combinational Logic Latch Combinational Logic Loops may borrow time internally but must complete within the cycle 27

28 How Much Borrowing? 2-Phase Latches T borrow c setup + nonoverlap ( ) t t t L1 1 2 Combinational Logic 1 L2 2 1 Pulsed Latches 2 T c t nonoverlap t t t borrow pw setup T c /2 Nominal Half-Cycle 1 elay t borrow t setup 2 28

29 Clock Skew q We have assumed zero clock skew q Clocks really have uncertainty in arrival time ecreases maximum propagation delay Increases minimum contamination delay ecreases time borrowing 29

30 Skew: Flip-Flops ( setup skew ) tpd Tc tpcq + t + t t t t + t cd hold sequencing overhead ccq skew 1 F1 1 t pcq Combinational Logic T c t pdq 2 t setup F2 t skew 2 F1 1 CL 2 F2 t skew t hold 1 t ccq 2 t cd 30

31 Skew: Latches 2-Phase Latches ( 2 ) tpd Tc tpdq 123 sequencing overhead Combinational 2 2 Combinational 3 Logic 1 Logic 2 L1 L2 L3 3 t, t t t t + t cd1 cd 2 hold ccq nonoverlap skew 2 T t t + t + t 2 ( ) c borrow setup nonoverlap skew Pulsed Latches cd hold pw ccq ( setup skew ) tpd Tc max tpdq, tpcq + t tpw + t t t + t t + t ( ) t t t + t sequencing overhead skew borrow pw setup skew 31

32 Two-Phase Clocking q If setup times are violated, reduce clock speed q If hold times are violated, chip fails at any speed q In this class, working chips are most important No tools to analyze clock skew q An easy way to guarantee hold times is to use 2- phase latches with big nonoverlap times q Call these clocks 1, 2 (ph1, ph2) 32

33 Safe Flip-Flop q Past years used flip-flop with nonoverlapping clocks Slow nonoverlap adds to setup time But no hold times q In industry, use a better timing analyzer Add buffers to slow signals if hold time is at risk 2 1 X

34 Adaptive Sequencing q esigners include timing margin Voltage Temperature Process variation ata dependency Tool inaccuracies ERR q Alternative: run faster and check for near failures Idea introduced as Razor Increase frequency until at the verge of error Can reduce cycle time by ~30% f p X f p X ERR 34

35 Summary q Flip-Flops: Very easy to use, supported by all tools Robust, at the expense of lost time q 2-Phase Transparent Latches: Lots of skew tolerance and time borrowing q Pulsed Latches: Fast, some skew tolerance and time borrowing, hold time risk q Maybe give asynchronous design a serious look 35

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