Y. Tsiatouhas. VLSI Systems and Computer Architecture Lab. Boundary Scan (JTAG ) 2

Transcription

1 CMOS INTEGRATE CIRCUIT EGN TECHNIUES University of Ioannina Boundary Scan Testing (JTAG ΙΕΕΕ 49 std) ept of Computer Science and Engineering Y Tsiatouhas CMOS Integrated Circuit esign Techniques VL Systems and Computer Architecture Lab Overview Basic JTAG architecture 2 The Test Access Port (TAP) 3 JTAG registers 4 State diagram Operating modes 5 Instruction set 6 External and internal testing operations Boundary Scan (JTAG 49) 2

2 Typical PCB Testing Probe Under Test Probe PCB Under Test rivers True Response Expected Response Tester Test Patterns Boundary Scan (JTAG 49) 3 Basic JTAG Architecture (Ι) (IEEE 49 std) Boundary Register The JTAG 49 Boundary Scan std supports PCB testing procedures according to a commonly acceptable (standard) test mechanism User or I Register Bypass Register Instruction Register Test Access Port TI Controller TCK TMS TAP Controller TO TRST It consists of: A Test Access Port TAP with 4 or 5 pins A set of registers (an instruction register (IR), a bypass register (BR) and dataregisters () ATAP Controller which is a finite state machine (FSM) with 6 states Boundary Scan (JTAG 49) 4 2

3 Basic JTAG Architecture (ΙI) In the normal mode of operation the JTAG circuitry is transparent to the chip under test and the PCB system where this chip is embedded TI TCK TMS TAP Controller TO TRST Two test modes of operation exist: Internal Testing where the internal logic of the chip is tested External Testing where the interconnections among the chips are tested Boundary Scan (JTAG 49) 5 Test Access Port TAP (I) PCB TO TRST TO TRST TI TCK TMS TO TRST TI TCK TMS TO TRST TAP TO TCK TRST TMS TI TI TCK TMS TI TCK TMS Boundary Scan (JTAG 49) 6 3

4 Test Access Port TAP (II) TCK (Test Clock): This is the test clock signal, which synchronizes the test procedure independently of the system clock Under the control of this signal test data are shifted between the TAP registers TI (Test ata Input): Serial test data input New data are scanned in at each positive edge of the TCK clock signal When not in use must remain at logic High TO (Test ata ): Serial test data output ata are scanned outatthe negative edge of the TCK clock signal TMS (Test Select): The sequence of values at this input is translated by the TAP Controller and is used to control the test procedure When not in use must remain at logic High TRST (Test Reset): This is an optional signal, which is used for the asynchronous initialization of the test logic independently of the clock signal TCK Boundary Scan (JTAG 49) 7 Registers PI TI TCK TMS TRST BSR Shift_ Clock Run_Test TAP Controller Scan Register ecoders User Registers ev I Register Bypass ecode IR Register Shift_IR Clock_IR _IR Reset BSR MUX Select MUX 2 FF TCK Shift TO The JTAG protocol provides the ability to support a large number of user dfi definedd registers it However,thepresenceof three registers is mandatory : Bypass Register (BR) (Καταχωρητής Παράκαμψης) Instruction Register (IR) (Καταχωρητής Εντολών) Boundary Scan Register (BSR) (Καταχωρητής Περιφερειακής Σάρωσης) Boundary Scan (JTAG 49) 8 4

5 ata Instruction Register IR (Καταχωρητής Εντολών) The Instruction Register IR (Καταχωρητής Εντολών) is a serial / parallel input and output register Each stage of the register consists of a pair of a flip flop and a latch The flip flop feeds the corresponding latch The latch holds the current instruction when the IR is updated with new data (instructions) The size of the register is at least two bits TI or Previous Cell IR Cell ShiftIR MUX ClockIR (CaptureIR) Shift Reg FF TO or Next Cell Latch FF CLR IR CLR Parallel TI n Parallel s Latch Flip Flops n n Shift Reg Flip Flops ata TO Boundary Scan (JTAG 49) 9 IR Boundary Scan Register BSR (Καταχωρητής Περιφερειακής Σάρωσης) The Boundary Scan Register BSR (Καταχωρητής Περιφερειακής Σάρωσης) is placed at the chip periphery, in between the input/output pads and the internal logic It consists of the Boundary Scan Cells (Κύτταρα Περιφερειακής Σάρωσης) and supports both the testing of the internal logic of the chip as well as the interconnects of the chip with other chips ata Input Pin Internal MUX Shift Reg FF To next or TO ShiftOut Latch FF MUX Internal Pin UP CLR CLR From previous (Capture) or TI ShiftIn Shift Clock (Test/Normal) Boundary Scan (JTAG 49) 5

6 Bypass Register BR The Bypass Register BR (Καταχωρητής Παράκαμψης) is an one bit register consisting of a single Flip Flop* It permits the signal at the TI input to bypass the BSR register and directly feed the TO output TI Capture AN Flip FlopFlop TO BR To TO output through MUX and MUX 2 BR CLR Clock (Capture) * In practice the BR is implemented as a single boundary scan cell! Boundary Scan (JTAG 49) TAP Controller State iagram The ΤΑΡ controller is a Finite State Machine (FSM) with 6 states The state transition takes place at the positive edge of the TCK clock signal At the state diagram beside, the arrows between the states are marked with or, which correspond to the logic level that the TMS signal must have before the positive ii edge of the clock signal TCK in order to activate the corresponding state transition Boundary Scan (JTAG 49) 2 6

7 s of Operation Two basic modes of operation exist for the JTAG 49 std and each mode supports specific instructions: Non Invasive (Απρόσκοπτος Τρόπος): The ΤΑΡ controller and the pertinent port operate asynchronously and independently with respect to the system under test In this mode, the ΤΑΡ port can be exploited without disturbing the operation of the system Pin Permission (Τρόπος Επίτρεψης Ακροδέκτη): In this mode, the internal logic of the circuit under test is disconnected from the input/output pins Consequently, only testing operations can be performed Boundary Scan (JTAG 49) 3 Instruction Set Ι (Non Invasive) BYPASS: This instruction places the bit bypass register between the TI and TO pins The BYPASS instruction is mandatory for the protocol The all ones state in the instruction register must correspondtothis instruction ICOE: This instruction places a 32 bit register between the TI and TO pins The register is loaded in parallel by the hardware with the code I of the chip USERCOE: Once again, this instruction places the previous 32 bit register between the TI and TO pins This time the register is not loaded with the code I of the chip but with auserdefined dfi dcode This instruction ti is related ltdto programmable devices (like FPGAs) Boundary Scan (JTAG 49) 4 7

8 Instruction Set ΙI (Non Invasive) SAMPLE/PRELOA instruction: This instruction places the boundary scan register (BSR) between the TI and TO pins This instruction is mandatory for the protocol The Sample/Preload instruction does not disturb the normal mode of operation since the signal of the second multiplexer in the boundary scan cells is at logic (normal mode) The instruction activates two operations: The SAMPLE operation is accomplished at the TURE state of the TAP controller where the Flip Flopscapture the data at their inputs Thus, the BSR register holds a snapshot of the activity at the chip s I/Os Then, the sampled data can be scanned out for observation The PRELOA operation is accomplished during the scan out activity, where in parallel new data are scanned in Thus, the data at the ShiftIn () inputs are captured by the Flip Flops and subsequently feed the UP Flip Flops when the TAP controller is at the UPATE state Boundary Scan (JTAG 49) 5 PI Input Instruction Set ΙII (Non Invasive) SAMPLE phase Capture UP UP Shift Clock Shift Clock Boundary Scan (JTAG 49) 6 8

9 PI Input Instruction Set ΙV (Non Invasive) PRELOA SHIFT phase Shift UP UP Shift Clock Shift Clock Boundary Scan (JTAG 49) 7 PI Input Instruction Set V (Non Invasive) End of PRELOA Secure/on t Care Values UP UP Shift Clock Shift Clock Boundary Scan (JTAG 49) 8 9

10 Instruction Set VΙ (Pin Permission) Permission) The EXTEST instruction: This instruction places the boundary scan register between the TI and TO pins The instruction is mandatory and the all zero state at the instruction register must correspond to it At the TURE state, the logic values at the input pads of the chip are captured in the Flip Flops of the cells In addition, the output pads are driven by the UP Flip Flops since the signal is With this instruction the input pads are sampled and the output pads are driven Consequently, at the shift operations on the BSR register, the state of the input pads is read while new values are set at the output pads of the chip Boundary Scan (JTAG 49) 9 PI Input Instruction Set VIΙ Secure/on t Care Values (Pin Permission) Permission) st Test Application phase of EXTEST UP UP Shift Clock Shift Clock Boundary Scan (JTAG 49) 2

11 PI Input Instruction Set VΙII (Pin Permission) Permission) 2 nd Test Response Capture phase of EXTEST Capture on t Care Values UP UP Shift Clock Shift Clock Boundary Scan (JTAG 49) 2 PI Input Instruction Set ΙX (Pin Permission) Permission) 3 rd Test ata Shift phase of EXTEST Shift UP UP Shift Clock Shift Clock Boundary Scan (JTAG 49) 22

12 PI Input Instruction Set X (Non Invasive) End of EXTEST Secure/on t Care Values BSR with Test ata UP UP Shift Clock Shift Clock Boundary Scan (JTAG 49) 23 Instruction Set XI (Pin Permission) Permission) The RUNBIST instruction: This instruction activates a user defined register which may be one of the existing registers in the protocol The target is to permit the use of embedded BIST techniques The BIST procedures start when the ΤΑΡ controller is at the RUN TEST ILE state The INTEST instruction: This instruction places the boundary scan register between the TI and TO pins It sets the inputs of the internal logic under the control of the corresponding UP Flip Flops of the BSR In addition, the BSR cells at the outputs of the internal logic sample the corresponding responses at the TURE state Consequently, at the UPATE state a test pattern is applied while at the TURE state the response of the logic to this pattern is sampled Next, the response is scanned out and concurrently a new test pattern is scanned in Boundary Scan (JTAG 49) 24 2

13 PI Input Instruction Set XΙI (Pin Permission) Permission) Test Application st phase of INTEST Secure/on t Care Values UP UP Shift Clock Shift Clock Boundary Scan (JTAG 49) 25 PI Input Instruction Set XIΙI on t Care Values (Pin Permission) Permission) Test Response Capture 2 nd phase of INTEST UP UP Shift Clock Shift Clock Boundary Scan (JTAG 49) 26 3

14 PI Input Instruction Set XIV (Pin Permission) Permission) 3 rd Test ata Shift phase of INTEST Shift UP UP Shift Clock Shift Clock Boundary Scan (JTAG 49) 27 PI Instruction Set XV (Non Invasive) BSR with Test ata End of INTEST Input Secure/on t Care Values UP UP Shift Clock Shift Clock Boundary Scan (JTAG 49) 28 4

15 Instruction Set XVI (Pin Permission) Permission) The HIGHZ instruction: This instruction places the bypass register between the TI and TO pins In addition, sets the output pads in the high Z condition o at the UPATE IR state It is exploited epotedfor the testing of chips that are not compliant with the JTAG protocol The CLΑMP instruction: This instruction places the bypass register between the TI and TO pins In addition, sets the output pads under the control of the BSR register, which has been earlier fed with proper values by exploiting a sequence of SAMPLE/PRELOA instructions Consequently, the output pads of the chip retain specific values during the testing procedures that are applied to other chips where these outputsdo notparticipate ii Boundary Scan (JTAG 49) 29 Instruction Register Ι Initialization at the TEST LOGIC RESET state by exploiting the TRST signal Proper use of the TMS and TCK signals in order to activate the TURE IR state and subsequently the SHIFT IR state At the TURE IR state the IR register is placed between the TI and TO pins At the SHIFT IR state the TO pin is activated Boundary Scan (JTAG 49) 3 5

16 Instruction Register ΙI Boundary Scan (JTAG 49) 3 Instruction Register ΙII PCB TO TRST TO TRST ΙR ΙR TI TCK TMS TO TRST ΙR TI TCK TMS TO TRST ΙR TAP TO TCK TRST TMS TI TI TCK TMS TI TCK TMS Boundary Scan (JTAG 49) 32 6

17 ata Register Activation The update of the IR register, at the UPATE IR state, will result to the connection of the proper data register between the TI and TO pins when the ΤΑΡ controller will be at the TURE state Boundary Scan (JTAG 49) 33 ata Register I At SHIFT state the TO is activated and new test data are scanned in/out to the selected register Boundary Scan (JTAG 49) 34 7

18 ata Register II Boundary Scan (JTAG 49) 35 PCB ata Register III (& Bypass Operation) TO TRST TO TRST BR BSR CUT TI TCK TMS TO TRST BR TI TCK TMS TO TRST BR TAP TO TCK TRST TMS TI TI TCK TMS TI TCK TMS Boundary Scan (JTAG 49) 36 8

19 ata Register Activation At the UPATE state the data register is updated Possibly another data shift phase will be initiated next Boundary Scan (JTAG 49) 37 Basic Testing Procedure Ι (External or Internal Testing) TEST LOGIG RESET 2 Load IR with the instruction SAMPLE/PRELOA Invasive The selected is placed between TI TO 3 4 Shift data to the selected (eg BSR) LoadIRwith the instruction EXTEST ή INTEST PRELOA phase Pin Permission The selected is placed between TI TO Test data application 5 Test response Capture Boundary Scan (JTAG 49) 38 9

20 Basic Testing Procedure ΙI (External or Internal Testing) 6 Scan out the test response Scan in new test data 7 New Test data application 8 YES More test data? 5 NO 9 Test response capture Boundary Scan (JTAG 49) 39 Basic Testing Procedure ΙII (External or Internal Testing) Scan out the test response Scan in secure data Secure data application 2 TEST LOGIG RESET Boundary Scan (JTAG 49) 4 2

21 IEEE P687 Internal JTAG (IJTAG) IEEE P687 std Also referred to as IJTAG (Internal JTAG), the IEEE P687 working group intends to develop a methodology for access to embedded test and debug features (but not the features themselves) via the IEEE 49 Test Access Port (TAP) and additional signals that may be required The IEEE 49 standard specifies circuits to be embedded within a Integrated Circuit to support board test, namely the Test Access Port (TAP), TAP Controller, and a number of internal registers In practice, the TAP and TAP controller are being used for other functions well beyond boundary scan in an ad hoc manner across the industry to access a wide variety of internal chip test and debug features The purpose of the IJTAG initiative is to provide an extension to the IEEE 49 standard specifically aimed at using the TAP to manage the configuration, operation and collection of data from embedded test and debug circuitry There exists the widespread use of embedded instrumentation (such as BIST Engines, Complex I/O Characterization and Calibration, Embedded Timing Instrumentation, etc) each of which is accessed and managed by a variety of external instrumentation using a variety of mechanisms and protocols Therefore, there exists a need for a standardization of these protocols in order to ensure an efficient and orderly methodology for the preparation of tests and the access and control of these embedded instruments The elements of the methodology include a description language for the characteristics of the features and for communication with the features, and requirements for interfacing to the features Source: ΙΕΕΕ Boundary Scan (JTAG 49) 4 References The Boundary Scan Handbook, K Parker, Kluwer Academic Publishers, 992 Principles of Testing Electronics Systems, S Mourad and Y Zorian, John Wiley & Sons, 2 Essentials of Electronic Testing: for igital, Memory and Mixed Signal VL Circuits, M Bushnell and V Agrawal, Kluwer Academic Publishers, 2 System on Test Architectures, L T Wang, C Stroud and N Touba, Morgan Kaufmann, 28 Boundary Scan (JTAG 49) 42 2