Exercise 2: D-Type Flip-Flop
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1 Flip-Flops Digital Logic Fundamentals Exercise 2: D-Type Flip-Flop EXERCISE OBJECTIVE When you have completed this exercise, you will be able to determine the characteristics of a D-type results with an oscilloscope. EXERCISE DISCUSSION There is one data input (D) and a clock input (CLK). The two outputs, Q and Q, are complementary. T a. b. 162 FACET by Lab-Volt
2 Digital Logic Fundamentals Flip-Flops A low (logic 0) at PR sets Q high (logic 1). A low at CLR resets Q low. respectively; data or clock signals have no effect on Q and Q. A low (logic 0) at PR sets Q a. high (logic 1). b. low (logic 0). The small circle and triangle at the CLK input indicate that the negative edge of the clock signal activates the data (D) input. FACET by Lab-Volt 163
3 Flip-Flops Digital Logic Fundamentals a. high to low. b. low to high. This is a timing diagram showing the relationship between the data input (D), the outputs (Q and Q), and the clock signal (CLK). Q equals the D input after the negative edge of the CLK. Q is the complement of D and Q. Q until there is another negative edge of the CLK signal. The Q output is logic 1. If input D is logic 0 during the next negative edge of the clock signal, the Q output a. stays logic 1. b. changes to logic FACET by Lab-Volt
4 Digital Logic Fundamentals Flip-Flops Q is logic 1. The logic states of D and CLK do not affect the outputs. If PR is logic 0, CLR is logic 1, and D is logic 0, what logic state will Q be after the next negative edge of the CLK? a. logic 0 b. logic 1 FACET by Lab-Volt 165
5 Flip-Flops Digital Logic Fundamentals If PR is logic 1, CLR is logic 1, and D is logic 0, what logic state will Q be after the next negative edge of the CLK? a. logic 0 b. logic 1 If PR is logic 1, CLR is logic 1, and D is logic 1, what logic state will Q be when the CLK changes from logic 0 to logic 1? a. Q will remain in its existing state. b. logic 1 PROCEDURE Locate the INPUT SIGNALS, SET/RESET FLIP-FLOP, and D-TYPE FLIP-FLOP circuit blocks. 166 FACET by Lab-Volt
6 Digital Logic Fundamentals Flip-Flops Connect A at the INPUT SIGNALS circuit block to A (D input) on the D-TYPE FLIP-FLOP circuit block. Connect the Q output of the SET/RESET FLIP-FLOP circuit block to B (CLK input) on the D-TYPE FLIP-FLOP circuit block. Set toggle switch A in the HIGH position to put a logic high (1) at the D input. Place a two-post connector in the S (SET) position on the SET/RESET FLIP-FLOP circuit block. This puts a high (1) clock signal to CLK. Connect the oscilloscope channel 1 probe to the Q output, and connect the channel 2 probe to the Q Connect the probe ground clips to a ground terminal on the circuit board. FACET by Lab-Volt 167
7 Flip-Flops Digital Logic Fundamentals This puts a logic 0 (low) at PR. Observe the logic states of Q (channel 1) and Q (channel 2) on the oscilloscope screen to answer the following questions. Preset Output Logic States The Q output is a. logic 1. b. logic 0. The Q output is a. logic 1. b. logic 0. Are the Q and Q outputs complementary? Remove the two-post connector at PRESET. Did the Q and Q outputs remain logic 1 and logic 0, respectively? 168 FACET by Lab-Volt
8 Digital Logic Fundamentals Flip-Flops This puts a logic 0 (low) at CLEAR. Clear Output Logic States The Q output is a. logic 1. b. logic 0. The Q output is a. logic 1. b. logic 0. Are the Q and Q outputs complementary? Remove the two-post connector at CLEAR. Did the Q and Q outputs remain logic 0 and logic 1, respectively? FACET by Lab-Volt 169
9 Flip-Flops Digital Logic Fundamentals to logic 1 by moving toggle switch A from HIGH to LOW and back to HIGH on the INPUT SIGNALS circuit block. Did the Q and Q output states change when the data input logic state was changed? Q and Q did not change because the Q and Q outputs respond to the data signal a. when the clock signal is logic 0. b. only on the negative edge (from high to low) of the clock signal. 170 FACET by Lab-Volt
10 Digital Logic Fundamentals Flip-Flops The data signal should be logic 1 (toggle switch A set to HIGH). While observing the Q and Q outputs on the oscilloscope screen, change the clock signal from logic 1 to 0 by setting the two-post connector from S to R on the SET/RESET FLIP-FLOP circuit block. The Q output a. changed to logic 1. b. stayed at logic 0. The Q output is a. logic 1. b. logic 0. Why did Q go to logic 1 and Q to logic 0? a. Because the data input (D) was logic 1 during the negative edge of the clock signal b. Because the Q and Q outputs change on a negative clock signal FACET by Lab-Volt 171
11 Flip-Flops Digital Logic Fundamentals While observing the Q and Q outputs on the oscilloscope screen, set the data signal to logic 0 by placing toggle switch A to LOW on the INPUT SIGNALS circuit block. Did the Q and Q output states change when the data input logic state was changed to logic 0? What will make the Q and Q output states respond to a data input change from logic 1 to 0? a. a logic 0 signal at PRESET b. a negative edge of a clock signal 172 FACET by Lab-Volt
12 Digital Logic Fundamentals Flip-Flops While observing the Q and Q outputs on the oscilloscope screen, create a negative edge of a clock signal by placing the two-post connector to the S position and then back to the R on the SET/RESET FLIP-FLOP circuit block. negative edge of the clock signal? The Q output is a. logic 1. b. logic 0. The Q output is a. logic 1. b. logic 0. FACET by Lab-Volt 173
13 Flip-Flops Digital Logic Fundamentals While observing the Q and Q outputs on the oscilloscope screen, set the two-post connector from R to S to R on the SET/RESET FLIP-FLOP circuit block. This cycles the clock signal from low to high to low, causing a negative edge. low? The outputs did not change because a. the data signal remained at logic 0 during the negative edge of the clock signal. b. Modify your test circuit by connecting the CLK (clock) input of the D-TYPE FLIP-FLOP circuit block to the CLOCK circuit block. The CLK input is receiving a 50 khz clock signal with a peak-to-peak amplitude of about 5 V. This means that there is a negative edge of the clock signal 50,000 times per second. 174 FACET by Lab-Volt
14 Digital Logic Fundamentals Flip-Flops Do the Q and Q outputs change when the D input remains at logic 0? While observing the Q and Q outputs on the oscilloscope screen, change the D input to logic 1 and back to logic 0 several times by changing the position of toggle switch A from LOW to HIGH and back to LOW several times. continuous 50 khz clock signal? a. Q b. Q FACET by Lab-Volt 175
15 Flip-Flops Digital Logic Fundamentals While observing the Q and Q outputs on the oscilloscope screen, reset the CLR input to logic 0 by putting the two-post connector in the terminals at CLEAR. Move toggle switch A to HIGH and back to LOW several times to change the logic state of D. While observing the Q and Q outputs of the oscilloscope screen, set the PR input by putting the two-post connector in the terminals at PRESET. 176 FACET by Lab-Volt
16 Digital Logic Fundamentals Flip-Flops Move the toggle switch A to HIGH and back to LOW several times to change the logic state of D. Based on your observation, does a logic 0 at the PR or CLR inputs initialize the logic state of the outputs? FACET by Lab-Volt 177
17 Flip-Flops Digital Logic Fundamentals CONCLUSION A PR (preset) input sets the Q output to a logic 1 state. A CLR (clear) input resets the Q output to a logic 0 state. The two outputs, Q and Q, are complementary. When PR and CLR are logic 1, Q equals the D input after the negative edge of the CLK signal. RESET state, respectively. REVIEW QUESTIONS 1. a. immediately passes all input data (D) state changes to its output. b. does not react to input data (D) state changes until clocked. c. must be triggered with a negative clock edge to accept PR or CLR inputs. d. changes its output state at every negative clock edge. 2. A logic 0 at the PR (PRESET) input sets the Q output to logic a. 1. b. 0. c. 0 on a positive clock edge. d. 1 on a negative clock edge. 178 FACET by Lab-Volt
18 Digital Logic Fundamentals Flip-Flops 3. A logic 0 at the CLR (CLEAR) input resets the Q output to logic a. 1. b. 0. c. 0 on a positive clock edge. d. 1 on a negative clock edge. 4. a. Q output follows the logic state of the D input. b. Q output follows the logic state of the CLK signal. c. outputs are both logic 0. d. outputs are locked in either the set or reset state, respectively. 5. a. the output follows all input data (D) state changes. b. PR and CLR inputs are locked out. c. the Q and Q outputs are no longer complements. d. FACET by Lab-Volt 179
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