Chapter 8 Functions of Combinational Logic

Size: px
Start display at page:

Download "Chapter 8 Functions of Combinational Logic"

Transcription

1 ETEC 23 Programmable Logic Devices Chapter 8 Functions of Combinational Logic Shawnee State University Department of Industrial and Engineering Technologies Copyright 27 by Janna B. Gallaher

2 Basic Adders Adders are included in all microprocessors and re needed in many other types of digital systems The Half-Adder Accepts two binary digits on its inputs and produces two binary digits on its outputs, a sum bit and a carry bit. A B Cout

3 Basic Adders Full-Adder Accepts two input bits and an input carry and generates a sum output and an output carry. A B Cin Cout

4 Basic Adders Full-Adders (continued) We can also implement Full-Adders using Half-Adder blocks

5 Parallel Binary Adders Two or more full-adders are connected to form parallel binary adders Note how the Carry Out bit from the Least Significant Bit is propagated to the next Most Significant Bit.

6 Parallel Binary Adders Four-Bit Parallel Adder Four bits are called a nibble. C = carry in to least significant bit C4 = output carry of the most significant bit - 4 = the sum outputs Truth Table for Each Stage

7 Parallel Binary Adders 74LS283 4-Bit Parallel Adder Commercially available IC implements a 4-Bit parallel adder.

8 Parallel Binary Adders Adder Expansion Cascading 4-bit adders provides for 8-bit or 6-bit or more complex adders. To make it work, connect the Cout from the less significant bit to the more significant bit and connect C to ground.

9 Ripple Carry Versus Look-Ahead Carry Adders The Ripple Carry Adder Full-adders are cascaded => propagation times also cascade Simple, but can be problematic from a propagation delay perspective Note that even though each adder has 8 ns delay, the full delay is 32 ns.

10 Ripple Carry Versus Look-Ahead Carry Adders The Look-Ahead Carry Adder Attempts to fix the propagation delay time problem of ripple carry adders by incorporating some carry look-ahead logic Carrys happen when: A OR B is with a Carry In A AND B is with no Carry In A AND B is with a Carry In

11 Comparators Comparators are used to compare two binary quantities to determine the relationship of those quantities. Equality EXOR gates form a simple -bit comparator Multi-bit comparators can be built using the outputs of EXNOR gates ANDED together

12 Comparators Inequality This IC compares two nibbles (4-bit numbers) and determines if they are equal, if A>B, or if A < B. Inequality is can be determined by ORing the A>B and the A<B outputs together. The 74HC85 4-Bit Magnitude Comparator

13 Decoders The Basic Binary Decoder Decoders are used for a variety of applications such as data line selectors, in A/D converter systems, etc. They can be made to generate a specific output code on a specific combination of input bits. This example shows that a specific combination or 4-data inputs can be decoded to give an output when the inputs are. Other circuits can be made to decode other combinations.

14 Decoders The 4-Bit Decoder Commercial ICs are made that decode 4-bits to a -of-6 output. Binary Inputs 74HC54 -of-6 Decoder Outputs A3 A2 A A

15 Decoders An Application Port Address Decoder Selects output port so that the data bus can be shared Provides expansion of expensive resources

16 Decoders The BCD-to-Decimal Decoder Converts binary numbers to decimal numbers 4-line-to--line decoder or -of- decoder Note that only one output line goes low on one of the combinations of the 4 input bits. Numbers through 5 are not allowed. (binary through )

17 Decoders The BCD-to-7-Segment Decoder There are a significant number of instruments and devices that rely on 7segment displays. For these a specific decoder has been devised. 74LS47 BCD-To-7-Segment Decoder/Driver Note that this IC also has driver electronics so that it can directly illuminate the segments.

18 Encoders The Decimal-to-BCD Encoder Essentially the reverse of a decoder they take a -of-many inputs and turn them into a binary number output. They are especially useful in applications such as keyboards, keypads, and other input devices. 74HC47 Decimal-To-BCD Encoder 74LS48 8-Line-To-3-Line Encoder

19 Encoders An Application Simplified Keyboard Encoder This scheme can be used in security system number pads, keyboards, or input devices to control systems. The use of dedicated hardware speeds up the system and unloads the microprocessor. But it does add cost and complexity to the system.

20 Code Converters Dedicated ICs to convert one type of code to another (e.g. BCD to Binary) BCD-to-Binary Conversion Binary-to-Gray and Gray-to-Binary Conversion Gray codes are used in communications, Karnaugh maps, angle measuring devices, etc. 4-Bit Gray-To-Binary Conversion Logic

21 Multiplexers (Data Selectors) Multiplexers are used to share some resource (data line, bus, etc.) There are several data lines input to the device but only one of them routed to the output at a time. Sometimes these devices are called Data Selectors Typical MUX IC Equivalent Logic Diagram for MUX

22 Multiplexers (Data Selectors) Two commercial Multiplexers: 74HC57 Quad 2-Input-Data Selector/Multiplexer 74LS5 8-Input Data Selector/ Multiplexer

23 Multiplexers (Data Selectors) Application 7-Segment Display Multiplexer Note that only one Decoder/driver is needed to create a 2-digit display. The multiplexer enables each of the 7-segment displays in alternately while the decoder applies the appropriate signal. The displays appear to be on constantly since the speed is faster than the persistence of vision.

24 Demultiplexers Essentially the opposite function of Multiplexers Takes one input and distributes it to -of-n data output lines. Typical Demultiplexing Logic 74HC54 Demultiplexer

25 Parity Generators/Checkers Parity generators are used to insure that data transmission are intact Parity can be either even or odd or none It is an extra bit added on to the data that is either set or unset to generate the parity Even parity => the total number of s in the code is an even number Odd parity => the total number of s in the code is an odd number Basic Parity Logic The sum (disregarding carries) of an even number of s is always, and the sum of an odd number of s is always. x = (Low) when the number of s on the inputs are even x = (High) when the number of s on the inputs is odd.

26 Parity Generators/Checkers 74LS28 9-Bit Parity Generator/Checker

27 Using 74XX Functions is Programmable Logic Quartus II 74XX Devices Xilinx ISE 74XX Devises Standard 74XX Quartus Devices Standard 74XX Xilinx Devices

Half-Adders. Ch.5 Summary. Chapter 5. Thomas L. Floyd

Half-Adders. Ch.5 Summary. Chapter 5. Thomas L. Floyd Digital Fundamentals: A Systems Approach Functions of Combinational Logic Chapter 5 Half-Adders Basic rules of binary addition are performed by a half adder, which accepts two binary inputs (A and B) and

More information

FUNCTIONS OF COMBINATIONAL LOGIC

FUNCTIONS OF COMBINATIONAL LOGIC FUNCTIONS OF COMBINATIONAL LOGIC Agenda Adders Comparators Decoders Encoders Multiplexers Demultiplexers Adders Basic Adders Adders are important in computers other types of digital systems in which numerical

More information

Combinational Logic Design

Combinational Logic Design Lab #2 Combinational Logic Design Objective: To introduce the design of some fundamental combinational logic building blocks. Preparation: Read the following experiment and complete the circuits where

More information

Chapter 9 MSI Logic Circuits

Chapter 9 MSI Logic Circuits Chapter 9 MSI Logic Circuits Chapter 9 Objectives Selected areas covered in this chapter: Analyzing/using decoders & encoders in circuits. Advantages and disadvantages of LEDs and LCDs. Observation/analysis

More information

MUHAMMAD NAEEM LATIF MCS 3 RD SEMESTER KHANEWAL

MUHAMMAD NAEEM LATIF MCS 3 RD SEMESTER KHANEWAL 1. A stage in a shift register consists of (a) a latch (b) a flip-flop (c) a byte of storage (d) from bits of storage 2. To serially shift a byte of data into a shift register, there must be (a) one click

More information

Analogue Versus Digital [5 M]

Analogue Versus Digital [5 M] Q.1 a. Analogue Versus Digital [5 M] There are two basic ways of representing the numerical values of the various physical quantities with which we constantly deal in our day-to-day lives. One of the ways,

More information

Find the equivalent decimal value for the given value Other number system to decimal ( Sample)

Find the equivalent decimal value for the given value Other number system to decimal ( Sample) VELAMMAL COLLEGE OF ENGINEERING AND TECHNOLOGY, MADURAI 65 009 Department of Information Technology Model Exam-II-Question bank PART A (Answer for all Questions) (8 X = 6) K CO Marks Find the equivalent

More information

Contents Circuits... 1

Contents Circuits... 1 Contents Circuits... 1 Categories of Circuits... 1 Description of the operations of circuits... 2 Classification of Combinational Logic... 2 1. Adder... 3 2. Decoder:... 3 Memory Address Decoder... 5 Encoder...

More information

Semester III. Subject Name: Digital Electronics. Subject Code: 09CT0301. Diploma Branches in which this subject is offered: Computer Engineering

Semester III. Subject Name: Digital Electronics. Subject Code: 09CT0301. Diploma Branches in which this subject is offered: Computer Engineering Semester III Subject Name: Digital Electronics Subject Code: 09CT0301 Diploma Branches in which this subject is offered: Objective: The subject aims to prepare the students, To understand the basic of

More information

Integrated Circuits 7

Integrated Circuits 7 7 IC Test Clip Series For temporary connections to DIP package components Heavy-duty spring loaded hinge provides positive contact 20 AWG insulated gold contacts Color: white 22103 Part No. Product No.

More information

DIGITAL FUNDAMENTALS

DIGITAL FUNDAMENTALS DIGITAL FUNDAMENTALS A SYSTEMS APPROACH THOMAS L. FLOYD PEARSON Boston Columbus Indianapolis New York San Francisco Upper Saddle River Amsterdam Cape Town Dubai London Madrid Milan Munich Paris Montreal

More information

SIGNETICS INTEGRATED CIRCUITS Low Power Schottky TTL 54LS00-74LS00 Series. Supply Current/typmA Delay/typns Quad 2-Input NAND Gate 54LS00/C,D

SIGNETICS INTEGRATED CIRCUITS Low Power Schottky TTL 54LS00-74LS00 Series. Supply Current/typmA Delay/typns Quad 2-Input NAND Gate 54LS00/C,D SIGNETICS INTEGRATED CIRCUITS Low Power Schottky TTL 54LS00-74LS00 Series Rating Value Unit Voltage - V CC +7.0 V Input Voltage Range - V I -0.5 to +7.0 V Output Voltage - V out +5.5 V Operating Temperature

More information

EE Chip list. Page 1

EE Chip list. Page 1 Chip # Description 7400 Quadruple 2-Input Positive NANDS 7401 Quadruple 2-Input Positive NAND with Open-Collector Outputs 7402 Quadruple 2-input Positive NOR 7403 Quadruple 2-Intput Positive NAND with

More information

TYPICAL QUESTIONS & ANSWERS

TYPICAL QUESTIONS & ANSWERS DIGITALS ELECTRONICS TYPICAL QUESTIONS & ANSWERS OBJECTIVE TYPE QUESTIONS Each Question carries 2 marks. Choose correct or the best alternative in the following: Q.1 The NAND gate output will be low if

More information

List of the CMOS 4000 series Dual tri-input NOR Gate and Inverter Quad 2-input NOR gate Dual 4-input NOR gate

List of the CMOS 4000 series Dual tri-input NOR Gate and Inverter Quad 2-input NOR gate Dual 4-input NOR gate List of the CMOS 4000 series 4000 - Dual tri-input NOR Gate and Inverter 4001 - Quad 2-input NOR gate 4002 - Dual 4-input NOR gate 4006-18 stage Shift register 4007 - Dual Complementary Pair Plus Inverter

More information

R13 SET - 1 '' ''' '' ' '''' Code No: RT21053

R13 SET - 1 '' ''' '' ' '''' Code No: RT21053 SET - 1 1. a) What are the characteristics of 2 s complement numbers? b) State the purpose of reducing the switching functions to minimal form. c) Define half adder. d) What are the basic operations in

More information

CS302 Digital Logic Design Solved Objective Midterm Papers For Preparation of Midterm Exam

CS302 Digital Logic Design Solved Objective Midterm Papers For Preparation of Midterm Exam CS302 Digital Logic Design Solved Objective Midterm Papers For Preparation of Midterm Exam MIDTERM EXAMINATION Spring 2012 Question No: 1 ( Marks: 1 ) - Please choose one A SOP expression is equal to 1

More information

PHYSICS 5620 LAB 9 Basic Digital Circuits and Flip-Flops

PHYSICS 5620 LAB 9 Basic Digital Circuits and Flip-Flops PHYSICS 5620 LAB 9 Basic Digital Circuits and Flip-Flops Objective Construct a two-bit binary decoder. Study multiplexers (MUX) and demultiplexers (DEMUX). Construct an RS flip-flop from discrete gates.

More information

Bachelor Level/ First Year/ Second Semester/ Science Full Marks: 60 Computer Science and Information Technology (CSc. 151) Pass Marks: 24

Bachelor Level/ First Year/ Second Semester/ Science Full Marks: 60 Computer Science and Information Technology (CSc. 151) Pass Marks: 24 2065 Computer Science and Information Technology (CSc. 151) Pass Marks: 24 Time: 3 hours. Candidates are required to give their answers in their own words as for as practicable. Attempt any TWO questions:

More information

1. Convert the decimal number to binary, octal, and hexadecimal.

1. Convert the decimal number to binary, octal, and hexadecimal. 1. Convert the decimal number 435.64 to binary, octal, and hexadecimal. 2. Part A. Convert the circuit below into NAND gates. Insert or remove inverters as necessary. Part B. What is the propagation delay

More information

TIME SCHEDULE. MODULE TOPICS PERIODS 1 Number system & Boolean algebra 17 Test I 1 2 Logic families &Combinational logic

TIME SCHEDULE. MODULE TOPICS PERIODS 1 Number system & Boolean algebra 17 Test I 1 2 Logic families &Combinational logic COURSE TITLE : DIGITAL INSTRUMENTS PRINCIPLE COURSE CODE : 3075 COURSE CATEGORY : B PERIODS/WEEK : 4 PERIODS/SEMESTER : 72 CREDITS : 4 TIME SCHEDULE MODULE TOPICS PERIODS 1 Number system & Boolean algebra

More information

NORTHWESTERN UNIVERSITY TECHNOLOGICAL INSTITUTE

NORTHWESTERN UNIVERSITY TECHNOLOGICAL INSTITUTE NORTHWESTERN UNIVERSITY TECHNOLOGICL INSTITUTE ECE 270 Experiment #8 DIGITL CIRCUITS Prelab 1. Draw the truth table for the S-R Flip-Flop as shown in the textbook. Draw the truth table for Figure 7. 2.

More information

Experiment (6) 2- to 4 Decoder. Figure 8.1 Block Diagram of 2-to-4 Decoder 0 X X

Experiment (6) 2- to 4 Decoder. Figure 8.1 Block Diagram of 2-to-4 Decoder 0 X X 8. Objectives : Experiment (6) Decoders / Encoders To study the basic operation and design of both decoder and encoder circuits. To describe the concept of active low and active-high logic signals. To

More information

EXPERIMENT: 1. Graphic Symbol: OR: The output of OR gate is true when one of the inputs A and B or both the inputs are true.

EXPERIMENT: 1. Graphic Symbol: OR: The output of OR gate is true when one of the inputs A and B or both the inputs are true. EXPERIMENT: 1 DATE: VERIFICATION OF BASIC LOGIC GATES AIM: To verify the truth tables of Basic Logic Gates NOT, OR, AND, NAND, NOR, Ex-OR and Ex-NOR. APPARATUS: mention the required IC numbers, Connecting

More information

Midterm Exam 15 points total. March 28, 2011

Midterm Exam 15 points total. March 28, 2011 Midterm Exam 15 points total March 28, 2011 Part I Analytical Problems 1. (1.5 points) A. Convert to decimal, compare, and arrange in ascending order the following numbers encoded using various binary

More information

VU Mobile Powered by S NO Group

VU Mobile Powered by S NO Group Question No: 1 ( Marks: 1 ) - Please choose one A 8-bit serial in / parallel out shift register contains the value 8, clock signal(s) will be required to shift the value completely out of the register.

More information

R13. II B. Tech I Semester Regular Examinations, Jan DIGITAL LOGIC DESIGN (Com. to CSE, IT) PART-A

R13. II B. Tech I Semester Regular Examinations, Jan DIGITAL LOGIC DESIGN (Com. to CSE, IT) PART-A SET - 1 Note: Question Paper consists of two parts (Part-A and Part-B) Answer ALL the question in Part-A Answer any THREE Questions from Part-B a) What are the characteristics of 2 s complement numbers?

More information

Course Plan. Course Articulation Matrix: Mapping of Course Outcomes (COs) with Program Outcomes (POs) PSO-1 PSO-2

Course Plan. Course Articulation Matrix: Mapping of Course Outcomes (COs) with Program Outcomes (POs) PSO-1 PSO-2 Course Plan Semester: 4 - Semester Year: 2019 Course Title: DIGITAL ELECTRONICS Course Code: EC106 Semester End Examination: 70 Continuous Internal Evaluation: 30 Lesson Plan Author: Ms. CH SRIDEVI Last

More information

Subject : EE6301 DIGITAL LOGIC CIRCUITS

Subject : EE6301 DIGITAL LOGIC CIRCUITS QUESTION BANK Programme : BE Subject : Semester / Branch : III/EEE UNIT 1 NUMBER SYSTEMS AND DIGITAL LOGIC FAMILIES Review of number systems, binary codes, error detection and correction codes (Parity

More information

Laboratory Objectives and outcomes for Digital Design Lab

Laboratory Objectives and outcomes for Digital Design Lab Class: SE Department of Information Technology Subject Logic Design Sem : III Course Objectives and outcomes for LD Course Objectives: Students will try to : COB1 Understand concept of various components.

More information

Lab #6: Combinational Circuits Design

Lab #6: Combinational Circuits Design Lab #6: Combinational Circuits Design PURPOSE: The purpose of this laboratory assignment is to investigate the design of combinational circuits using SSI circuits. The combinational circuits being implemented

More information

DIGITAL ELECTRONICS & it0203 Semester 3

DIGITAL ELECTRONICS & it0203 Semester 3 DIGITAL ELECTRONICS & it0203 Semester 3 P.Rajasekar & C.M.T.Karthigeyan Asst.Professor SRM University, Kattankulathur School of Computing, Department of IT 8/22/20 Disclaimer The contents of the slides

More information

Logic Design Viva Question Bank Compiled By Channveer Patil

Logic Design Viva Question Bank Compiled By Channveer Patil Logic Design Viva Question Bank Compiled By Channveer Patil Title of the Practical: Verify the truth table of logic gates AND, OR, NOT, NAND and NOR gates/ Design Basic Gates Using NAND/NOR gates. Q.1

More information

Department of Computer Science and Engineering Question Bank- Even Semester:

Department of Computer Science and Engineering Question Bank- Even Semester: Department of Computer Science and Engineering Question Bank- Even Semester: 2014-2015 CS6201& DIGITAL PRINCIPLES AND SYSTEM DESIGN (Common to IT & CSE, Regulation 2013) UNIT-I 1. Convert the following

More information

Advanced Devices. Registers Counters Multiplexers Decoders Adders. CSC258 Lecture Slides Steve Engels, 2006 Slide 1 of 20

Advanced Devices. Registers Counters Multiplexers Decoders Adders. CSC258 Lecture Slides Steve Engels, 2006 Slide 1 of 20 Advanced Devices Using a combination of gates and flip-flops, we can construct more sophisticated logical devices. These devices, while more complex, are still considered fundamental to basic logic design.

More information

PURBANCHAL UNIVERSITY

PURBANCHAL UNIVERSITY [c] Implement a full adder circuit with a decoder and two OR gates. [4] III SEMESTER FINAL EXAMINATION-2006 Q. [4] [a] What is flip flop? Explain flip flop operating characteristics. [6] [b] Design and

More information

MODEL QUESTIONS WITH ANSWERS THIRD SEMESTER B.TECH DEGREE EXAMINATION DECEMBER CS 203: Switching Theory and Logic Design. Time: 3 Hrs Marks: 100

MODEL QUESTIONS WITH ANSWERS THIRD SEMESTER B.TECH DEGREE EXAMINATION DECEMBER CS 203: Switching Theory and Logic Design. Time: 3 Hrs Marks: 100 MODEL QUESTIONS WITH ANSWERS THIRD SEMESTER B.TECH DEGREE EXAMINATION DECEMBER 2016 CS 203: Switching Theory and Logic Design Time: 3 Hrs Marks: 100 PART A ( Answer All Questions Each carries 3 Marks )

More information

CS6201 UNIT I PART-A. Develop or build the following Boolean function with NAND gate F(x,y,z)=(1,2,3,5,7).

CS6201 UNIT I PART-A. Develop or build the following Boolean function with NAND gate F(x,y,z)=(1,2,3,5,7). VALLIAMMAI ENGINEERING COLLEGE SRM Nagar, Kattankulathur-603203 DEPARTMENT OF COMPUTER SCIENCE AND ENGINEERING Academic Year: 2015-16 BANK - EVEN SEMESTER UNIT I PART-A 1 Find the octal equivalent of hexadecimal

More information

Solution to Digital Logic )What is the magnitude comparator? Design a logic circuit for 4 bit magnitude comparator and explain it,

Solution to Digital Logic )What is the magnitude comparator? Design a logic circuit for 4 bit magnitude comparator and explain it, Solution to Digital Logic -2067 Solution to digital logic 2067 1.)What is the magnitude comparator? Design a logic circuit for 4 bit magnitude comparator and explain it, A Magnitude comparator is a combinational

More information

gate symbols will appear in schematic Dierent of a circuit. Standard gate symbols have been diagram Figures 5-3 and 5-4 show standard shapes introduce

gate symbols will appear in schematic Dierent of a circuit. Standard gate symbols have been diagram Figures 5-3 and 5-4 show standard shapes introduce chapter is concerned with examples of basic This circuits including decoders, combinational xor gate and parity circuits, multiplexers, comparators, adders. Those basic building circuits frequently and

More information

Date: Author: New: Revision: x SAULT COLLEGE OF APPLIED ARTS & TECHNOLOGY SAULT STE. MARIE, ONTARIO ELN TWO

Date: Author: New: Revision: x SAULT COLLEGE OF APPLIED ARTS & TECHNOLOGY SAULT STE. MARIE, ONTARIO ELN TWO SAULT COLLEGE OF APPLIED ARTS & TECHNOLOGY SAULT STE. MARIE, ONTARIO COURSE OUTLINE Course Title: DIGITAL ELECTRONICS Code No.: ELN 107-5 Program: ELECTRICAL/ELECTRONIC TECHNICIAN Semester: TWO Date: AUGUST

More information

DIGITAL ELECTRONICS MCQs

DIGITAL ELECTRONICS MCQs DIGITAL ELECTRONICS MCQs 1. A 8-bit serial in / parallel out shift register contains the value 8, clock signal(s) will be required to shift the value completely out of the register. A. 1 B. 2 C. 4 D. 8

More information

Semester 6 DIGITAL ELECTRONICS- core subject -10 Credit-4

Semester 6 DIGITAL ELECTRONICS- core subject -10 Credit-4 Semester 6 DIGITAL ELECTRONICS- core subject -10 Credit-4 Unit I Number system, Binary, decimal, octal, hexadecimal-conversion from one another-binary addition, subtraction, multiplication, division-binary

More information

Chapter 3. Boolean Algebra and Digital Logic

Chapter 3. Boolean Algebra and Digital Logic Chapter 3 Boolean Algebra and Digital Logic Chapter 3 Objectives Understand the relationship between Boolean logic and digital computer circuits. Learn how to design simple logic circuits. Understand how

More information

MODULE 3. Combinational & Sequential logic

MODULE 3. Combinational & Sequential logic MODULE 3 Combinational & Sequential logic Combinational Logic Introduction Logic circuit may be classified into two categories. Combinational logic circuits 2. Sequential logic circuits A combinational

More information

High Performance Carry Chains for FPGAs

High Performance Carry Chains for FPGAs High Performance Carry Chains for FPGAs Matthew M. Hosler Department of Electrical and Computer Engineering Northwestern University Abstract Carry chains are an important consideration for most computations,

More information

Final Exam review: chapter 4 and 5. Supplement 3 and 4

Final Exam review: chapter 4 and 5. Supplement 3 and 4 Final Exam review: chapter 4 and 5. Supplement 3 and 4 1. A new type of synchronous flip-flop has the following characteristic table. Find the corresponding excitation table with don t cares used as much

More information

DIGITAL SYSTEM DESIGN UNIT I (2 MARKS)

DIGITAL SYSTEM DESIGN UNIT I (2 MARKS) DIGITAL SYSTEM DESIGN UNIT I (2 MARKS) 1. Convert Binary number (111101100) 2 to Octal equivalent. 2. Convert Binary (1101100010011011) 2 to Hexadecimal equivalent. 3. Simplify the following Boolean function

More information

Digital Electronic Circuits Design & Laboratory Guideline

Digital Electronic Circuits Design & Laboratory Guideline D.2. Encoders Often we use diverse peripheral devices such as switches, numeric keypads and more in order to interface the analog world with the digital one and, along with the usage of these devices,

More information

2. Counter Stages or Bits output bits least significant bit (LSB) most significant bit (MSB) 3. Frequency Division 4. Asynchronous Counters

2. Counter Stages or Bits output bits least significant bit (LSB) most significant bit (MSB) 3. Frequency Division 4. Asynchronous Counters 2. Counter Stages or Bits The number of output bits of a counter is equal to the flip-flop stages of the counter. A MOD-2 n counter requires n stages or flip-flops in order to produce a count sequence

More information

CSE221- Logic Design, Spring 2003

CSE221- Logic Design, Spring 2003 EE207: Digital Systems I, Semester I 2003/2004 CHAPTER 3 -ii: Combinational Logic Design Design Procedure, Encoders/Decoders (Sections 3.4 3.6) Overview Design Procedure Code Converters Binary Decoders

More information

Dev Bhoomi Institute Of Technology Department of Electronics and Communication Engineering PRACTICAL INSTRUCTION SHEET

Dev Bhoomi Institute Of Technology Department of Electronics and Communication Engineering PRACTICAL INSTRUCTION SHEET Dev Bhoomi Institute Of Technology Department of Electronics and Communication Engineering PRACTICAL INSTRUCTION SHEET LABORATORY MANUAL EXPERIMENT NO. 1 ISSUE NO. : ISSUE DATE: REV. NO. : REV. DATE :

More information

Minnesota State College Southeast

Minnesota State College Southeast ELEC 2211: Digital Electronics II A. COURSE DESCRIPTION Credits: 4 Lecture Hours/Week: 2 Lab Hours/Week: 4 OJT Hours/Week: *.* Prerequisites: None Corequisites: None MnTC Goals: None Minnesota State College

More information

UNIT 1 NUMBER SYSTEMS AND DIGITAL LOGIC FAMILIES 1. Briefly explain the stream lined method of converting binary to decimal number with example. 2. Give the Gray code for the binary number (111) 2. 3.

More information

Page No.1. CS302 Digital Logic & Design_ Muhammad Ishfaq

Page No.1. CS302 Digital Logic & Design_ Muhammad Ishfaq Page No.1 File Version Update: (Dated: 17-May-2011) This version of file contains: Content of the Course (Done) FAQ updated version.(these must be read once because some very basic definition and question

More information

CHAPTER 4 RESULTS & DISCUSSION

CHAPTER 4 RESULTS & DISCUSSION CHAPTER 4 RESULTS & DISCUSSION 3.2 Introduction This project aims to prove that Modified Baugh-Wooley Two s Complement Signed Multiplier is one of the high speed multipliers. The schematic of the multiplier

More information

Encoders and Decoders: Details and Design Issues

Encoders and Decoders: Details and Design Issues Encoders and Decoders: Details and Design Issues Edward L. Bosworth, Ph.D. TSYS School of Computer Science Columbus State University Columbus, GA 31907 bosworth_edward@colstate.edu Slide 1 of 25 slides

More information

WINTER 15 EXAMINATION Model Answer

WINTER 15 EXAMINATION Model Answer Important Instructions to examiners: 1) The answers should be examined by key words and not as word-to-word as given in the model answer scheme. 2) The model answer and the answer written by candidate

More information

UNIT 1: DIGITAL LOGICAL CIRCUITS What is Digital Computer? OR Explain the block diagram of digital computers.

UNIT 1: DIGITAL LOGICAL CIRCUITS What is Digital Computer? OR Explain the block diagram of digital computers. UNIT 1: DIGITAL LOGICAL CIRCUITS What is Digital Computer? OR Explain the block diagram of digital computers. Digital computer is a digital system that performs various computational tasks. The word DIGITAL

More information

Tribhuvan University Institute of Science and Technology Bachelor of Science in Computer Science and Information Technology

Tribhuvan University Institute of Science and Technology Bachelor of Science in Computer Science and Information Technology Tribhuvan University Institute of Science and Technology Bachelor of Science in Computer Science and Information Technology Course Title: Digital Logic Full Marks: 60 + 0 + 0 Course No.: CSC Pass Marks:

More information

Digital Circuits ECS 371

Digital Circuits ECS 371 Digital Circuits ECS 37 Dr. Prapun Suksompong prapun@siit.tu.ac.th Lecture 0 Office Hours: BKD 360-7 Monday 9:00-0:30, :30-3:30 Tuesday 0:30-:30 Announcement HW4 posted on the course web site Chapter 5:

More information

Nirma University Institute of Technology. Electronics and Communication Engineering Department. Course Policy

Nirma University Institute of Technology. Electronics and Communication Engineering Department. Course Policy Nirma University Institute of Technology Electronics and Communication Engineering Department Course Policy B. Tech Semester - III Academic Year: 2017 Course Code & Name : Credit Details : L T P C 4 2

More information

Engineering College. Electrical Engineering Department. Digital Electronics Lab

Engineering College. Electrical Engineering Department. Digital Electronics Lab Engineering College Electrical Engineering Department Digital Electronics Lab Prepared by: Dr. Samer Mayaleh Eng. Nuha Odeh 2009/2010-1 - CONTENTS Experiment Name Page 1- Measurement of Basic Logic Gates

More information

Operating Manual Ver.1.1

Operating Manual Ver.1.1 Event Counter Operating Manual Ver.1.1 An ISO 9001 : 2000 company 94-101, Electronic Complex Pardesipura, Indore- 452010, India Tel : 91-731- 2570301/02, 4211100 Fax: 91-731- 2555643 e mail : info@scientech.bz

More information

Come and join us at WebLyceum

Come and join us at WebLyceum Come and join us at WebLyceum For Past Papers, Quiz, Assignments, GDBs, Video Lectures etc Go to http://www.weblyceum.com and click Register In Case of any Problem Contact Administrators Rana Muhammad

More information

North Shore Community College

North Shore Community College North Shore Community College Course Number: IEL217 Section: MAL Course Name: Digital Electronics 1 Semester: Credit: 4 Hours: Three hours of Lecture, Two hours Laboratory per week Thursdays 8:00am (See

More information

Introduction to Digital Logic Missouri S&T University CPE 2210 Exam 3 Logistics

Introduction to Digital Logic Missouri S&T University CPE 2210 Exam 3 Logistics Introduction to Digital Logic Missouri S&T University CPE 2210 Exam 3 Logistics Egemen K. Çetinkaya Egemen K. Çetinkaya Department of Electrical & Computer Engineering Missouri University of Science and

More information

1. True/False Questions (10 x 1p each = 10p) (a) I forgot to write down my name and student ID number.

1. True/False Questions (10 x 1p each = 10p) (a) I forgot to write down my name and student ID number. CprE 281: Digital Logic Midterm 2: Friday Oct 30, 2015 Student Name: Student ID Number: Lab Section: Mon 9-12(N) Mon 12-3(P) Mon 5-8(R) Tue 11-2(U) (circle one) Tue 2-5(M) Wed 8-11(J) Wed 6-9(Y) Thur 11-2(Q)

More information

ISSN:

ISSN: 427 AN EFFICIENT 64-BIT CARRY SELECT ADDER WITH REDUCED AREA APPLICATION CH PALLAVI 1, VSWATHI 2 1 II MTech, Chadalawada Ramanamma Engg College, Tirupati 2 Assistant Professor, DeptofECE, CREC, Tirupati

More information

Logic Design II (17.342) Spring Lecture Outline

Logic Design II (17.342) Spring Lecture Outline Logic Design II (17.342) Spring 2012 Lecture Outline Class # 03 February 09, 2012 Dohn Bowden 1 Today s Lecture Registers and Counters Chapter 12 2 Course Admin 3 Administrative Admin for tonight Syllabus

More information

DIGITAL CIRCUIT LOGIC UNIT 9: MULTIPLEXERS, DECODERS, AND PROGRAMMABLE LOGIC DEVICES

DIGITAL CIRCUIT LOGIC UNIT 9: MULTIPLEXERS, DECODERS, AND PROGRAMMABLE LOGIC DEVICES DIGITAL CIRCUIT LOGIC UNIT 9: MULTIPLEXERS, DECODERS, AND PROGRAMMABLE LOGIC DEVICES 1 Learning Objectives 1. Explain the function of a multiplexer. Implement a multiplexer using gates. 2. Explain the

More information

ระบบคอมพ วเตอร และการเช อมโยง Computer Systems and Interfacing บทท 1 พ นฐานด จ ตอล

ระบบคอมพ วเตอร และการเช อมโยง Computer Systems and Interfacing บทท 1 พ นฐานด จ ตอล 04-612-307 ระบบคอมพ วเตอร และการเช อมโยง Computer Systems and Interfacing บทท 1 พ นฐานด จ ตอล สาขาว ชาว ศวกรรมคอมพ วเตอร คณะว ศวกรรมศาสตร มหาว ทยาล ยเทคโนโลย ราชมงคลพระนคร Digital and Analog Quantities

More information

ECE 263 Digital Systems, Fall 2015

ECE 263 Digital Systems, Fall 2015 ECE 263 Digital Systems, Fall 2015 REVIEW: FINALS MEMORY ROM, PROM, EPROM, EEPROM, FLASH RAM, DRAM, SRAM Design of a memory cell 1. Draw circuits and write 2 differences and 2 similarities between DRAM

More information

Electrical and Telecommunications Engineering Technology_TCET3122/TC520. NEW YORK CITY COLLEGE OF TECHNOLOGY The City University of New York

Electrical and Telecommunications Engineering Technology_TCET3122/TC520. NEW YORK CITY COLLEGE OF TECHNOLOGY The City University of New York NEW YORK CITY COLLEGE OF TECHNOLOGY The City University of New York DEPARTMENT: SUBJECT CODE AND TITLE: COURSE DESCRIPTION: REQUIRED: Electrical and Telecommunications Engineering Technology TCET 3122/TC

More information

MAHARASHTRA STATE BOARD OF TECHNICAL EDUCATION (Autonomous) (ISO/IEC Certified) WINTER 2018 EXAMINATION MODEL ANSWER

MAHARASHTRA STATE BOARD OF TECHNICAL EDUCATION (Autonomous) (ISO/IEC Certified) WINTER 2018 EXAMINATION MODEL ANSWER Important Instructions to examiners: 1) The answers should be examined by key words and not as word-to-word as given in themodel answer scheme. 2) The model answer and the answer written by candidate may

More information

Implementation of Low Power and Area Efficient Carry Select Adder

Implementation of Low Power and Area Efficient Carry Select Adder International Journal of Engineering Science Invention ISSN (Online): 2319 6734, ISSN (Print): 2319 6726 Volume 3 Issue 8 ǁ August 2014 ǁ PP.36-48 Implementation of Low Power and Area Efficient Carry Select

More information

Helping Material of CS302

Helping Material of CS302 ABEL : Advanced Boolean Expression Language; a software compiler language for SPLD programming; a type of hardware description language (HDL) Adder : A digital circuit which forms the sum and carry of

More information

ECE 372 Microcontroller Design

ECE 372 Microcontroller Design E.g. Port A, Port B Used to interface with many devices Switches LEDs LCD Keypads Relays Stepper Motors Interface with digital IO requires us to connect the devices correctly and write code to interface

More information

A.R. ENGINEERING COLLEGE, VILLUPURAM ECE DEPARTMENT

A.R. ENGINEERING COLLEGE, VILLUPURAM ECE DEPARTMENT .R. ENGINEERING COLLEGE, VILLUPURM ECE EPRTMENT QUESTION BNK SUB. NME: IGITL ELECTRONICS SUB. COE: EC223 SEM: III BRNCH/YER: ECE/II UNIT-I MINIMIZTION TECHNIQUESN LOGIC GTES PRT- ) efine Minterm & Maxterm.

More information

1. a) For the circuit shown in figure 1.1, draw a truth table showing the output Q for all combinations of inputs A, B and C. [4] Figure 1.

1. a) For the circuit shown in figure 1.1, draw a truth table showing the output Q for all combinations of inputs A, B and C. [4] Figure 1. [Question 1 is compulsory] 1. a) For the circuit shown in figure 1.1, draw a truth table showing the output Q for all combinations of inputs A, B and C. Figure 1.1 b) Minimize the following Boolean functions:

More information

QUICK GUIDE COMPUTER LOGICAL ORGANIZATION - OVERVIEW

QUICK GUIDE COMPUTER LOGICAL ORGANIZATION - OVERVIEW QUICK GUIDE http://www.tutorialspoint.com/computer_logical_organization/computer_logical_organization_quick_guide.htm COMPUTER LOGICAL ORGANIZATION - OVERVIEW Copyright tutorialspoint.com In the modern

More information

EEE130 Digital Electronics I Lecture #1_2. Dr. Shahrel A. Suandi

EEE130 Digital Electronics I Lecture #1_2. Dr. Shahrel A. Suandi EEE130 Digital Electronics I Lecture #1_2 Dr. Shahrel A. Suandi 1-4 Overview of Basic Logic Functions Digital systems are generally built from combinations of NOT, AND and OR logic elements The combinations

More information

BCN1043. By Dr. Mritha Ramalingam. Faculty of Computer Systems & Software Engineering

BCN1043. By Dr. Mritha Ramalingam. Faculty of Computer Systems & Software Engineering BCN1043 By Dr. Mritha Ramalingam Faculty of Computer Systems & Software Engineering mritha@ump.edu.my http://ocw.ump.edu.my/ authors Dr. Mohd Nizam Mohmad Kahar (mnizam@ump.edu.my) Jamaludin Sallim (jamal@ump.edu.my)

More information

MAHARASHTRA STATE BOARD OF TECHNICAL EDUCATION (Autonomous) (ISO/IEC Certified)

MAHARASHTRA STATE BOARD OF TECHNICAL EDUCATION (Autonomous) (ISO/IEC Certified) Important Instructions to examiners: 1) The answers should be examined by key words and not as word-to-word as given in the model answer scheme. 2) The model answer and the answer written by candidate

More information

LECTURE NOTES. ON Digital Circuit And Systems

LECTURE NOTES. ON Digital Circuit And Systems Digital circuit&systems LECTURE NOTES ON Digital Circuit And Systems 2018 2019 III B. Tech I Semester (JNTUA-R15) Mrs.M.CHANDINI, Assistant Professor CHADALAWADA RAMANAMMA ENGINEERING COLLEGE (AUTONOMOUS)

More information

EC6302-DIGITAL ELECTRONICS II YEAR /III SEMESTER ECE ACADEMIC YEAR

EC6302-DIGITAL ELECTRONICS II YEAR /III SEMESTER ECE ACADEMIC YEAR LECTURER NOTES ON EC6302-DIGITAL ELECTRONICS II YEAR /III SEMESTER ECE ACADEMIC YEAR 2014-2015 D.ANTONYPANDIARAJAN ASSISTANT PROFESSOR FMCET Introduction: The English mathematician George Boole (1815-1864)

More information

TEST-3 (DIGITAL ELECTRONICS)-(EECTRONIC)

TEST-3 (DIGITAL ELECTRONICS)-(EECTRONIC) 1 TEST-3 (DIGITAL ELECTRONICS)-(EECTRONIC) Q.1 The flip-flip circuit is. a) Unstable b) multistable c) Monostable d) bitable Q.2 A digital counter consists of a group of a) Flip-flop b) half adders c)

More information

An Efficient 64-Bit Carry Select Adder With Less Delay And Reduced Area Application

An Efficient 64-Bit Carry Select Adder With Less Delay And Reduced Area Application An Efficient 64-Bit Carry Select Adder With Less Delay And Reduced Area Application K Allipeera, M.Tech Student & S Ahmed Basha, Assitant Professor Department of Electronics & Communication Engineering

More information

12-bit Wallace Tree Multiplier CMPEN 411 Final Report Matthew Poremba 5/1/2009

12-bit Wallace Tree Multiplier CMPEN 411 Final Report Matthew Poremba 5/1/2009 12-bit Wallace Tree Multiplier CMPEN 411 Final Report Matthew Poremba 5/1/2009 Project Overview This project was originally titled Fast Fourier Transform Unit, but due to space and time constraints, the

More information

ET398 LAB 4. Concurrent Statements, Selection and Process

ET398 LAB 4. Concurrent Statements, Selection and Process ET398 LAB 4 Concurrent Statements, Selection and Process Decoders/Multiplexers February 16, 2013 Tiffany Turner OBJECTIVE The objectives of this lab were for us to become more adept at creating VHDL code

More information

EXPERIMENT 13 ITERATIVE CIRCUITS

EXPERIMENT 13 ITERATIVE CIRCUITS EE 2449 Experiment 13 Revised 4/17/2017 CALIFORNIA STATE UNIVERSITY LOS ANGELES Department of Electrical and Computer Engineering EE-246 Digital Logic Lab EXPERIMENT 13 ITERATIVE CIRCUITS Text: Mano, Digital

More information

Department of Electrical Engineering University of Hail Ha il - Saudi Arabia

Department of Electrical Engineering University of Hail Ha il - Saudi Arabia Department of Electrical Engineering University of Hail Ha il - Saudi Arabia Laboratory Manual EE 200 Digital Logic Circuit Design October 2017 1 PREFACE This document is prepared to serve as a laboratory

More information

EKT 121/4 ELEKTRONIK DIGIT 1

EKT 121/4 ELEKTRONIK DIGIT 1 EKT 2/4 ELEKTRONIK DIGIT Kolej Universiti Kejuruteraan Utara Malaysia Sequential Logic Circuits - COUNTERS - LATCHES (review) S-R R Latch S-R R Latch Active-LOW input INPUTS OUTPUTS S R Q Q COMMENTS Q

More information

4.S-[F] SU-02 June All Syllabus Science Faculty B.Sc. II Yr. Instrumentation Practice [Sem.III & IV] S.Lot

4.S-[F] SU-02 June All Syllabus Science Faculty B.Sc. II Yr. Instrumentation Practice [Sem.III & IV] S.Lot [Sem.III & IV] S.Lot. - 1 - [Sem.III & IV] S.Lot. - 2 - [Sem.III & IV] S.Lot. - 3 - Syllabus B.Sc. ( Instrumentation Practice ) Second Year ( Third and Forth Semester ) ( Effective from June 2014 ) [Sem.III

More information

DEPARTMENT OF COMPUTER SCIENCE & ENGINEERING

DEPARTMENT OF COMPUTER SCIENCE & ENGINEERING DRONACHARYA GROUP OF INSTITUTIONS, GREATER NOIDA Affiliated to Mahamaya Technical University, Noida Approved by AICTE DEPARTMENT OF COMPUTER SCIENCE & ENGINEERING Lab Manual for Computer Organization Lab

More information

SAULT COLLEGE OF APPLIED ARTS & TECHNOLOGY SAULT STE. MARIE, ONTARIO LOGIC & SWITCHING CIRCUITS NON-SEMESTERED TECHNICIAN PROGRAM

SAULT COLLEGE OF APPLIED ARTS & TECHNOLOGY SAULT STE. MARIE, ONTARIO LOGIC & SWITCHING CIRCUITS NON-SEMESTERED TECHNICIAN PROGRAM SAULT COLLEGE OF APPLED ARTS & TECHNOLOGY SAULT STE. MARE, ONTARO COURSE OUTLNE Course Title: LOGC & SWTCHNG CRCUTS Code No.: ELN 207 Program: Semester: Date: Author: NON-SEMESTERED TECHNCAN PROGRAM THREE

More information

St. MARTIN S ENGINEERING COLLEGE

St. MARTIN S ENGINEERING COLLEGE St. MARTIN S ENGINEERING COLLEGE Dhulapally, Kompally, Secunderabad-500014. Branch Year&Sem Subject Name : Electronics and Communication Engineering : II B. Tech I Semester : SWITCHING THEORY AND LOGIC

More information

Counters. ENT 263 Digital Electronics

Counters. ENT 263 Digital Electronics Counters ENT 263 Digital Electronics Objectives Describe the difference between an asynchronous and a synchronous counter Analyze counter timing diagram Analyze counter circuits Determine the sequence

More information

Design and Implementation of High Speed 256-Bit Modified Square Root Carry Select Adder

Design and Implementation of High Speed 256-Bit Modified Square Root Carry Select Adder Design and Implementation of High Speed 256-Bit Modified Square Root Carry Select Adder Muralidharan.R [1], Jodhi Mohana Monica [2], Meenakshi.R [3], Lokeshwaran.R [4] B.Tech Student, Department of Electronics

More information

ME 515 Mechatronics. Introduction to Digital Electronics

ME 515 Mechatronics. Introduction to Digital Electronics ME 55 Mechatronics /5/26 ME 55 Mechatronics Digital Electronics Asanga Ratnaweera Department of Faculty of Engineering University of Peradeniya Tel: 8239 (3627) Email: asangar@pdn.ac.lk Introduction to

More information