UNIVERSITI MALAYSIA PERLIS. EKT 124 Digital Electronics 1 [Electronik Digit 1]

Size: px

Start display at page:

Download "UNIVERSITI MALAYSIA PERLIS. EKT 124 Digital Electronics 1 [Electronik Digit 1]"

Cori Logan
6 years ago
Views:

1 UNIVERSITI MALAYSIA PERLIS Peperiksaan Semester Kedua Sidang Akademik 2013/2014 May 2014 EKT 124 Digital Electronics 1 [Electronik Digit 1] Duration : 3 hours Masa : 3 jam Please make sure that this paper has TEN (10) printed pages including this front page before you start the examination. [Sila pastikan kertas soalan ini mengandungi SEPULUH (10) muka surat yang bercetak termasuk muka hadapan sebelum anda memulakan peperiksaan ini.] This question paper has FIVE (5) questions. Answer ALL questions. [Kertas soalan ini mengandungi LIMA (5) soalan. Jawab SEMUA soalan.]

2 -2- (EKT124) Question 1 [Soalan 1] [C2, CO1, PO1] (a) Convert the following numbers according to the base given. Write the solution for each conversion. [Tukar nombor-nombor berikut berdasarkan asas yang diberikan. Tulis jalan penyelesaian untuk setiap penukaran.] (i) 57 8 to binary [2 marks/markah] (ii) 3B.C 16 to decimal [2 marks/markah] (iii) to hexadecimal [2 marks/markah] (b) [C3,CO2,PO1] Compute addition from the BCD representation given a pair of decimal numbers. [Kira penambahan dari perwakilan BCD diberi sepasang nombor desimal.] [3 marks/markah] (c) Given a Boolean expression [Diberi pernyataan Boolean] X = AB + BCD + ABCD (i) (ii) (iii) [C3,CO2,PO1] Produce a standard Sum of Product (SOP) expression from the expression [Hasilkan pernyataan piawai SOP daripada pernyataan tersebut] [C3,CO2,PO1] Produce a truth table from the standard SOP expression in (i) [3 marks/markah] [Hasilkan jadual kebenaran daripada pernyataan piawai SOP di (i)] [C3,CO2,PO1] Write minimized Boolean expression by using Karnaugh Map (K-Map) method [Tulis pernyataan Boolean minimum menggunakan kaedah Karnaugh Map]

3 -3- (EKT124) Question 2 [Soalan 2] [C5,CO3,PO2] (a) Figure 1 is a block diagram for a full adder. Using Figure 1, design a six-bit (6 bit) ripple adder and label the diagram properly. [Rajah 1 adalah rajah blok bagi penambah penuh. Dengan menggunakan Rajah 1, rekabentuk penambah penuh riak enam-bit dan label gambarajah dengan betul.] X Y XYCin Co0 CoutΣ Co1 Σ0 Figure 1 [Rajah 1] [C3,CO3,PO2] (b) A six-bit (6 bit) subtractor can be build using the six-bit (6 bit) ripple adder and six inverters. Redesign the adder in (a) to be a six-bit (6 bit) subtractor. Demonstrate the subtraction of and by adding and Complete the Table 1 below. [Satu enam-bit penolak boleh dibangunkan dengan menggunakan enam-bit penambah riak dan enam penyongsang. Ubahsuai penambah di (a) kepada enam-bit penolak..tunjukkan proses penolakan bagi dan dengan mencampurkan dan Lengkapkan Jadual 1 dibawah.] x5 x4 x3 x2 x1 x0 y5 y4 y3 y2 y1 y0 Σ5 Σ5 Σ4 Σ3 Σ1 Σ0 Co6 Co5 Co4 Co3 Co2 Co1 Co0 Table 1 [Jadual 1] 4/10

4 -4- (EKT124) [C4,C5,CO3,PO2] (c) Figure 2 is a block diagram of a 10 line to 4 line encoder. It is a basic encoder for decimal number to Binary Coded Decimal (BCD). (i) Construct the truth table for the encoder. (ii) Analyze the output and design the logic circuit for the encoder. [Rajah 2 adalah rajah blok bagi 10 talian ke 4 talian pengekod. Ini adalah pengekod asas bagi nombor perpuluhan kepada kod binari perpuluhan (BCD). (i) Bina jadual kebenaran bagi pengekod tersebut. (ii) Analisa hasil keluaran dan rekabentuk litar logik bagi pengekod tersebut.] [12 marks/markah] I0 I1 I2 I3 I4 I5 I6 I7 I8 I9 A0 A1 A2 A3 Figure 2 [Rajah 2]

-5- (EKT124) Question 3 [Soalan3] [C3,CO3,PO2] (a) Refer to the multiplexer in Figure 3, and based on the data selector waveforms in Appendix A, produce a timing diagram of the output for the

5 -5- (EKT124) Question 3 [Soalan3] [C3,CO3,PO2] (a) Refer to the multiplexer in Figure 3, and based on the data selector waveforms in Appendix A, produce a timing diagram of the output for the following data input states: [Merujuk kepada pemultipleks di Rajah 3, dan berdasarkan kepada input gelombang data pilihan seperti Appendiks A, hasilkan rajah pemasaan untuk gelombang output bagi input-input berikut:] D 0 = 1, D 1 = 0, D 2 = 1, D 3 = 0 Figure 3 [Rajah 3] [6 marks/markah] (b) Given the following standard SOP Boolean function F(A,B,C,D) = Σ (1,3,4,11,12,13,14,15), whereby A is the Most Significant Bit (MSB). [Diberikan fungsi Boolean piawaian hasil tambah hasil darab (SOP) seperti berikut F(A,B,C,D) = Σ (1,3,4,11,12,13,14,15), dimana A adalah bit paling signifikan (MSB).] (i) [C3,CO2,PO1] Construct a truth table for the Boolean function given. [Jana jadual kebenaran menggunakan fungsi Boolean yang diberikan.] (ii) [C5,CO3,PO2] Design a logic circuit using an 8-to-1 multiplexer from the truth table obtained in (i) and label all the inputs clearly. [Rekabentuk litar logik menggunakan pemultipleks 8-ke-1 daripada jadual kebenaran yang didapati di (i) dan labelkan semua input secara jelas.] 6/10

6 -6- (EKT124) (c) A three (3) bit data (A (MSB), B, C) is to be transmitted in a system with an even parity bit error correction scheme. [Tiga (3) bit data dihantar melalui sistem yang mempunyai skim pembetulan pariti bit ralat genap.] (i) (ii) (iii) [C5,CO3,PO2] Construct a truth-table for an even parity generator for all possible input. [Bangunkan jadual kebenaran untuk pariti bit ralat genap ini untuk kesemua masukan] [2 marks/markah] [C5,CO3,PO2] Write the Boolean expression of the even parity generator using K-Map [Tulis ungkapan Boolean bagi penjana pariti bit ralat genap dengan menggunakan K-Map] [2 marks/markah] [C5,CO3,PO2] Write simplification of the Boolean expression obtain in (ii) [Tulis ringkasan ungkapan Boolean yang didapati di (ii) ] [2 marks/markah]

7 -7- (EKT124) Question 4 [Soalan4] [C2,C04,PO2,PO11] (a) Illustrate logic diagram of respective shift register: [Gambarkan gambarajah logik bagi daftar anjak berikut:] i) Serial In/Parallel Out (SIPO) [Siri Masuk / Selari Keluar (SIPO)] ii) Parallel In/Parallel Out (PIPO) [Selari Masuk/ Selari Keluar (PIPO)] [C4,C04,PO2,PO11] (b) Johnson counter is a common type of a shift register counter. Figure 4 shows a 4-bit Johnson counter logic diagram. Analyze the logic diagram and produce the sequence of 4-bit Johnson counter in table form. Assume that the initial condition of all Q is 0. [PembilangJohnson adalah sejenis pembilang daftar anjak yang umum. Rajah 4 menunjukkan gambarajah pembilang logik 4-bit Johnson. Analisa rajah logik dan hasilkan urutan pembilang logik 4-bit Johnson dalam bentuk jadual. Andaikan keadaan awal semua Q adalah 0.] Figure 4 [Rajah 4] [8 marks/markah] [C5,C04,PO2,PO11] (c) Construct an asynchronous counter logic diagram that have a modulus of NINE (9) with a straight binary sequence from 0000 until Assume that the clock of the J-K flip-flop is negative edge triggered. [Binakan satu gambarajah logik bagi pembilang tidak segerak yang mempunyai modulus SEMBILAN (9) dengan urutan binari dari 0000 sehingga 1000 secara berturutan. Andaikan jam daripada J-K flip-flop dipicu pada pinggir negatif.] [8 marks/markah]

8 -8- (EKT124) Question 5 [Soalan 5] [C5,C04,PO2,PO11] Design a counter with the irregular binary count sequence shown in the state diagram of Figure 5. Use J-K flip-flops with positive edge triggered clock. The J-K flip-flop transition table is given in Table 2. [Rekabentuk pembilang dengan urutan kiraan binari yang tidak teratur seperti yang ditunjukkan di dalam gambar rajah keadaan seperti Gambarajah 5.Gunakan J-K flip-flop dengan jam yang dipicu pada pinggir positif. Jadual peralihan J-K flip-flop adalah seperti Jadual 2.] [20 marks/markah] 0000 (0) 1101 (13) 0101 (5) 1010 (10) Figure 5 [Rajah 5] Table 2: J-K Flip-flop Transition Table [Jadual 2 :Jadual Transisi Flip-Flop] Output Transitions Flip-flop Inputs J K X X 1 0 X X 0 -oo0oo-

9 -9- (EKT124) Course Outcomes (COs) CO1 CO2 CO3 CO4 Ability to identify different numbering systems and to understand basic theory of binary system. Ability to apply method of minimizing Boolean functions for digital logic circuit. Ability to design and evaluate combinational logic circuit in terms of Boolean function. Ability to design and evaluate sequential logic circuit in terms of Boolean function. Program Outcomes (POs) PO 01 PO 02 PO 03 PO 04 PO 05 PO 06 PO 07 PO 08 PO 09 PO 10 PO 11 PO 12 Ability to acquire and apply knowledge of mathematics, science, engineering and an in-depth technical competence in computer engineering discipline to solve the complex engineering problem Ability to identify, formulate and solve complex engineering problems. Ability to design solutions for complex engineering problems and systems, components or processes to meet desired needs. Ability to conduct investigation into complex problems as well as to analyze and interpret data. Ability to use techniques, skills and modern engineering tools necessary for complex engineering practices so as to be easily adaptable to industrial needs. Understanding of the social, cultural, global and environmental responsibilities of a professional engineer. Ability to have entrepreneurship, the process of innovation and the need for environmental and sustainable development. Ability to understand the professional and ethical responsibilities and commitment to the community. Ability to function on multi-disciplinary teams. Ability to communicate effectively on complex engineering activities with the engineering community and with society at large A Recognition of the need for, and an ability to engage in life-long learning Demonstrate the understanding of project management and finance principles

10 -10- (EKT124) MATRIC NO.: PROGRAM: Appendix A [Appendiks A] D0 D1 D2 D3

UNIVERSITI MALAYSIA PERLIS. PLT106 Digital Electronics [Elektronik Digital]

UNIVERSITI MALAYSIA PERLIS. PLT106 Digital Electronics [Elektronik Digital] UNIVERSITI MALAYSIA PERLIS Peperiksaan Akhir Semester Kedua Sidang Akademik 2016/2017 Jun 2017 PLT106 Digital Electronics [Elektronik Digital] Masa : 3 jam Please make sure that this question paper has