Chapter 4. Logic Design

Transcription

1 Chapter 4 Logic Design 4.1 Introduction. In previous Chapter we studied gates and combinational circuits, which made by gates (AND, OR, NOT etc.). That can be represented by circuit diagram, truth table or by mapping of variables. That makes Digital Circuits. There are two types of digital circuits: Combinational and sequential, the progress in Integrated Circuit (IC) technology has made combination of gates circuit which is known as SSI (Small Scale Integration), MSI (Medium Scale Integration), functional level devices LSI (Large Scale Integration) and VLSI (Very Large Scale Integration) systems. In this chapter, we explain the combinational and sequential circuits, which are most useful for create flip-flops, counters and clock. 4.2 Combinational and Sequential Circuits: A combinational circuit is a connected arrangement of logic gates, Hardware component of computer system is built of several logic circuits, with a set of one or more output of a combinational circuit is a function of all the input to the circuit. The n binary input variables come from external sources, the m binary output variables go to an external destination and in between there is an inter connection of logic gates. This inter-connection of logical gates is a nothing but a combinational circuit as per figure-4.1. n Input Variables Combinational Circuit m Output Variables Figure 4.1 Block Diagram of Combinational Circuit Combinational circuit is analyzing with Boolean functions or a truth table. The design of combinational circuit starts from the problem solving, or output analysis and end with logic circuit diagrams. The procedures involve the following steps: 1. The Problem Finding 2. Think input and output of finding problem 3. Find variables and create truth table or create Boolean expression 4. Simplified Boolean expression 5. Draw logical Diagram 6. Create circuit Difference between, Combinational circuit and Sequential circuit. Combinational Circuit: 1. It contains no memory elements. 2. The present values of its outputs are determined solely by the present values of its inputs.

2 3. Its behavior is described by the set of output functions. Sequential Circuit: 1. It contains memory elements. 2. The present values of its outputs are determined by the present values of its inputs and its present state. 3. Its behavior is described by the set of next-state functions and the set of output function. Input Variable Combinational Circuit Output Variable Memory Figure 4.2 Block Diagram of Sequential Circuit 4.3 Sequential Logic: A sequential circuit defines its output as a function of both, its current inputs and its previous inputs. Therefore, the output depends on past inputs. To remember previous inputs, sequential circuits must have some sort of storage element. We typically refer to this storage element as a flip-flop. For example, Fig 4.3 if the output X is equal to 1 and the inverter creates output to 0, which turn back for upper inverter convert to 1 this situation is repeated indefinitely. Here, it is clear that one output is a complement of other. Figure 4.3 Cross Coupled Circuits As another example, in Fig 4.4 it is a simple sequential circuit of an XOR gate. The circuit has a single external input and single external output Figure 4.4 Simple XOR- Sequential circuit

3 4.4 Flip-Flops: The storage elements working in clocked sequential circuits are called flip-flops. A flip-flop is a storing one bit of information. It has two outputs, one for normal value and one for the complement value of the bit stored in it. Flipflop is also known as Bi-stable multi-vibrators of device. There are various types of flip-flops are varies among them is difference of input affect the binary state. Most common types of flip-flops are presented as SR Flip-flop, D-Flip-flops, JK Flip-flops, Edge Trigger Flip-flops, Master Slave Flip-flop, Binary counter ( T Flip-flops) etc. RS Flip-Flops: The simplest type of flip-flop is Set-Reset flip-flop; it has two inputs, which are complementary to each other, denoted by X and X. The S-R Latch can be constructed by cross-coupling the two NOR gates as shown in Fig 4.5. It has two states: X=0 and X=1. We shall use X n and X n+1 to denote the present state and the next state of the flip-flop, four possible inputs exist for the S-R flips-flop. The output for these four possible inputs are described as, 1. For S=0 and R=0, The X remains unchanged : Xn+1 =Xn 2. For S=0 and R=1, Except Xn, Xn+1 value will be 0 3. For S=1 and R=0, Except Xn, Xn+1 value will be 1 4. For S=R=1 Xn+1= X n+1 =0, which is not allowed. 1. The S-R flip-flop is a two state sequential circuit. From the logic function table of 4.5.B it is seen that next state Q for S=0 and R=0 is equal to the present state of the circuit; thus the next state of the circuit is a function of its present input and its present state. The operational behavior of logic function the S-R flip-flop is follows as the fig 4.5.A logic function table. 2. State transition diagram as Fig 4.6 indicate that if the present state of the circuit is X=0 and the present input is SR=10, the next state of circuit is X=1, is indicate by 10 drawn from state X=0 to state X=1. 3. The S-R flip flop is an asynchronous sequential circuit. Its state time depends only upon the delay of the two NOR gates.

4 4. The S-R flip-flop is a memory element. It can be used to store a binary digit, 0 or 1. To store a binary digit 0 and 1 we simply apply S=0 and R=1, and S=1 and R=0, respectively to the flip-flop. This information is available in memory till the power supply is on, once power supply is off data in the memory are lost. The S-R flip-flop also realized by cross coupling two NAND gates as shown in fig 4.7.The functional circuit and table of NAND gate S-R Flip flop of Fig 4.7.A. The functional circuit of NAND S-R gate will be identical to NOR S-R flip-flop for three allowable S-R inputs. S-R flip-flop is limited to one mode of operation, asynchronous. But in most desirable function of S-R is to input clock to the flip-flop so device operate simultaneously with all other in system. The wave form shown in Fig 4.8 is working of an active-low S-R latch.

5 4.5 Flip-Flops Design and Gated Flip flops: Flip flops are made by gates Fig. 4.5 show two NOR gate cross-coupled and in fig 4.7 two cross coupled NAND to create an RS Flip-flop. These both the circuits have two input R and S and two output X and X. Initially X=0 and S and R are in normal resting state, i.e. S=1 and R=1 since X is in 0 state, a negative pulse applied in R at time t1 can not produce any effect and X remains as 0. But negative pulse applied to s at time t2 bring X to a 1 state since, X is already equal to 1, A negative pulse applied to S at time t3 can not produce any effect and X remains at 1. The negative pulse applied to R at time t4, change the state of the latch and X become a 0. It means latch always remember the last input that was activated and will not change states until the opposite input is activated. When power is applied to circuit it is not possible to predict the starting state of a flip-flop output, where it s SET and RESET input are in their inactive states. There is just as much chance that the starting state will be a X=0 as X=1. It will depend on things like internal propagation delay, parasitic capacitance and external loading. There is one obvious state not managed by this particular flip-flop. What happens if both S and R are set to 1? This forces both X and X is 1, but it is invalid because, X = 1 = X is not obvious. This results in an unstable circuit. Therefore, this combination of inputs is not allowed in an SR flip-flop. We could modified the logic of SR flip flop to ensure that the illegal state never arises we simply modify the SR flip-flop as shown in Fig 4.9. This results in a JK flip-flop. JK flip-flops were named after the Texas Instruments engineer, Jack Kilby, who invented the integrated circuit in Another variant of the SR flip-flop is the D (data) flip-flop. A D flip-flop is a true representation of physical computer memory.

6 1. This sequential circuit stores one bit of information. If a 1 is asserted on the input line D, and the clock is pulsed, the output line Q becomes a If a 0 is asserted on the input line and the clock is pulsed, the output becomes Remember that output Q represents the current state of the circuit. Therefore, an output value of 1 means the circuit is currently storing a value of 1. Fig 4.10 illustrates the D flip-flop, lists its characteristic table, and reveals that the D flip-flop is actually a modified SR flip-flop. 4.6 Transfer Circuit: The RS flip flop is simple and basic circuit which is useful for various purposes, the operation of RS-flip flop is known as a transfer circuit. As per the circuit diagram Fig 4.11 show two set of flip flop X1, X2, X3 and Y1, Y2, Y3. The function of this configuration is to transfer the states, or contents, of Y1 in to X1, Y2 in to X2, and Y3 in to x3 upon the TRANSFER command which consist of a 1 on the TRANSFER bus. Here, Y1, Y2 and Y3 store some value and that will transfer to x1,x2 and x3 respectively, Y flip-flop are used to store other values of further calculations. Here, we assume that bus transfer 1 information and state of Y1=0 so Y1 =1, Y2=1 so Y2 =0, Y3=0 so Y3 =1. Transfer Y1 in to S1 X1, and Y1 in to R1 X1 transfer bus send 1 S1, 1 R1, so output of S1= 0 and Output of R1 = 1. Those are input of S and R flip flop, and value of Xn+1=0? Transfer Y2 in to S2 X2, and Y2 in to R2 X2 transfer bus send 1 S1, 1 R1, so output of S1= 1 and Output of R1 = 0. Those are input of S and R flip flop, and value of Xn+1=1? Transfer Y3 in to S3 X3, and Y3 in to R3 X3 transfer bus send 1 S3, 1 R3, so output of S3= 0 and Output of R3 = 1. Those are input of S and R flip flop, and value of Xn+1=0. This is the simple transfer operation are important to use registers, and the three Y1, Y2, Y3 are simple Y register and the three flip flops X1,X2,X3 are called register X. Here 1 on transfer bus sent information and y sent store bit to X is important concept.

7 NOTE: In reality, physical components have additional lines for power and for ground, as well as a clear line (which gives the ability to reset the entire register to all zeros). However, in this text, we are willing to leave those concepts to the computer engineers and focus on the actual digital logic present in these circuits. 4.7 Clocks Sequential logic is always dependent on other events (sequential circuit uses past inputs to determine present outputs, so event order is important). Sequential circuits are either Asynchronous or Synchronous. Synchronous: A sequential circuit is based on an equal state time or a state time defined by external means such as a clock is called a Synchronous sequential circuit. Asynchronous: A circuit whose state time depends exclusively upon the internal logic circuit delays is called an asynchronous sequential circuit. A clock used to order events, a clock is a circuit that produces a series of pulses with a exact pulse width and an interval between successive pulses. This interval is the clock cycle time. Clock speed is generally measured in megahertz (MHz), or millions of pulses per second. Common cycle times are from one to several hundred MHz. A clock is used to decide to update the state of the circuit (when, present inputs become past inputs?). It means current inputs to the circuit can only affect the store element at given, discrete instances of time. So in this chapter when we use sequential circuit word, it means, it is synchronous sequential circuit. Most sequential circuits are edge-triggered (as opposed to being level-triggered). This means they are allowed to change their states on either the rising or falling edge of the clock signal, as seen in Figure Clock signal are used to initiate flip-flop actions, clock input is include on most flipflops. Clock is marked as a small Triangle as shown in fig 4.12(a), It will be separately indicate as positive going clock edge 4.12(a) or negative going clocked are

8 indicated bubble before input the clock fig 4.12(b). Clock also indicate as a CL in block diagram instead of triangle. The flip-flops are operated according to the rules (Positive edge clock Fig 4.12a, c): 1. If S and R are 0s then flip flop doesn t change its state. 2. If the S=1 and R=0 then flip flop change the state and it goes to If S=0 and R=1 flip flop is cleared to the If S=1 and R=1 clock signal s positive going edge occurs. The flip-flops are operated according to the rules (Negative edge clock Fig 4.12b, d): 1. If S and R are 0s then flip flop doesn t change its state. 2. If the S=1 and R=0 then set the flip flop. 3. If S=0 and R=1 reset the flip flop. If S=1 and R=1 clock signal s negative going edge occurs. 4.8 Master Slave Flip-Flop The Master-Slave flip flop is basically two RS flip-flop connected serially. Here the first is the Master and the second is Slave. The configuration of RS-Master Slave flip-flop is shown in Figure 4.13a. The clock controls and inverted clock control the separation and connection of the circuit inputs from the inputs of the master and slave inputs from the master outputs. Here, the tr and tf are the transition time to change the status of clock from o to 1 and 1 to 0, respectively, as per timing diagram (Figure 4.13b). Different stages of transition. 1. As the clock changes state from 0 1, at point A the slave stage is disconnected from the master stage 2. At point B, the master is connected to the circuit input S and change S its state based on the inputs. 3. At point C, as the clock makes it transition from 1 0, the master stage is isolated from the inputs 4. At D, the slave inputs are connected to the outputs of the master stage. The slave flip-flop changes its state based on its inputs, and the slave stage is isolated from the master stage at A again. Thus, the master-slave configuration during each clock period one state changed, so avoiding the race conditions resulting from clock pulse width. Note: that the inputs to the master stage can change after the clock pulse while the slave stage is changing its state without affecting the operation of the master slave flip-flop, since these changes are not recognized by the master until the next clock pulse. Master slave flip-flops are especially useful when the input of a flip flop is a function of its own Consider the timing diagram of Figure 4.13c for a master slave flip-flop. Here, initially S=R=0. The flip-flop should not change its state during the clock pulse. However, a fault in the S line while clock is high sets the master stage, which in turn is transferred to the slave stage, resulting in an erroneous state. This is called one s catching problem and can be avoided by ensuring that all the input changes are complete and the inputs stable well before the leading edge of the clock. Edge-triggered flip-flops are preferred over master_ slave flip- flops because of the one s catching problem associated with the latter output.

9 4.9 Register Each flip-flop capable to store a single bit of information, Binary digit (a bit) can store n-bits in n flip-flops and it can store an n-bit word. Which is called a register and Group of register is called a memory. Register considered as circuit elements in their own right, registers have many applications including arithmetic operations, special types of counter and the simple storage of binary patterns. Some of the most common of these are shift register and binary counters Shift registers A register that is used to assemble and store information arriving from a serial source is called a shift register. Each output of a flip-flop is serially connected with the input of successive flip-flop, so that information can be passed between them and a common clock pulse is applied to all flip flops, clocking them synchronously, so the shift register is a synchronous sequential circuit. Obviously to be of use data must be able to be moved in and out of this structure, and this can be performed either serially or in parallel. When data is passing serially into the flip-flop at the end of the line and then fed along from flip-flop to flip-flop. In parallel mode data is input to all flip-flops

10 simultaneously. Fig shows a three-bit shift register constructed out of D-type flip-flops. Note how: the inputs and outputs of adjacent flip-flops are connected; all the clear and clock lines are joined together; and the gated preset arrangement allows the register to be parallel loaded with any preferred pattern. There are four possible modes of operation to entering and extracting data from shift register: 1. Serial In, Parallel Out (SIPO) 2. Serial In, Serial Out (SISO) 3. Parallel In, Serial Out (PISO) 4. Parallel In, Parallel Out (PIPO) Although some of these forms are of more use than others we will briefly look at how the shift register shown in Fig would be used in each of these four modes. SIPO 1. Clear all flip-flops by taking clear LOW. 2. Set clear and preset HIGH for normal flip-flop operation. 3. Apply serially data pass to the first flip-flop and clock at a rate synchronized to the data train so that one bit is entered for each clock trigger (for three bits of data for this shift register). 4. Data is now residing in the shift register and can be read out in parallel from all three flip-flops simultaneously using X0, X1 and X2. Example 6.4 Draw the contents of a four-bit shift register, at each clock pulse, which has the binary pattern 0110 serially loaded into it. Solution: This is shown in Fig X3 X2 X1 X0 Reset Clock Clock Clock Clock Figure bit register shift with binary pattern Note that in the SIPO shift register the data is transformed from being separated in time (temporally) and space (spatially), within the individual flip-flops.

11 SISO For the serial in, serial out shift register data is loaded same as SIPO but simply clocked out serially by X2. Obviously once loaded the data need not be accessed immediately and so can be stored. Also, it can be clocked out at a different rate, so providing a method of buffering data between two digital systems running at different clock speeds. Note that because a SISO can be operated with only two connections (to get the data in and out) its size is not constrained by necessary access to any other inputs and outputs. PISO 1. Clear all flip-flops by taking clear LOW. 2. Present the parallel data (a three-bit word) to the preset input lines Pr 2, Pr1, Pr0. 3. Write this data into the register by taking preset enable HIGH. This means the three-bit word is stored in the register, and can be read out as for the SISO using three clock pulses. Note that the PISO performs a spatial-to temporal conversion of data. PIPO The PIPO shift register takes the data parallel in and parallel outputs. for this reason there is no shifting of data within the circuit, rather it simply acts as three memory cells. The register discussed here can only shift data in one direction. Bidirectional shift registers are also available that can shift data in either direction. Note that one potential use of shift registers is for the multiplication or division by factors of two (by simply shifting data left or right respectively, see Section 2.5). Applications of shift registers: 1. Digital delay lines: If a single-bit data stream is entering serially into a shift register and then read out serially from the register's flip-flops for that reason delaying the data stream. For a clock period T then if the data is read from the nth stage of the register, the data is delayed by (n- 1) T. 2. Sequence generator: If a binary pattern is entering into a shift register it can then be output serially to produce a known binary sequence. If the output of that sequence is entering as input it can generate the same sequence indefinitely. When a SISO shift register is connected to itself this is usually referred to as a re-entrant shift register, dynamic shift register, ring buffer or circulating memory. Variations on this type of circuit are used for data encryption, error checking and for holding data during digital signal processing. Counters While flip-flop programmed as counters are widely used of different counting application in scientific instrument, industrial controls, computers, and communication equipments, as well as in many other areas. Counter is to remember how many clock pulses have been applied to the input; hence in the most basic sense counter are the memory system. They are used for counting

12 pulses, equipment operation sequencing, frequency division, and mathematical manipulation. Because of wide use of counters as well as their demands, they are available in market but some of the basic features of counters are circuitries, complexities, functional versatility, speed, power, and cost. It is also block of register so it may be synchronous or asynchronous counters, all flip flops in a synchronous counter are under the control of same clock pulse, whereas those in asynchronous counter are not. All counters are made up from a set of flip-flops in series. Binary Counter With the use of JK flip flop another useful sequential circuit is a binary counter, which goes through a predetermined sequence of states as the clock pulses. In a straight binary counter, these states reflect the binary number sequence. If we begin counting in binary: 0000, 0001, 0010, 0011,..., we can see that as the numbers increase, the low order Bit is complemented each time. Whenever it changes state from 1 to 0, the bit to the left is then complemented. Each of the other bits changes state from 0 to 1 when all bits to the right are equal to 1. Because of this concept of complementing states, our binary counter is best implemented using a JK flip-flop (recall that when J and K are both equal to 1, the flip-flop complements the present state). Instead of independent inputs to each flip-flop, there is a count enable line that runs to each flip-flop. The circuit counts only when the clock pulses and this count enable line is set to 1. If count enable is set to 0 and the

13 clock pulses, the circuit does not change state. You should examine Figure 3.24 very carefully, tracing the circuit with various inputs to make sure you understand how this circuit outputs the binary numbers from 0000 to You should also check to see which state the circuit enters if the current state is 1111 and the clock is pulsed BCD Counter A digital counter, or simply counter, is a semiconductor device that is used for counting the number of times that a digital event has occurred. The counter's output is indexed by one LSB every time the counter is clocked. A simple implementation of a 4-bit counter is shown in Figure 1, which consists of 4 stages of cascaded J-K flip-flops. This is a binary counter, since the output is in binary system format, i.e., only two digits are used to represent the count, i.e., '1' and '0'. With only 4 bits, it can only count up to '1111', or decimal number 15. As one can see from Figure 1, the J and K inputs of all the flip-flops are tied to '1', so that they will toggle between states every time they are clocked. Also, the output of each flip-flop in the counter is used to clock the next flip-flop. As a result, the succeeding flip-flop toggles between '1' and '0' at only half the frequency as the flip-flop before it. Figure 1. A Simple Ripple Counter Consisting of J-K Flip-flops Thus, in Figure 1's 4-bit example, the last flip-flop will only toggle after the first flip-flop has already toggled 8 times. This type of binary counter is known as a 'serial', 'ripple', or 'asynchronous' counter. The name 'asynchronous' comes from the fact that this counter's flip-flops are not being clocked at the same time. A 4-bit counter, which has 16 unique states that it can count through, is also called a modulo-16 counter, or mod-16 counter. By definition, a modulo-k or base-k counter is one that returns to its initial state after k cycles of the input waveform. A counter that has N flip-flops is a modulo 2N counter. An asynchronous counter has a serious drawback - its speed is limited by the cumulative propagation times of the cascaded flip-flops. A counter that has N flipflops, each of which has a propagation time t, must therefore wait for a duration equal to N x t before it can undergo another transition clocking. A better counter, therefore, is one whose flip-flops are clocked at the same time. Such a counter is known as a synchronous counter. A simple 4-bit synchronous counter is shown in Figure 2. Not all counters with N flip-flops are designed to go through all its 2N possible states of count. In fact, digital counters can be used to output decimal numbers by using logic gates to force them to reset when the output becomes equal to decimal 10. Counters used in this manner are said to be in binary-coded decimal (BCD).

14 Figure 2. A Simple Synchronous Counter Consisting of J-K Flip-flops and AND gates One of the most widely used representations of numerical data is the binary coded decimal (BCD) form in which each integer of a decimal number is represented by a 4-bit binary number It is particularly useful for the driving of display devices where a decimal output is desired. BCD usually refers to such coding in which the binary digits have their normal values, i.e., Sometimes it is written "8421 BCD" to clearly distinguish it from other binary codes such as the 4221 Code, but when BCD is used without qualification, the 8421 version is assumed. A BCD counter or decade counter can be constructed from a straight binary counter by terminating the "ripple-through" counting when the count reaches decimal 9 (binary 1001). Since the next toggle would set the two most significant bits, a NAND gate tied from those two outputs to the asynchronous clear line will start the count over after Counter Design A counter is first described by a state diagram, which is shows the sequence of states through which the counter advances when it is clocked. Figure 18 shows a state diagram of a 3-bit binary counter. Figure. State diagram of a 3-bit binary counter

15 The circuit has no inputs other than the clock pulse and no outputs other than its internal state (outputs are taken off each flip-flop in the counter). The next state of the counter depends entirely on its present state, and the state transition occurs every time the clock pulse occurs. Figure 19 shows the sequences of count after each clock pulse. Once the sequential circuit is defined by the state diagram, the next step is to obtain the next-state table, which is derived from the state diagram in Figure 18 and is shown in Table 15. Table 15. State table State Present Q2 Q1 Q Next State Q2 Q1 Q Since there are eight states, the number of flip-flops required would be three. Now we want to implement the counter design using JK flip-flops. Next step is to develop an excitation table from the state table, which is shown in Table 16. Table 16. Excitation table Output State Transitions Flip-flop inputs Present State Q2 Q1 Q Next State Q2 Q1 Q J2 K2 J1 K1 J0 K0 0 X 0 X 1 X 0 X 1 X X 1 0 X X 0 1 X 1 X X 1 X 1 X 0 0 X 1 X X 0 1 X X 1 X 0 X 0 1 X X 1 X 1 X 1 Now transfer the JK states of the flip-flop inputs from the excitation table to Karnaugh maps to derive a simplified Boolean expression for each flip-flop input. This is shown in Figure 20.

16 Figure 20. Karnaugh maps The 1s in the Karnaugh maps of Figure 20 are grouped with "don't cares" and the following expressions for the J and K inputs of each flip-flop are obtained: J0 = K0 = 1 J1 = K1 = Q0 J2 = K2 = Q1*Q0 The final step is to implement the combinational logic from the equations and connect the flip-flops to form the sequential circuit. The complete logic of a 3-bit binary counter is shown in Figure 21. Figure 21. Logic diagram of a 3-bit binary counter 4.12 Summary Exercise