K.T. Tim Cheng 07_dft, v Testability

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1 K.T. Tim Cheng 07_dft, v1.0 1 Testability Is concept that deals with costs associated with testing. Increase testability of a circuit Some test cost is being reduced Test application time Test generation time Fault simulation time Fault location time Test equipment cost K.T. Tim Cheng 07_dft, v1.0 1

2 Design for Testability Goal: keep test cost within a reasonable bound and ensure product quality exceeds desired level Definition - Design for Testability (DFT) refers to those design techniques that make test generation and testing cost-effective and ensure high-quality testing Some DFT methods: 1. Ad-hoc methods, design reviews, etc.. Scan, full and partial 3. Built-in self-test (BIST) 4. Boundary scan K.T. Tim Cheng 07_dft, v1.0 3 Important Factors of Testability Controllability: Measure the ease of controlling a line. Observability: Measure the ease of observing a line at a PO In general, DFT deals with ways for improving controllability and observability K.T. Tim Cheng 07_dft, v1.0 4

3 Costs Associated with DFT Pins Area/Yield Performance Design time There s no free lunch!! K.T. Tim Cheng 07_dft, v1.0 5 Ad Hoc Design For Testability Design guidelines Avoid asynchronous logic Avoid clock gating Insert test points Disadvantages High fault coverage not guaranteed Design iterations required K.T. Tim Cheng 07_dft, v

4 Test Point Insertion Employ test points to enhance Controllability Observability CP: Control Points Primary inputs used to enhance controllability OP: Observation Points Primary outputs used to enhance observability K.T. Tim Cheng 07_dft, v1.0 7 Example OP W X Y Z G1 G G3 G4 G5 G6 CP K.T. Tim Cheng 07_dft, v

5 Modifications 0 1 X X X Observe X 0 1 X X X X 0 X X 1 X X Control Points K.T. Tim Cheng 07_dft, v1.0 9 Problems Large number of I/O pins Add MUX s to reduce number of I/O pins Serially shifts control point values Long testing time K.T. Tim Cheng 07_dft, v

6 General Architecture Using Test Points Tied to Scan Registers S X Z X' Z' R1 R Control Observe K.T. Tim Cheng 07_dft, v Partitioning Using Transparent Registers B B R A E C A R E R C D Sin Sout R D K.T. Tim Cheng 07_dft, v

7 Scan Design Objective: To provide controllability and observability of internal state variables for testing Method: Add test mode control signal(s) to circuit Connect flip-flops to form shift register(s) in test mode Make inputs/outputs of the test shift registers controllable/observable K.T. Tim Cheng 07_dft, v The Scan Concept Primary Inputs Mode Swithch Combinational Logic Primary Outputs Scan in FF FF FF Scan out K.T. Tim Cheng 07_dft, v

8 Tests for Full-Scan Circuits Test generation for combinational logic only Denote the test vectors and response data based on PI, PO and state variables t i = t ii, t F i i = 1,,, n r i = r io, r F i Test application 1. Scan-in t if by setting the circuit in test mode. Apply t i I 3. Observe r i O 4. Set the circuit in functional mode and capture the response r if into scan register 5. Scan-out r if while scanning -in t i+1 F by setting the circuit in test mode 6. i i+1. Goto K.T. Tim Cheng 07_dft, v Scan Flip-Flop (SFF) D Master latch Slave latch TC Logic overhead Q SD MUX Q CK D flip-flop CK Master open Slave open t TC Normal mode, D selected Scan mode, SD selected t K.T. Tim Cheng 07_dft, v

9 Level-Sensitive Scan-Design Flip- Flop (LSSD-SFF) Master latch Slave latch D Q MCK Q SCK D flip-flop SD TCK Logic overhead MCK TCK MCK TCK Normal mode Scan mode SCK t K.T. Tim Cheng 07_dft, v Scan Design Rules Use only clocked D-type of flip-flops for all state variables. All flip-flop clocks must be controlled from primary inputs Clocks must not feed data inputs of flip-flops All asynchronous preset or clear of flip-flops must be disabled during scan The circuit cannot have bus contention during scan shifting Memory arrays must support write-lock during scan shifting. K.T. Tim Cheng 07_dft, v

10 Scan Rule Violation Example D1 D Flip Flop Q1 D D Flip Flop Q Clock Rule Violation D1 Clock D Q1 Flip Flop D D Flip Flop Q A Workaround K.T. Tim Cheng 07_dft, v Bus Contention: Normal Mode In normal system operation, it is assumed that there will not be bus contention. This assumption cannot be justified in the scanshift cycle for scan design and/or in the test sequence generated by ATPG. Therefore add disabling logic unless... RECOMMEND Fully Decoded Enables! d q clk qn dff data_1 d q clk qn dff data_ K.T. Tim Cheng 07_dft, v

11 Add Logic to Prevent Bus Contention in Scan Mode Automatically add real disabling logic scan_enable scan_in d q sclk clk qn csdff data_1 Inactive scan_in d q sclk clk qn csdff data_ Active K.T. Tim Cheng 07_dft, v1.0 Some Problems with Full Scan Area overhead Possible performance degradation Long test application time Not applicable to all designs (e.g. asynchronous designs, designs violating scan design rules) High power dissipation during testing K.T. Tim Cheng 07_dft, v1.0 11

12 Standard-Cell Design Layout Polycell Rows Routing Channels K.T. Tim Cheng 07_dft, v1.0 3 Layout of Scan Circuit Scan-Out MODSW Scan Flip-Flops Scan-in K.T. Tim Cheng 07_dft, v

13 Area Overhead Due to larger flip-flops Due to extra routing Performance Overhead Increase in delay of normal data paths includes Extra gate delay due to the multiplexer Extra capacitive loading delay due to scan wiring at the flip-flop output K.T. Tim Cheng 07_dft, v1.0 5 Issues for Multiple-Clock Design Clock skew might occur between different domains To minimize skew during scan shift, scan chains should be ordered s.t. all FFs in same clock domain are grouped together minimizing locations where clock skew can occur To completely avoid skew where the scan/clock domains cross, a lockup latch can be inserted. A B Y SI SE CLK1 CLK D SET SFF1 CLR Q Q D SET Q SFF CLR Q D L SET LL1 CLR Q Q SET D Q SO SFF3 CL R Q Lockup latch K.T. Tim Cheng 07_dft, v

14 Issues for MC Design Cont d To avoid clock skew during capture, pulse only one clock per pattern Resulting in high pattern count (long test time) Start load_unload shift Pattern 1 Pattern shift capture Start load_unload shift shift capture TClk1 TClk TClk3 TClk4 Optimization: Perform clock domain analysis to identify independent clock domains and/or clocks that can be safely pulsed simultaneously Pattern 1 Pattern Start load_unload Start shift shift capture shift load_unload shift capture Scan Enable TClk1 TClk TClk3 TClk4 K.T. Tim Cheng 07_dft, v1.0 7 General Issues of Scan Design Scan chain ordering To prevent skew during shift To minimize routing overhead Use placement info to determine a good ordering Balancing scan chains To minimize total test time Total scan cycles = (Scan patterns +1)*(Length of longest scan chains) # of scan chains is normally limited by the package (pins available to borrow or dedicate for scan) as well as the tester (channels available with memory depth that can handle scan vectors). K.T. Tim Cheng 07_dft, v

15 Partial Scan Basic idea Select a subset of flip-flops for scan lower overhead (area and speed) Relaxed design rules Cycle-breaking technique Cheng & Agrawal, IEEE Trans. on Computers, 1990 Select scan flip-flops to simplify sequential ATPG Timing-driven partial scan Jou & Cheng, ICCAD, Nov Allow optimization of area, timing and testability simultaneously K.T. Tim Cheng 07_dft, v1.0 9 What Makes ATPG Difficult? Poor controllability and observability of memory elements Structure-dependence Circuit N o. of g ates No. of flip-flop s Sequentia l d ep th Test gen. CPU sec. Fault coverag e TLC % Chip-A % Gate count, memory element count, and sequential depth do not explain the results Cycles in the circuit are mainly responsible for the test generation complexity K.T. Tim Cheng 07_dft, v

16 Directed Graph A Synchronous Sequential Circuit A circuit with eight flip-flops 3 D 1 L= L=1 L=1 Graph of the ciruit L=1 7 8 L= K.T. Tim Cheng 07_dft, v Test Length In A Sequential Ckt D: Sequential depth (the distance along the longest path in its graph) L: Maximum length of any cycle Test generation complexity of a cycle-free circuit (pipeline structure) is similar to that of a comb. ckt In a circuit with depth D, any single-sa fault can be tested by at most D+1 vectors The length of a test sequence ~ D L K.T. Tim Cheng 07_dft, v

17 Partial Scan For Cycle-free Structure Select minimal set of flip-flops to eliminate some or all cycles Self-loops (cycles of unit length ) are not broken to the scan overhead low The number of self-loops in real design can be quite large Limit the length of consecutive self-loop paths Long consecutive self-loop paths in large circuits may pose problems to sequential ATPG K.T. Tim Cheng 07_dft, v Example: Directed Graph Of A Synchronous Sequential Ckt A circuit with eight flip-flops 3 D 1 L= L=1 L=1 Graph of the ciruit L=1 7 8 L= K.T. Tim Cheng 07_dft, v

18 A Cycle-Breaking Algorithm Lee - Reddy algorithm (ICCAD 90) Begin graph reduction while (graph is not completely reduction) do begin heuristic node selection graph reduction end end K.T. Tim Cheng 07_dft, v basic operations (a) Source operation Graph Reduction V e 1e e 3 Remove V, e 1, e & e 3 (b) Sink operation e 1 e V Remove V, e 1, e & e 3 e 3 K.T. Tim Cheng 07_dft, v

19 (c) Self-loop operation e 1 V e 3 e e 4 Select V & remove V, e 1, e, e 3 & e 4 (d) Unit - in operation e 1 V e 5 V e 3 e 1 Merge V into V e V e 5 e 3 e e 4 e 4 K.T. Tim Cheng 07_dft, v (e) Unit - out operation e 1 V V e 3 e 1 Merge V into V e V e 3 e e 4 e 4 Heuristic Node Selection Selects node with maximum ( in_degree * out_degree) and removes it and its incident edges K.T. Tim Cheng 07_dft, v

20 Clocking Schemes for Partial Scan Circuits Scheme 1: Use a separate scan clock (dff+csff) scanpath sysclk scanclk Primary Inputs Combinational Logic } Combinational Logic Primary Outputs } K.T. Tim Cheng 07_dft, v Clocking Schemes for Partial Scan Circuits Scheme : Gate the system clock (dff+mdff) scan enable sysclk scan path Primary inputs Combinational Logic } Combinational Logic Primary outputs gated clock } non-scan cells K.T. Tim Cheng 07_dft, v

21 Partial Scan With a Separate Scan Clock or Gated Clock Purpose: Freeze the values in non-scan FFs during scan mode Disadvantage: Require multiple clock trees and cause extra clocksignal routing efforts Advantage: ATPG is easier: scan FFs are fully controllable & observable; can be treated as PI/PO for ATPG Test generation procedure: Scan FFs are removed and their input and output signals are added to the PO/PI lists A sequential ATPG is used for test generation The vector sequences are then converted into scan sequences: Each vector is preceded by a scan-in sequence to set the required values in scan FFs A scan-out sequence is added at the end of each vector sequence to observe the values captured in scan FFs K.T. Tim Cheng 07_dft, v Test Gen. Model - A Separate Scan Clock or Gated Clock I 1 I I n ScanIn PPI 1 PPI m PS 1 PS PS k O 1 O O n PPO 1 PPO m NS 1 NS NS k Time frame 1 system clock Time frame system clock system clock Time frame N K.T. Tim Cheng 07_dft, v

22 Experimental Results - TLC (A Toy Ckt w/ 355 Gates, 1 FFs) No. of Scan flipflops Max. cycle length Depth Test Gen. CPU sec. Fault sim. CPU sec. Fault Coverage No. of tests Total vectors % % % % % K.T. Tim Cheng 07_dft, v Test Length Statistics For TLC No. of Fault No. of Fault No. of Fault Without Scan Test lenght scan flip-flops Test lenght scan flip-flops Test lenght K.T. Tim Cheng 07_dft, v1.0 44

23 Clocking Schemes for Partial Scan Ckts Scheme 3: Use the system clock as a scan clock but without gating the clock* scan enable sysclk scan path Primary inputs Combinational Logic } Combinational Logic Primary outputs } non-scan cells Ref: Cheng, Single-Clock Partial Scan, IEEE Design and Test of Computers, June K.T. Tim Cheng 07_dft, v Using System Clock for Scan Operation The contents of the non-scan FFs may change during the scan operations ATPG needs to deal with it - test generation process is more complicated The fault coverage may be slightly lower than that of two-clock partial scan designs The total test length (including scan sequences) is usually shorter than that of two-clock PS designs K.T. Tim Cheng 07_dft, v

24 Test Generation Model - Clocking Scheme 3 Scan Shifting I 1 I I n ScanIn PPI 1 PPI m PS 1 PS PS k O 1 O O n PPO 1 PPO m NS 1 NS NS k Time frame 1 system clock Time frame Test Mode system clock system clock Time frame N Functional mode K.T. Tim Cheng 07_dft, v Test Generation Model - Clocking Scheme 3 Functional Justification I 1 I I n ScanIn SI 1 SI m PS 1 PS PS k O 1 O O n SO 1 SO m NS 1 NS NS k Time frame 1 system clock Time frame system clock Functional Mode system clock Time frame N K.T. Tim Cheng 07_dft, v

25 Area Growth vs.atpg Effort CPU Time Real-estate growth Test Generation Effort real-estate growth 0% 15% ATPG complexity 10% 5% non-scan only self loops remain feedback free circuit full scan K.T. Tim Cheng 07_dft, v Timing-Driven Partial Scan Aim at reducing both area overhead and performance degradation caused by test logic Timing analysis data can be used to guide scan flipflop selection Avoid selecting flip-flops on critical paths Can be incorporated in existing logic synthesis system to satisfy or trade-off design constraints in terms of area, performance and testability Testability Area Performance K.T. Tim Cheng 07_dft, v

26 Summary-Seq. ATPG & Partial Scan The combination of sequential ATPG and partial scan offers a cost-effective solution Cycle breaking is an effective heuristic for scan flipflop selection to simplify sequential ATPG Timing analysis data can be incorporated in the FF selection process to minimize performance degradation There are choices in clocking schemes Commercial tools are available to support this methodology K.T. Tim Cheng 07_dft, v Primary Reasons For Using IEEE JTAG Boundary Scan (1) To allow efficient testing of board interconnect () To facilitate isolation and testing of chips via the test bus (3) To reuse the chip level tests at the board level K.T. Tim Cheng 07_dft, v

27 IEEE JTAG Boundary Scan All primary inputs/outputs latched and connected in a shift register in test mode A test access port added with following signals: TMS Test mode signal TCK Test clock TDI Test data input TDO Test data output Test instructions & test data are sent to a chip over TDI Test results & status information are sent from a chip over TDO TAP controller is an FSM that decodes the state of the bus. K.T. Tim Cheng 07_dft, v Boundary Scan Architecture Boundary - Scan Path Scannable Register To other scannable registers Identity Bypass Instruction Control MUX TDI TMS TCK TDO Test Access Port (TAP) System Logic K.T. Tim Cheng 07_dft, v

28 Boundary Scan Cell IN SIN Shift DR 0 MUX 1 Clock DR QA Sout Update DR QB 0 MUX S 1 Mode control Out 1. Normal mode: Mode-control = 0. Scan mode: Shift DR = 1 First scan FF is driven by TDI Last scan FF drives TDO 3. Capture mode: Shift DR = 0 4. Update mode: Mode-control = 1 K.T. Tim Cheng 07_dft, v Board & Chip Test Modes (1) External test mode 1 Chip 1 Chip update operation capture operation () Sample Test Mode: The I/O data associated with a chip can be sampled during normal system operation. The sampled data can be scanned out while the board remains in normal operation. (3) Internal Test Mode Scan BIST K.T. Tim Cheng 07_dft, v

Chapter 8 Design for Testability

電機系 Chapter 8 Design for Testability 測試導向設計技術 2 Outline Introduction Ad-Hoc Approaches Full Scan Partial Scan 3 Design For Testability Definition Design For Testability (DFT) refers to those design techniques