FTF3021M 6M Full-Frame CCD Image Sensor

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Bernard Phelps
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1 IMAGE SENSORS FTF302M October 7, 2008 DASA Professional Imaging October 7, 2008

2 FTF302M Table of Contents. Description Architecture of the FTF302M Operating Conditions Absolute Maximum Ratings DC Voltage Settings AC Clock evel Conditions Timing Diagrams Performance Application Information Device andling Pin Configuration Package Information Order Codes October 7,

3 FTF302M Image format 36 x 24 mm 2 6M active pixels (3072 x 2044V) >94% fill factor Excellent anti-blooming & fast electronic shuttering igh quantum efficiency ow dark current and low fixed pattern noise orizontal and vertical binning Vertical sub-sampling igh linear dynamic range (>72dB) Mirrored and split readout Bottom amplifiers (W, X) optimized for high charge capacity Top amplifiers (Y, Z) optimized for high sensitivity and low noise igh speed readout up to 36 Mz per output RoS compliant The FTF302M is a monochrome full-frame CCD image sensor designed for medical and scientific applications, with very low dark current and a wide linear dynamic range of over 2 true bits. igh quantum efficiency is achieved by the use of the transparent membrane poly-silicon electrodes. Metal strapping allows high-speed vertical and horizontal transport. Two amplifiers optimized for high charge capacity at the bottom (W, X) and two amplifiers optimized for high sensitivity and low noise at the top (Y, Z) make the FTF302M the best fit for a wide range of high-end applications. A readout speed of 5 frames per second is possible when using only one output amplifier. By using dual outputs, the frame rate increases accordingly. On-chip charge binning offers significant increases in speed, signalto-noise ratio and sensitivity when reading out at lower resolution. The device structure is shown in figure.. Description Output register top Amp Z Amp Y Device structure 6 dummy lines + 6 black lines Optical size: mm () x mm (V) Chip size: mm () x 26,329 mm (V) Pixel size: 2 µm x 2 µm Active pixels: 3072 () x 2044(V) Total nr of pixels: 320 () x 2088 (V) Optical black pixels: eft: 20 Right : 20 Image section 2044 Overscan pixels: eft: 4 Right : 4 active 2088 Dummy register cells: eft: Right: lines lines Optical black lines: Top: 6 Bottom: 6 Dummy lines: Top: 6 Bottom: active pixels dummy lines + 6 black lines Amp W 320 Amp X Output register bottom Figure. Device structure. October 7,

4 FTF302M 2. Architecture of the FTF302M The optical centers of all pixels in the image section form a square grid. The charge is generated and integrated in this section. Readout registers are located below and above the image section. After the integration time, the image charge is shifted one line at a time to the upper or lower register. The left and the right half of each register can be controlled independently. This enables either single or split readout. During vertical transport, the C3 gates separate the cells in the register. The central C3 gates of the lower and upper registers are part of the left half of the sensor (W and Z quadrants respectively). Both registers can be used for vertical binning. Each register contains a summing gate at both ends that can be used for horizontal binning (see figure 2). The bottom register ends on both sides (W, X) with two identical amplifiers optimized for high charge capacity. The top register ends on both sides (Y, Z) with two identical amplifiers optimized for low noise and high sensitivity. IMAGE SECTION Image diagonal (active video only) Aspect ratio Active image width x height Pixel width x height Geometric fill factor Image clock pins Capacity of each clock phase Number of active lines Number of black reference lines Number of dummy black lines Total number of lines Number of active pixels per line Number of over scan (timing) pixels per line Number of black reference pixels per line Total number of pixels per line mm 3: x mm 2 2 x 2 µm 2 >94% 6 pins (A...) 38nF per pin (=2x8) 32 (=2x6) (=2x4) 40 (=2x20) 320 READOUT REGISTERS Output buffers on each corner Number of readout registers Number of dummy cells per register Number of register cells per register Readout register clock pins Capacity of each C-clock phase Overlap capacity between neighboring C-clocks Output register Summing Gates Capacity of each SG Reset Gate clock phases Capacity of each Three-stage source follower 2 22 (2x) 342 ( ) 6 pins per register (C...C3) 200 pf per pin 40pF 4 pins (SG), one per output 5pF 4 pins (), one per output 5pF October 7,

5 FTF302M SG OG C3 C2 C C3 C2 C C3 C2 C C3 C2 C C3 C3 C2 C C3 C3 C2 C C3 C3 C2 C C3 C2 C C3 C2 C C3 C2 C C3 SG C C3 C2 OG OUT_Z TG TG OUT_Y 6 dummy + 6 black A A A 2044 active A A A A A 6 dummy + 6 black A A OUT_W A A TG TG OG SG C3 C2 C C3 C2 C C3 C2 C C3 C2 C C3 C3 C2 C C3 C3 C2 C C3 C2 C C3 C3 C2 C C3 C2 C C3 C2 C C3 C2 C C3 SG OG OUT_X col col 24 + col K col K + 24 dummy pixels 20 black + 4 overscan 2032 image pixels 4 overscan + 20 black dummy pixels Figure 2. Detailed internal structure. October 7,

6 FTF302M 3. Operating Conditions When applicable the operating conditions are listed separately for W,X-output or Y,Z-output. 3. Absolute Maximum Ratings ABSOUTE MAXIMUM RATINGS MIN MAX UNIT GENERA: Storage temperature ºC Ambient temperature during operation ºC Voltage between any two gates V DC current through any clock (absolute value) µa OUT current (no short circuit protection) 0 +0 ma VOTAGES IN REATION TO :,, V, V All other pins (except ) V VOTAGES IN REATION TO :, V,, V All other pins (except ) V VOTAGES IN REATION TO : -5 0 V Voltage V ) During Charge reset it is allowed to exceed maximum rating levels. 3.2 DC Voltage Settings DC CONDITIONS, 2 W,X-OUTPUT MIN [V] TYPICA [V] MAX [V] MAX [ma] 3 N-substrate 20 adjusted 28 5 P-substrate Source Follower Drain Source Follower Source Current Source OG Output Gate Reset Drain All voltages in relation to ; typical values are according to test conditions. 2 Power-up sequence:,,,, all others. The difference between and should not exceed 5V during power up or down. 3 To set the voltage for optimal Vertical Anti-blooming (VAB), it should be adjustable between minimum and maximum values. October 7,

7 FTF302M DC CONDITIONS, 2 Y,Z-OUTPUT MIN [V] TYPICA [V] MAX [V] MAX [ma] 3 N-substrate 20 adjusted 28 5 P-substrate Source Follower Drain Source Follower Source Current Source OG Output Gate Reset Drain All voltages in relation to ; typical values are according to test conditions. 2 Power-up sequence:,,,, all others. The difference between and should not exceed 5V during power up or down. 3 To set the voltage for optimal Vertical Anti-blooming (VAB), it should be adjustable between minimum and maximum values. 3.3 AC Clock evel Conditions The following voltages should be applied for operating the sensor. A clocking scheme of 3 gates integrating and gate blocking should be used. AC COCK EVE CONDITIONS W,X-OUTPUT MIN TYPICA MAX UNIT IMAGE COCKS/ TRANSFER GATES 2 A-clock amplitude during integration and hold 8 9 V A-clock amplitude during vertical transport (duty cycle=5/8) 2 4 V A-clock low level V Charge reset (CR) level on A-clock V OUTPUT REGISTER COCKS: C-clock amplitude (duty cycle during hor. transport=3/6) V C-clock low level V Summing Gate (SG) amplitude V Summing Gate (SG) low level V OTER COCKS: Reset Gate () amplitude V Reset Gate () low level V Charge Reset (CR) pulse on V All voltages in relation to ; typical values are according to test conditions. 2 Transfer gate should be clocked as A during normal transport or held low during a line shift to sub-sample image. 3 Charge Reset can be achieved in two ways of which the first method is preferred: A. The typical A-clock low level is applied to all image clocks for proper CR, an additional Charge Reset pulse on is required B. The minimum CR level is applied to all image clocks simultaneously. October 7,

8 FTF302M AC COCK EVE CONDITIONS Y,Z-OUTPUT MIN TYPICA MAX UNIT IMAGE COCKS/ TRANSFER GATES 2 A-clock amplitude during integration and hold 8 8 V A-clock amplitude during vertical transport (duty cycle=5/8) 4 V A-clock low level V Charge reset (CR) level on A-clock V OUTPUT REGISTER COCKS: C-clock amplitude (duty cycle during hor. transport=3/6) V C-clock low level V Summing Gate (SG) amplitude V Summing Gate (SG) low level V OTER COCKS: Reset Gate () amplitude V Reset Gate () low level V Charge Reset (CR) pulse on V All voltages in relation to ; typical values are according to test conditions. 2 Transfer gate should be clocked as A during normal transport or held low during a line shift to sub-sample image. 3 Charge Reset can be achieved in two ways of which the first method is preferred: A. The typical A-clock low level is applied to all image clocks for proper CR, an additional Charge Reset pulse on is required B. The minimum CR level is applied to all image clocks simultaneously. October 7,

9 FTF302M 3.4 Timing Diagrams AC CARACTERISTICS MIN TYPICA MAX UNIT orizontal frequency (/Tp) Mz Vertical frequency kz Charge Reset (CR) time ine time µs Rise and fall times: image clocks (A) ns register clocks (C) /8 Tp ns summing gate (SG) 5 /8 Tp ns reset gate () 3 /8 Tp ns TP= clock period 2 Duty cycle=50% integration 2088 image lines idle integration 6 dummy 6 black 2044 active lines 6 black 6 dummy CR SSC NS puls/cr Trig_in CR VA high TG/A REMARKS * CR is applied during the first line after the transition from to of Trig_in * CCD is integrating during high period of Trig_in * After readout sequence the timing will go into idle mode. Figure 3. Frame timing diagram. October 7,

10 FTF302M Sensor Output Active Pixels Pixelnumbers represent the beginning of the concerning pixel B 20 black dummy Active Pixels overscan SSC Falling edge of pixel 95 Rising edge of pixel us 344 VA high TG/A 2.50us 3.75us 62 5us us 3.75us us us 3.75us us REMARKS * Thorizontal = 95 * /25E6 = 76.6us * Vertical transport frequency = 00kz Figure 4. Vertical transport for W, X output. Dual output. Note: When outputs Y, Z are used the and clock pulses must be switched. October 7,

11 FTF302M Sensor Output Active Pixels B 20 4 black timing Pixelnumbers represent the beginning of the concerning pixel B 20 black dummy Active Pixels overscan SSC Falling edge of pixel 3475 Rising edge of pixel us 344 VA high TG/A 2.50us 3.75us 62 5us us 3.75us us 6.25us 3.75us us REMARKS * Thorizontal = 3475 * /25E6 = 39us * Vertical transport frequency = 00kz Figure 5. Vertical transport for W, X output. Single output. Note: When outputs Y, Z are used the and clock pulses must be switched October 7, 2008

12 FTF302M SSC SSC clocked with rising edge of C2 C3 C C2 SG SINGE OUTPUT dummy 20 black 4 overscan 3072 active 4 overscan 20 black DUA OUTPUT dummy 20 black 4 overscan 536 active SENSOR PIN SINGE OUTPUT eft SINGE OUTPUT Right DUA OUTPUT C C2 C3 CR C2RC3R C C2 C3 C C2 C3 C2 C C3 C2 C C3 C C2 C3 C2 C C3 C3 C C2 SG black Sensor output signal 40ns 20ns 3.33ns 26.67ns 6.67ns 25Mz Figure 6. orizontal read out. Single and Dual output. October 7,

13 FTF302M 4. Performance The test conditions for the performance characteristics are as follows: All values are measured using typical operating conditions. is adjusted as low as possible while maintaining proper vertical anti-blooming Sensor temperature=60 C (333K) orizontal transport frequency=25mz Vertical transport frequency=00kz Integration time=0ms The light source is a lamp of 3200K in conjunction with neutral density filters and a.7mm thick BG40 infrared cut-off filter. INEAR OPERATION W,X-OUTPUT MIN TYPICA MAX UNIT Charge Transfer Efficiency vertical Charge Transfer Efficiency horizontal % Image lag 0 0 % Resolution 42 lp/mm % Peak Quantum Efficiency 530 nm % IR filter 20 kel/lux.sec ow pass shading % Random Non-Uniformity (RNU) 3 2 % Charge Transfer Efficiency values are tested by evaluation and expressed as the value per gate transfer. 2 ow Pass Shading is defined as the ratio of the one-σ value of an 8x8 pixel blurred image (low-pass) to the mean signal value. 3 RNU is defined as the ratio of the one-σ value of the high pass image to the mean signal value at nominal light. INEAR OPERATION Y,Z-OUTPUT MIN TYPICA MAX UNIT Charge Transfer Efficiency vertical Charge Transfer Efficiency horizontal % Image lag 0 0 % Resolution 42 lp/mm % Peak Quantum Efficiency 530 nm % IR filter 20 kel/lux.sec ow pass shading % Random Non-Uniformity (RNU) 3 2 % Charge Transfer Efficiency values are tested by evaluation and expressed as the value per gate transfer. 2 ow Pass Shading is defined as the ratio of the one-σ value of an 8x8 pixel blurred image (low-pass) to the mean signal value. 3 RNU is defined as the ratio of the one-σ value of the high pass image to the mean signal value at nominal light. October 7,

14 FTF302M Quantum Efficiency (QE) as function of wavelength QE (%) Wavelength Figure 7. Quantum efficiency as function of wavelength. October 7,

15 FTF302M INEAR/SATURATION MIN TYPICA MAX UNIT USING OUTPUT W & X Full-well capacity saturation level (Qmax) 290 kel Full-well capacity linear operation (Qlin) kel inear dynamic range 76 db Charge handling capacity kel Overexposure 4 handling >200 x Qmax level USING OUTPUT Y & Z Full-well capacity saturation level (Qmax) 50 kel Full-well capacity linear operation (Qlin) 2 05 kel inear dynamic range 72 db Charge handling capacity kel Overexposure 4 handling >200 x Qmax level Qmax is determined from the low-pass filtered image. 2 The linear full-well capacity Qlin is calculated from linearity test (see dynamic range). The evaluation test guarantees 97% linearity. 3 Charge handling capacity is the largest charge packet that can be handled by the horizontal register. 4 Overexposure over entire area while maintaining good vertical anti-blooming (VAB). It is tested by measuring the dark line. October 7,

16 FTF302M OUTPUT BUFFERS BOTTOM (W, X) MIN TYPICA MAX UNIT Conversion factor 0 µv/el. Mutual conversion factor matching ( ACF) 0 µv/el. Supply current 4.5 ma Bandwidth (R load=3.3kω) 20 Mz Output impedance buffer (R load=3.3kω, C load=2pf) 300 Ω RMS readout noise over full bandwidth after CDS 38 el OUTPUT BUFFERS TOP (Y, Z) MIN TYPICA MAX UNIT Conversion factor 22 µv/el. Mutual conversion factor matching ( ACF) 0 2 µv/el. Supply current 4.5 ma Bandwidth (R load=3.3kω) 20 Mz Output impedance buffer (R load=3.3kω, C load=2pf) 300 Ω RMS readout noise over full bandwidth after CDS 25 el Matching of the two outputs of bottom or top is specified as ACF with respect to reference measured at the operating point (Q lin/2) DARK CONDITION MIN TYPICA MAX UNIT W,X-OUTPUT Dark current 20 C 6 20 pa/cm 2. Dark current 60 C pa/cm 2. Fixed Pattern Noise 60ºC el/s Y,Z-OUTPUT Dark current 20 C 6 20 pa/cm 2. Dark current 60 C pa/cm 2. Fixed Pattern Noise 60ºC el/s FPN is one-σ value of the high-pass image. 000 Dark Current (pa/cm2) Temp. ( o C) Dark current versus temperature Figure 8. Dark current versus temperature. October 7,

17 FTF302M 5. Application Information Current handling One of the purposes of is to drain the holes that are generated during exposure of the sensor to light. Free electrons are either transported to the V connection and, if excessive (from overexposure), free electrons are drained to. No current should flow into any connection of the sensor. During high overexposure a total current of 0 to 5mA through all connections together may be expected. The PNP emitter follower in the circuit diagram (figure 2) serves these current requirements. drains superfluous electrons as a result of overexposure. In other words, it only sinks current. During high overexposure, a total current of 0 to 5mA through all connections together may be expected. The NPN emitter follower in the circuit diagram meets these current requirements. The clamp circuit, consisting of the diode and electrolytic capacitor, enable the addition of a Charge Reset (CR) pulse on top of an otherwise stable voltage. To protect the CCD, the current resulting from this pulse should be limited. This can be accomplished by designing a pulse generator with a rather high output impedance. Decoupling of DC voltages All DC voltages (not, which has additional CR pulses as described above) should be decoupled with a 00nF decoupling capacitor. This capacitor must be mounted as close as possible to the sensor pin. Further noise reduction (by bandwidth limiting) is achieved by the resistors in the connections between the sensor and its voltage supplies. The electrons that build up the charge packets that will reach the floating diffusions only add up to a small current, which will float through V. Therefore, a large series resistor in the V connection may be used. Outputs To limit the on-chip power dissipation, the output buffers are designed with open source outputs. Outputs to be used should therefore be loaded with a current source or more simply with a resistance to GND. In order to prevent the output (which typically has an output impedance of about 400Ω) from bandwidth limitation as a result of capacitive loading, load the output with an emitter follower built from a high-frequency transistor. Mount the base of this transistor as close as possible to the sensor and keep the connection between the emitter and the next stage short. The CCD output buffer can easily be destroyed by ESD. By using this emitter follower, this danger is suppressed; do NOT reintroduce this danger by measuring directly on the output pin of the sensor with an oscilloscope probe. Instead, measure on the output of the emitter follower. Slew rate limitation is avoided by avoiding a too-small quiescent current in the emitter follower; about 0mA should do the job. The collector of the emitter follower should be uncoupled properly to suppress the Miller effect from the base-collector capacitance. A CCD output load resistor of 3.3kΩ typically results in a bandwidth of 20Mz. Device protection The output buffers of the FTF302M are likely to be damaged if rises above or at any time. This danger is most realistic during power-on or power-off of the camera. The voltage should always be lower than the voltage. Never exceed the maximum output current. This may damage the device permanently. The maximum output current should be limited to 0mA. Be especially aware that the output buffers of these image sensors are very sensitive to ESD damage. Because of the fact that our CCDs are built on an n-type substrate, we are dealing with some parasitic npn transistors. To avoid activation of these transistors during switch-on and switch-off of the camera, we recommend the application diagram of figure 2. Unused sections To reduce power consumption, the following steps can be taken. Connect unused output register pins (C...C3, SG, OG) and unused pins to zero Volts. Color processing (for color sensors) In order to guarantee true colors, always use an external IR filter type CM500(0)s, mm or similar. The cover glass itself is not an IR filter. More information Detailed application information is provided in the application note AN. October 7,

18 FTF302M From V-Driver V NS CR A TG From PPG SG C C2 C3 BAT74 35V u 47K NS_CR V 00n NS 00n NS_CR 00n V NS 5K6 28K8 0K 22K BC860C BAT74 BAT74 00n BAT74 NS V NS 00n CCD OUT BFR92 00n 00n 00n 00n 2K2 NS_CR NS_CR 90E 2K4 * OUTZ TG Z Z Z AZ AW W W W TG OUT OG OG SG SG C C C2 C3 C3 C2 C SG CCD image sensor C2 C3 C3 C2 C SG OG OG OUTY TG Y Y Y AY AX X X X TG OUT 00n 00n NS_CR 00n NS_CR 00n 00n TR2 NS NS V DRIVER 2K 00K VOG V NS_CR V VOG 00 47p 6n8 48K 2K 6K 2K 00K VOG 00K 00K 00K 00K 00n NS 00n 00n 00 47p TR 6n8 74ACT04 DRIVER 74ACT04 DRIVER 74ACT04 00K 00K * adjust resistor values to match the input voltage to the input voltage range of the front end Figure 9. Application diagram. October 7,

19 FTF302M 6. Device andling An image sensor is a MOS device that can be destroyed by electro-static discharge (ESD). Therefore, the device should be handled with care. Always store the device with short-circuiting clamps or on conductive foam. Always switch off all electric signals when inserting or removing the sensor into or from a camera (the ESD protection in the CCD image sensor process is less effective than the ESD protection of standard CMOS circuits). Being a high quality optical device, it is important that the cover glass remain undamaged. When handling the sensor, use finger cots. When cleaning the glass we recommend using ethanol. Use of other liquids is strongly discouraged: if the cleaning liquid evaporates too quickly, rubbing is likely to cause ESD damage. the cover glass and its coating can be damaged by other liquids. Rub the window carefully and slowly. Dry rubbing of the window may cause electro-static charges or scratches that can destroy the device. October 7,

20 FTF302M 7. Pin Configuration SYMBO FUTION PIN # W PIN # X PIN # Y PIN # Z n-substrate A U U0 A0 n-substrate C2 S2 S9 C9 n-substrate G M M0 G0 p-well U2 U9 A9 Source Follower Drain B2 T2 T9 B9 Source Follower Source D2 R2 R9 D9 Current Source C S S0 C0 OG Output Gate B3 T3 T8 B8 Reset Drain D R R0 D0 TG Transfer Gate (Phase ) A5 U5 U6 A6 A Image Clock (Phase ) B5 T5 T6 B6 Image Clock (Phase 2) U3 U8 A8 Image Clock (Phase 3) U4 U7 A7 Image Clock (Phase 4) B4 T4 T7 B7 C Register Clock (Phase ) F2 N2 N9 F9 C2 Register Clock (Phase 2) F N N0 F0 C3 Register Clock (Phase 3) G2 M2 M9 G9 SG Summing Gate E P P0 E0 Reset Gate E2 P2 P9 E9 OUT Output B T T0 B0 Not Connected J K K0 J0 Not Connected J2 K2 K9 J9 Not Connected 0 0 Not Connected The FTF302M is mounted in a Pin Grid Array (PGA) package with 96 pins in a 20x5 grid of x 40.00mm 2. The position of pin A (quadrant W) is marked with a gold dot on top of the package. The image clock phases of all quadrants are internally connected (e.g. phase A: pins B5, T5, T6, B6 are internally connected). October 7,

21 FTF302M A B C D E F G J K M N P R S T U 0 OUT SG C2 C2 SG OUT 9 C C3 C3 C 8 OG OUT OUT OG 7 6 TG A A OG SG C C2 C3 C C2 C3 SG OG Z TOP Y A A TG 5 4 TG A A OG SG W C C2 C3 C C2 C3 X SG OG A A TG 3 OG OUT OUT OG 2 C C3 C3 C OUT SG C2 C2 SG OUT DOT ON TOP OF CCD INDICATES OCATION OF PIN A Figure 0. Pin configuration (top view). October 7,

22 20± ±0.20 DASA Professional Imaging FTF302M 8. Package Information Package information IMAGE SENSOR COVER GASS EPOXY GUE Top cover glass to top image sensor 2.4 ±0.25 Image sensor - bottom package.8 ±0.5 Image sensor - cover glass.3 ±0.20 Cover glass.0 ±0.05 Image sensor A TOP VIEW 40±0.40.4/00 INDEX MARK PIN 26.35± ±0.53 COVER GASS.27± ±0.5 STAND-OFF PIN (2.54) 0.46±0.05 BOTTOM VIEW 48.26±0.27 A is the center of the image area. Position of A: ± 0.5 to left edge of package ± 0.5 to upper edge of package.8 ± 0.5 to bottom of package Angle of rotation: less than ± Sensor flatness: < 30 µm (P-V) Cover glass: oya CG Thickness of cover glass: ± 0.05 Refractive index: n d =.53 Double sided AR coating < % ( nm) reflection All drawing units are in mm Figure 4 - Mechanical drawing of the PGA package Figure. Mechanical drawing of the PGA package. October 7,

23 9. Order Codes The CCD image sensor can be ordered in a specific quality grade. The grading is defined with the maximum amount of pixel defects, column defects, row defects and cluster defects, in both illuminated and non-illuminated conditions. For detailed grading information, please contact your local DASA representative. FTF302M sensors Description Quality Grade Order Code FTF302M/TG Test grade FTF302M/EG Economy grade FTF302M/IG Industrial grade FTF302M/G igh grade For More Information For more detailed information on this and other products, contact your local rep or visit our web site at DASA Professional Imaging Sales Department igh Tech Campus AE Eindhoven The Netherlands Tel: Fax: sales.sensors@dalsa.com This information is subject to change without notice. October 7,

FTT1010-M Philips Semiconductors

FTT1010-M Philips Semiconductors IMAGE SENSORS FTTM 999 September File under Image Sensors Philips Semiconductors TRAD FTTM inch optical format M active pixels ( x ) Progressive scan Excellent antiblooming ariable electronic shuttering