CprE 281: Digital Logic
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1 CprE 28: Digital Logic Instructor: Alexander Stoytchev
2 T Flip-Flops & JK Flip-Flops CprE 28: Digital Logic Iowa State University, Ames, IA Copyright Alexander Stoytchev
3 Administrative Stuff Homework 8 is due next Monday. The second midterm exam is next Friday.
4 Midterm Exam #2 Administrative Stuff When: Friday October 4pm. Where: This classroom What: Chapters, 2, 3, 4 and The exam will be open book and open notes (you can bring up to 3 pages of handwritten notes).
5 Midterm 2: Format The exam will be out of 30 points You need 95 points to get an A for this exam It will be great if you can score more than 00 points. but you can t roll over your extra points L
6 Midterm 2: Topics Binary Numbers and Hexadecimal Numbers s complement and 2 s complement representation Addition and subtraction of binary numbers Circuits for adders and fast adders Single and Double precision IEEE floating point formats Converting a real number to the IEEE format Converting a floating point number to base 0 Multiplexers (circuits and function) Synthesis of logic functions using multiplexers Shannon s Expansion Theorem
7 Midterm 2: Topics Decoders (circuits and function) Demultiplexers Encoders (binary and priority) Code Converters K-maps for 2, 3, and 4 variables Synthesis of logic circuits using adders, multiplexers, encoders, decoders, and basic logic gates Synthesis of logic circuits given constraints on the available building blocks that you can use Latches (circuits, behavior, timing diagrams) Flip-Flops (circuits, behavior, timing diagrams) Registers and Register Files
8 T Flip-Flop
9 Motivation A slight modification of the D flip-flop that can be used for some nice applications. In this case, T stands for Toggle.
10 T Flip-Flop [ Figure 5.5a from the textbook ]
11 T Flip-Flop Positive-edge-triggered D Flip-Flop [ Figure 5.5a from the textbook ]
12 T Flip-Flop What is this? [ Figure 5.5a from the textbook ]
13 What is this? T D
14 It is a 2-to- Multiplexer T T D D
15 What is this? T D + =?
16 It is a T Flip-Flop T 0 Clock D
17 It is a T Flip-Flop T 0 Clock D Note that the two inputs to the multiplexer are inverses of each other.
18 Another Way to Draw This T 0 Clock D
19 Another Way to Draw This T 0 Clock D What is this?
20 What is this? T D
21 What is this? T D D = T + T
22 It is an XOR T D D = + T
23 It is an XOR T D D = + T
24 What is this? + =?
25 It is a T Flip-Flop too T D Clock
26 It is a T Flip-Flop too T D T D Clock
27 It is a T Flip-Flop too T D T D Clock
28 T Flip-Flop (how it works) If T=0 then it stays in its current state If T= then it reverses its current state In other words the circuit toggles its state when T=. This is why it is called T flip-flop.
29 T Flip-Flop (circuit and truth table) [ Figure 5.5a,b from the textbook ]
30 T Flip-Flop (circuit and graphical symbol) [ Figure 5.5a,c from the textbook ]
31 T Flip-Flop (Timing Diagram) [ Figure 5.5d from the textbook ]
32 T Flip-Flop (Timing Diagram) Decision Point [ Figure 5.5d from the textbook ]
33 T Flip-Flop (Timing Diagram) [ Figure 5.5d from the textbook ]
34 T Flip-Flop (Timing Diagram) [ Figure 5.5d from the textbook ]
35 T Flip-Flop (Timing Diagram) [ Figure 5.5d from the textbook ]
36 JK Flip-Flop
37 JK Flip-Flop D = J + K [ Figure 5.6a from the textbook ]
38 JK Flip-Flop J D K Clock (a) Circuit J K ( t + ) ( t) 0 Hold Reset J 0 ( t) Set Toggle K (b) Truth table (c) Graphical symbol [ Figure 5.6 from the textbook ]
39 JK Flip-Flop (how it works) A versatile circuit that can be used both as a SR flip-flop and as a T flip flop If J=0 and S =0 it stays in the same state Just like SR It can be set and reset J=S and K=R If J=K= then it behaves as a T flip-flop
40 JK Flip-Flop (timing diagram)
41 JK Flip-Flop (timing diagram)
42 JK Flip-Flop (timing diagram)
43 JK Flip-Flop (timing diagram)
44 Complete Wiring Diagrams
45 Positive-Edge-Triggered D Flip-Flop
46 Negative-Edge-Triggered D Flip-Flop
47 The Complete Wiring Diagram for a Positive-Edge-Triggered D Flip-Flop D Clock
48 The Complete Wiring Diagram for a Negative-Edge-Triggered D Flip-Flop D Clock
49 The Complete Wiring Diagram for a Negative-Edge-Triggered D Flip-Flop D Clock
50 Positive-Edge-Triggered T Flip-Flop T D Clock
51 Negative-Edge-Triggered T Flip-Flop T D Clock
52 The Complete Wiring Diagram for a Positive-Edge-Triggered D Flip-Flop T Clock
53 The Complete Wiring Diagram for a Negative-Edge-Triggered D Flip-Flop T Clock
54 Positive-Edge-Triggered JK Flip-Flop Clock J K D
55 Negative-Edge-Triggered JK Flip-Flop Clock J K D
56 The Complete Wiring Diagram for a Positive-Edge-Triggered JK Flip-Flop J K Clock
57 The Complete Wiring Diagram for a Negative-Edge-Triggered JK Flip-Flop J K Clock
58 uestions?
59 THE END
CprE 281: Digital Logic
CprE 281: igital Logic Instructor: Alexander Stoytchev http://www.ece.iastate.edu/~alexs/classes/ Registers CprE 281: igital Logic Iowa State University, Ames, IA Copyright Alexander Stoytchev Administrative
CprE 281: Digital Logic
CprE 281: igital Logic Instructor: Alexander Stoytchev http://www.ece.iastate.edu/~alexs/classes/ Registers CprE 281: igital Logic Iowa State University, Ames, IA Copyright Alexander Stoytchev Administrative
CprE 281: Digital Logic
CprE 281: igital Logic Instructor: Alexander Stoytchev http://www.ece.iastate.edu/~alexs/classes/ Registers CprE 281: igital Logic Iowa State University, Ames, IA Copyright Alexander Stoytchev Administrative
CprE 281: Digital Logic
CprE 28: Digital Logic Instructor: Alexander Stoytchev http://www.ece.iastate.edu/~alexs/classes/ Registers and Counters CprE 28: Digital Logic Iowa State University, Ames, IA Copyright Alexander Stoytchev
CprE 281: Digital Logic
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