LogiCORE IP Spartan-6 FPGA Triple-Rate SDI v1.0

Transcription

1 LogiCORE IP Spartan-6 FPGA Triple-Rate SDI v1.0 User Guide

2 Notice of Disclaimer The information disclosed to you hereunder (the Materials ) is provided solely for the selection and use of Xilinx products. To the maximum extent permitted by applicable law: (1) Materials are made available "AS IS" and with all faults, Xilinx hereby DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including negligence, or under any other theory of liability) for any loss or damage of any kind or nature related to, arising under, or in connection with, the Materials (including your use of the Materials), including for any direct, indirect, special, incidental, or consequential loss or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered as a result of any action brought by a third party) even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility of the same. Xilinx assumes no obligation to correct any errors contained in the Materials or to notify you of updates to the Materials or to product specifications. You may not reproduce, modify, distribute, or publicly display the Materials without prior written consent. Certain products are subject to the terms and conditions of the Limited Warranties which can be viewed at IP cores may be subject to warranty and support terms contained in a license issued to you by Xilinx. Xilinx products are not designed or intended to be fail-safe or for use in any application requiring fail-safe performance; you assume sole risk and liability for use of Xilinx products in Critical Applications: Copyright 2011 Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Zynq, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. All other trademarks are the property of their respective owners. Revision History The following table shows the revision history for this document. Date Version Revision 06/22/ Initial Xilinx release. Spartan-6 FPGA Triple-Rate SDI User Guide

3 Table of Contents Revision History Preface: About This Guide Additional Resources References List of Acronyms Chapter 1: Introduction About the Core Supported Tools and System Requirements Operating System Requirements Tools Technical Support Feedback Spartan-6 FPGA Triple-Rate SDI Core Documentation Chapter 2: Overview SD-SDI HD-SDI G-SDI Video Payload ID Ancillary Data Support Complete Triple-Rate SDI Interface Solution Chapter 3: Core Architecture Core Block Diagram Spartan-6 FPGA Triple-Rate SDI Core Top-Level Module Reference Clocks DRP Clock Shared DRP Clock Sharing Chapter 4: Triple-Rate SDI Receiver Operation Triple-Rate SDI Receiver Overview Bit Rate and Transport Format Detection Operation of the Triple-Rate SDI Receiver in the Various SDI Modes Triple-Rate SDI Receiver Clocking SD-SDI RX Operation HD-SDI RX Operation Spartan-6 FPGA Triple-Rate SDI User Guide 3

4 3G-SDI Level A RX Operation G-SDI Level B RX Operation Electrical Interface Other Triple-Rate SDI RX Design Considerations Dual Link HD-SDI Processing Embedded Audio and Other Ancillary Data SMPTE 352 Video Payload ID Packets SD-SDI EDH Error Detection SD-SDI Data Recovery Unit SD-SDI Clock Recovery Chapter 5: Triple-Rate SDI Transmitter Operation Triple-Rate SDI Transmitter Overview Operation of the Triple-Rate SDI Transmitter in the SDI Modes SD-SDI Transmitter Operation HD-SDI Transmitter Operation G-SDI Transmitter Operation Level A Mode Level B Mode Dual Link HD-SDI Transmitter Operation Summary of Triple-Rate TX Modes Triple-Rate TX Details ST 352 Packet Insertion Line Number Insertion CRC Generation and Insertion EDH Generation and Insertion Ancillary Data Insertion Reference Clocks and Reference Clock Switching Electrical Interface Chapter 6: Implementing the Core Timing Constraints Other Constraints SD-SDI DRU GTP Transceiver Wrapper Spartan-6 FPGA Triple-Rate SDI User Guide

5 Preface About This Guide Additional Resources References List of Acronyms This user guide describes the LogiCORE IP Spartan -6 FPGA Triple-Rate SDI core. This core implements triple-rate serial digital interface (SDI) receivers and transmitters in Spartan-6 devices. It supports SD-SDI, HD-SDI, and 3G-SDI (level A, level B-DL, and level B-DS) and dual link HD-SDI standards. For support resources such as Answers, Documentation, Downloads, and Forums, see the Xilinx Support website at: For a glossary of technical terms used in Xilinx documentation, see: For more information, see these documents at DS849: LogiCORE IP Spartan-6 FPGA Triple-Rate SDI Data Sheet UG386: Spartan-6 FPGA GTP Transceivers User Guide XAPP1014: Audio/Video Connectivity Solutions for Virtex-5 FPGAs XAPP1075: Implementing Triple-Rate SDI with Virtex-6 FPGA GTX Transceivers XAPP1076: Implementing Triple-Rate SDI with Spartan-6 FPGA GTP Transceivers The following table defines acronyms used in this document. Acronym Definition ANC AP ASSP CDR CML CRC Ancillary Active Picture Application-Specific Standard Product Clock Data Recovery Current Mode Logic Cyclic Redundancy Check Spartan-6 FPGA Triple-Rate SDI User Guide 5

6 Preface: About This Guide Acronym Definition DRU EAV EDH FF HANC HD HDL LVDS MMCM RX SAV SD SDI SMPTE TRS TX VPID Data Recovery Unit End of Active Video Error Detection and Handling Full Field Horizontal Ancillary High Definition Hardware Description Language Low-Voltage Differential Signalling Mixed-Mode Clock Manager Receiver Start of Active Video Standard Definition Serial Digital Interface Society of Motion Picture and Television Engineers Timing Reference Signal Transmitter Video Payload Identifier 6 Spartan-6 FPGA Triple-Rate SDI User Guide

7 Chapter 1 Introduction About the Core The triple-rate serial digital interface (SDI) supports the SMPTE SD-SDI, HD-SDI, and 3G-SDI standards. The SDI interface is widely used in professional broadcast video equipment. SDI interfaces are used in broadcast studios and video production centers to carry uncompressed digital video along with embedded ancillary data, such as multiple audio channels. The LogiCORE IP Spartan -6 FPGA Triple-Rate SDI core implements triple-rate SDI receivers and transmitters in Spartan-6 devices. It supports SD-SDI, HD-SDI, and 3G-SDI (level A, level B-DL, and level B-DS) and dual-link HD-SDI standards. The Spartan-6 FPGA Triple-Rate SDI core is compatible with the GTP transceivers in Spartan-6 devices. SDI interface solutions for other Xilinx FPGAs can be found at The Spartan-6 FPGA Triple-Rate SDI core is a CORE Generator IP software core. It does not require a license. It is provided in source code form in both Verilog and VHDL. Supported Tools and System Requirements Operating System Requirements For a list of system requirements, see the ISE Design Suite 13: Release Notes Guide. Tools The tools and their respective versions for the 13.2 release are: ISE software 13.2 Mentor Graphics ModelSim 6.6d Technical Support For technical support, go to Questions are routed to a team with expertise using the Spartan-6 FPGA Triple-Rate SDI core. Spartan-6 FPGA Triple-Rate SDI User Guide 7

8 Chapter 1: Introduction Feedback Xilinx welcomes comments and suggestions about the Spartan-6 FPGA Triple-Rate SDI core and the accompanying documentation. Spartan-6 FPGA Triple-Rate SDI Core Documentation For comments or suggestions about the core, submit a WebCase at support/clearexpress/websupport.htm. Be sure to include this information: Core name Core version number Explanation of your comments For comments or suggestions about the core documentation, submit a WebCase at Be sure to include this information: Document title Document number Page number(s) to which your comments refer Explanation of your comments 8 Spartan-6 FPGA Triple-Rate SDI User Guide

9 Chapter 2 Overview SD-SDI HD-SDI 3G-SDI The LogiCORE IP Spartan -6 FPGA Triple-Rate SDI core implements three main SMPTE interface standards: SD-SDI (SMPTE ST 259): SDTV Digital Signal/Data - Serial Digital Interface HD-SDI (SMPTE ST 292): 1.5 Gb/s Signal/Data Serial Interface 3G-SDI (SMPTE ST 424): 3 Gb/s Signal/Data Serial Interface In addition, two triple-rate SDI receivers or transmitters can be combined to implement an SMPTE ST 372 dual link 1.5 Gb/s digital interface. The Spartan-6 FPGA Triple-Rate SDI core supports the 270 Mb/s bit rate (level C) of the SD-SDI standard. This bit rate is too slow for the RX clock data recovery (CDR) circuit in the GTP receiver to receive, directly, so the GTP receiver is used to oversample the 270 Mb/s data stream, and a data recovery unit (DRU), implemented in the Spartan-6 FPGA Triple-Rate SDI core, is used to recover the data with a high degree of jitter tolerance. This DRU supports only 270 Mb/s SD-SDI. However, it is possible to use a more general-purpose DRU to receive any SD-SDI bit rate. Customers needing to do this should contact Xilinx technical support for more information. The Spartan-6 FPGA Triple-Rate SDI core fully supports the SMPTE RP 165 Error Detection and Handling (EDH) standard for the receive and transmit sections. Although the HD-SDI standard is called a 1.5 Gb/s interface, the bit rates supported by HD-SDI are Gb/s and 1.485/1.001 Gb/s. The Spartan-6 FPGA Triple-Rate SDI core fully supports both bit rates. The Triple-Rate SDI core also fully supports generation (TX side) and checking (RX side) of CRC values for each video line and the insertion (TX side) and capture (RX side) of line number values for each line. The 3G-SDI standard is called a 3 Gb/s interface, but the bit rates are 2.97 Gb/s and 2.97/1.001 Gb/s. The Spartan-6 FPGA Triple-Rate SDI core fully supports both of these bit rates. 3G-SDI supports several different mapping levels, described in the SMPTE ST 425 standard. These levels are called A, B-DL, and B-DS. The Triple-Rate SDI core supports all three levels. As with the HD-SDI standard, the Triple-Rate SDI core supports CRC generation and checking and line number insertion and capture for 3G-SDI. Spartan-6 FPGA Triple-Rate SDI User Guide 9

10 Chapter 2: Overview Video Payload ID Ancillary Data Support The Spartan-6 FPGA Triple-Rate SDI core implements an SMPTE ST 352 compliant video payload ID (VPID) ancillary data packet insertion capability for the transmitter that works in all SDI modes (SD-SDI, HD-SDI, 3G-SDI, and dual link HD-SDI). The receive side also detects and captures the four data bytes of ST 352 VPID packets. The Spartan-6 FPGA Triple-Rate SDI core allows the application to implement ancillary data packet insertion prior to transmission. While the core does not provide ancillary data packet insertion capability, it has the necessary datapaths to allow ancillary data packet insertion to be implemented by the application. On the receive side, all embedded ancillary data is preserved by the Triple-Rate SDI core s receiver section and is present in the SDI data streams output from the core. Applications can process the received SDI data streams to process the ancillary data as needed. Complete Triple-Rate SDI Interface Solution A complete triple-rate SDI interface is comprised of: A GTP transceiver The LogiCORE IP Spartan-6 FPGA Triple-Rate SDI core An industry-standard SDI cable driver (for TX) and SDI cable equalizer (for RX) GTP reference clock source(s) Figure 2-1 shows a high-level block diagram of an SDI receive/transmit interface using the Spartan-6 FPGA Triple-Rate SDI core. The Triple-Rate SDI core implements one triple-rate SDI receiver and one triple-rate SDI transmitter. If only a receiver or only a transmitter is needed by the application, the input ports for the unused half of the core can be tied to ground, and the output ports can be left unconnected. The synthesis tool optimizes the unused portion of the core out of the application. When both the receiver and transmitter sections of the Triple-Rate SDI core are used, the receiver and transmitter are completely independent. They can operate in different SDI modes and bit rates (receiving 3G-SDI at 2.97/1.001 Gb/s while transmitting SD-SDI at 270 Mb/s or HD-SDI at either bit rate, for example). The Spartan-6 FPGA Triple-Rate SDI core always supports all three SDI modes (SD-SDI, HD-SDI, and 3G-SDI). If only a subset of these modes is required by an application, the full Triple-Rate SDI core is still used Spartan-6 FPGA Triple-Rate SDI User Guide

11 Complete Triple-Rate SDI Interface Solution X-Ref Target - Figure 2-1 Figure 2-1: Overview of Triple-Rate SDI Interface Notes relevant to Figure 2-1: 1. The SDI cable equalizer and cable driver are external to the FPGA. 2. The optional ancillary (ANC) packet insertion function is not included with the Spartan-6 FPGA Triple-Rate SDI core. Spartan-6 FPGA Triple-Rate SDI User Guide 11

12 Chapter 2: Overview 12 Spartan-6 FPGA Triple-Rate SDI User Guide

13 Chapter 3 Core Architecture Core Block Diagram Figure 3-1 shows a detailed top-level block diagram of a complete triple-rate SDI receive/transmit interface implemented with the LogiCORE IP Spartan -6 FPGA Triple-Rate SDI core. Spartan-6 FPGA Triple-Rate SDI User Guide 13

14 Chapter 3: Core Architecture X-Ref Target - Figure 3-1 Figure 3-1: Triple-Rate SDI RX/TX Interface Detailed Block Diagram 14 Spartan-6 FPGA Triple-Rate SDI User Guide

15 Spartan-6 FPGA Triple-Rate SDI Core Top-Level Module Spartan-6 FPGA Triple-Rate SDI Core Top-Level Module The Spartan-6 FPGA Triple-Rate SDI core top-level module implements three main functions: Triple-rate SDI receiver Triple-rate SDI transmitter GTP transceiver control The GTP transceiver control function provides the necessary resets and other control for the GTP transceiver to initialize the transceiver and to dynamically change the GTP transceiver attributes to change the SDI mode in which the receiver and transmitter are operating. Table 3-1 describes the ports of the Triple-Rate SDI core's top-level module. Table 3-1: Spartan-6 FPGA Triple-Rate SDI Core Ports Port Name I/O Width Description Receive Ports transceiver_id In 1 rxpipeclk In 1 rx_rst In 1 Specifies which transceiver in the GTP tile is connected to this instance of the core. This port is used by the GTP control section to create resets and control the DRP. It must always be set correctly regardless of whether there is a secondary core or if this instance is primary or secondary. 0 = Transceiver 0 1 = Transceiver 1 This input is the receiver pipeline clock at 1/20th the serial bit rate. Connect it to rxusrclk2 of the core instance that sources the RX user clocks to the GTP transceiver. This synchronous reset input usually can be tied to ground because a reset is not required. After FPGA configuration, this module is in a fully operational mode and does not require a reset. Both rx_ce_sd and rx_din_rdy_3g must be High when rx_rst is High to completely reset the receiver. Spartan-6 FPGA Triple-Rate SDI User Guide 15

16 Chapter 3: Core Architecture Table 3-1: Spartan-6 FPGA Triple-Rate SDI Core Ports (Cont d) Port Name I/O Width Description rx_frame_en In 1 rx_mode_in In 2 rx_mode_en In 3 rx_mode Out 2 This input enables the SDI framer function. When this input is High, the framer automatically readjusts the output word alignment to match the alignment of each timing reference signal (TRS), EAV or SAV. Normally, this input is always High. However, if controlled properly, this input can be used to implement TRS alignment filtering. For example, if the nsp output is connected to the rx_frame_en input, the framer ignores a single misaligned TRS, keeping the existing word alignment until the new word alignment is confirmed by a second matching TRS. It is important to turn off any TRS filtering during the synchronous switching lines by driving the rx_frame_en input High on the synchronous switching lines. For a primary instance of the core, this port is the mode input from the secondary core. For a secondary core or when there is no secondary core, this input is not used. This port has unary bits to enable reception of each of the three SDI modes: Bit 0 enables HD-SDI mode Bit 1 enables SD-SDI mode Bit 2 enables 3G-SDI mode When a bit is High, the corresponding SDI mode is enabled. When a bit is Low, the receiver does not attempt to detect incoming SDI signals for that mode. Disabling unused SDI modes using these bits decreases the amount of time it takes for the receiver to lock to the incoming signal when it changes modes. This output port indicates the current SDI mode of the receiver: 00 = HD-SDI 01 = SD-SDI 10 = 3G-SDI When the receiver is not locked, the rx_mode port changes values as the receiver searches for the correct SDI mode. During this time, the rx_mode_locked output is Low. When the receiver detects the correct SDI mode, the rx_mode_locked output goes High Spartan-6 FPGA Triple-Rate SDI User Guide

17 Spartan-6 FPGA Triple-Rate SDI Core Top-Level Module Table 3-1: Spartan-6 FPGA Triple-Rate SDI Core Ports (Cont d) Port Name I/O Width Description rx_mode_hd rx_mode_sd rx_mode_3g Out 1 These three output ports are decoded versions of the rx_mode port. They are provided for convenience. Unlike the rx_mode port, which changes continuously as the receiver seeks to identify and lock to the incoming signal, these outputs are all forced Low when the receiver is not locked. The output matching the current SDI mode of the receiver is High when rx_mode_locked is High. rx_mode_locked Out 1 rx_bit_rate Out 1 rx_t_locked Out 1 rx_t_family Out 4 rx_t_rate Out 4 rx_t_scan Out 1 When this output is Low, the receiver is actively searching for the SDI mode that matches the input data stream. During this time, the rx_mode output port changes frequently. When the receiver locks to the correct SDI mode, the rx_mode_locked output goes High. This output port indicates which bit rate is being received in HD-SDI and 3G-SDI modes. This output is only valid when rx_mode_locked is High. HD-SDI mode: rx_bit_rate = 0: Bit rate = Gb/s rx_bit_rate = 1: Bit rate = 1.485/1.001 Gb/s 3G-SDI mode: rx_bit_rate = 0: Bit rate = 2.97 Gb/s rx_bit_rate = 1: Bit rate = 2.97/1.001 Gb/s This output is High when the transport detection function in the receiver has identified the transport mode of the SDI signal. This output indicates which family of video signals is being used as the transport on the SDI interface. This output is only valid when rx_t_locked is High. This port does not necessarily identify the video format of the picture being transported. It only identifies the transport characteristics. See Table 4-1, page 38 for the encoding of this port. This output indicates the frame rate of the transport. This is not necessarily the same as the frame rate of the actual picture. See Table 4-2, page 39 for the encoding of this port. This output is only valid when rx_t_locked is High. This output indicates whether the transport is interlaced (Low) or progressive (High). This is not necessarily the same as the scan mode of the actual picture. This output is only valid when rx_t_locked is High. Spartan-6 FPGA Triple-Rate SDI User Guide 17

18 Chapter 3: Core Architecture Table 3-1: Spartan-6 FPGA Triple-Rate SDI Core Ports (Cont d) Port Name I/O Width Description rx_level_b_3g Out 1 rx_ce_sd Out 1 rx_nsp Out 1 rx_line_a Out 11 rx_a_vpid Out 32 In 3G-SDI mode, this output is driven High when the input signal is level B and driven Low when the input signal is level A. This output is only valid when rx_mode_3g is High. This output is a clock enable for SD-SDI mode. It is asserted, on average, one cycle out of every 2.75 cycles of rxpipeclk in SD-SDI mode. The SD-SDI data stream on the rx_ds1a port and the RX video timing signals (rx_trs, rx_eav, and rx_sav) are only valid when rx_ce_sd is High in SD-SDI mode. In other SDI modes, rx_ce_sd is always High. When this output is High, it indicates that the framer has detected a TRS at a new word alignment. If rx_frame_en is High, this output is only asserted briefly. If rx_frame_en is Low, this output remains High until the framer is allowed to readjust to the new TRS alignment (by asserting rx_frame_en High during the occurrence of a TRS). The current line number captured from the LN words of the Y data stream is output on this port. This output is valid in HD-SDI and 3G-SDI modes, but not in SD-SDI mode. In 3G-SDI level B mode, the output value is the line number from the Y data stream of link A or HD-SDI signal 1. For any case where the interface line number is not the same as the picture line number, such as for 1080p 60 Hz carried on 3G-SDI level B or dual link HD-SDI, the output value is the interface line number, not the picture line number. All four user data bytes of the SMPTE 352 packet from data stream 1 are output on this port in this format: most-significant byte to least-significant byte: byte4, byte3, byte2, byte1. This output port is valid only when rx_a_vpid_valid is High. This port is potentially valid in any SDI mode, if there are SMPTE 352 packets embedded in the SDI signal. In 3G-SDI level A mode, the output data is the VPID data captured from data stream 1 (luma). In 3G-SDI level B mode, the output data is the VPID data captured from data stream 1 of link A (dual link streams,) or HD-SDI signal 1 (dual HD-SDI signals). rx_a_vpid_valid Out 1 This output is High when rx_a_vpid is valid Spartan-6 FPGA Triple-Rate SDI User Guide

19 Spartan-6 FPGA Triple-Rate SDI Core Top-Level Module Table 3-1: Spartan-6 FPGA Triple-Rate SDI Core Ports (Cont d) Port Name I/O Width Description rx_b_vpid Out 32 All four user data bytes of the SMPTE 352 packet from data stream 2 are output on this port in this format: most-significant byte to least-significant byte: byte4, byte3, byte2, byte1. This output is valid only in 3G-SDI mode and only when rx_b_vpid_valid is High. In 3G-SDI level A mode, the output data is the VPID data captured from data stream 2 (chroma). In 3G-SDI level B mode, the output data is the VPID data captured from data stream 1 of link B (dual link streams) or HD-SDI signal 2 (dual HD-SDI signals). rx_b_vpid_valid Out 1 This output is High when rx_b_vpid is valid. rx_crc_err_a Out 1 rx_ds1a Out 10 rx_ds2a Out 10 rx_eav Out 1 rx_sav Out 1 This output is asserted High for one sample period when a CRC error is detected on the previous video line. For 3G-SDI level B mode, this output indicates CRC errors on data stream 1 only. There is a second output called rx_crc_err_b that indicates CRC errors on data stream 2 for 3G-SDI level B mode. This output is not valid in SD-SDI mode. The recovered data stream 1 is output on this port. The contents of this data stream are dependent on the SDI mode: SD-SDI: Multiplexed Y/C data stream HD-SDI: Y data stream 3G-SDI level A: Data stream 1 3G-SDI level B-DL: Data stream 1 of link A 3G-SDI level B-DS: Y data stream of HD-SDI signal 1 The recovered data stream 2 is output on this port. The contents of this data stream are dependent on the SDI mode: SD-SDI: Not used HD-SDI: C data stream 3G-SDI level A: Data stream 2 3G-SDI level B-DL: Data stream 2 of link A 3G-SDI level B-DS: C data stream of HD-SDI signal 1 This output is asserted High for one sample time when the XYZ word of an EAV is present on the data stream output ports. This output is asserted High for one sample time when the XYZ word of an SAV is present on the data stream output ports. Spartan-6 FPGA Triple-Rate SDI User Guide 19

20 Chapter 3: Core Architecture Table 3-1: Spartan-6 FPGA Triple-Rate SDI Core Ports (Cont d) Port Name I/O Width Description rx_trs Out 1 rx_line_b Out 11 rx_dout_rdy_3g Out 2 rx_crc_err_b Out 1 rx_ds1b Out 10 rx_ds2b Out 10 rx_edh_errcnt_en In 16 rx_edh_clr_errcnt In 1 rx_edh_ap Out 1 rx_edh_ff Out 1 rx_edh_anc Out 1 This output is asserted High for four consecutive sample times when the four words of an EAV or SAV are output on the data stream ports. This output port is only valid in 3G-SDI level B mode. It outputs the line number for the Y data stream of link B or HD-SDI signal 2. For any case where the interface line number is not the same as the picture line number, the line number output on this port is the interface line number, not the picture line number. In 3G-SDI level B mode, the output data rate is MHz, but the rxpipeclk frequency is MHz. The rx_dout_rdy_3g output is asserted at a MHz rate in 3G-SDI level B mode. This output is always High in all other modes, allowing it to be used as a clock enable to downstream modules. This output is the CRC error indicator for link B or HD-SDI signal 2. The rx_crc_err_b output is asserted High for a single clock cycle when a CRC error is detected. This output is only used in 3G-SDI level B mode. The data stream output on this port is: 3G-SDI level B-DL: Data stream 1 of link B 3G-SDI level B-DS: Y data stream of HD-SDI signal 2 This output is only used in 3G-SDI level B mode. The data stream output on this port is: 3G-SDI level B-DL: Data stream 2 of link B 3G-SDI level B-DS: C data stream of HD-SDI signal 2 This input controls which EDH error conditions increment the rx_edh_errcnt counter. See Table 4-4, page 46 for more details. When High, this input clears the rx_ed_errcnt counter. This input port must be High during the same clock cycle when rx_ce_sd is also High to clear the error counter. This output is asserted High when the active picture CRC calculated for the previous field does not match the AP CRC value in the EDH packet. This output is asserted High when the full field CRC calculated for the previous field does not match the FF CRC value in the EDH packet. This output is asserted High when an ancillary data packet checksum error is detected Spartan-6 FPGA Triple-Rate SDI User Guide

21 Spartan-6 FPGA Triple-Rate SDI Core Top-Level Module Table 3-1: Spartan-6 FPGA Triple-Rate SDI Core Ports (Cont d) Port Name I/O Width Description rx_edh_ap_flags Out 5 rx_edh_ff_flags Out 5 rx_edh_anc_flags Out 5 rx_edh_packet_flags Out 4 rx_edh_errcnt Out 16 The active picture error flag bits from the most recently received EDH packet are output on this port. See Table 4-5, page 47 for more information. The full field error flag bits from the most recently received EDH packet are output on this port. See Table 4-5, page 47 for more information. The ancillary error flag bits from the most recently received EDH packet are output on this port. See Table 4-5, page 47 for more information. This port outputs four error flags related to the most recently received EDH packet. See Table 4-6, page 47 for more information. This port is the SD-SDI EDH error counter. It increments once per field when any of the error conditions enabled by the rx_edh_err_en port occurs during that field. Transmit Ports txpipeclk In 1 tx_rst In 1 tx_ce In 3 tx_din_rdy In 1 tx_mode0 In 2 This input is the transmitter pipeline clock at 1/20th the serial bit rate. Connect it to txusrclk2 of the core instance that sources the TX user clocks to the GTP transceiver. This port is a synchronous reset input. It resets the transmit section when High. To fully reset the transmitter, both tx_ce and tx_din_rdy must be High when tx_rst is High. The clock enable must be asserted at a 27 MHz rate for SD-SDI mode (with a mandatory 5/6/5/6 clock cycle cadence). For all other SDI modes, the clock enable is always High. Three identical copies of the clock enable signal must be provided on the three bits of this port. For SD-SDI, HD-SDI, and level A 3G-SDI modes, this input must be kept High at all times. For level B 3G-SDI mode, this input must be asserted every other clock cycle. This input port selects the transmitter SDI mode for GTP transceiver 0. If this instance is primary and there is an associated secondary core, both tx_mode0 and tx_mode1 must be connected. If this instance is secondary or there is no secondary core, only the mode for the transceiver to which this instance is connected needs to be driven. 00 = HD-SDI (including dual link HD-SDI) 01 = SD-SDI 10 = 3G-SDI 11 = Invalid Spartan-6 FPGA Triple-Rate SDI User Guide 21

22 Chapter 3: Core Architecture Table 3-1: Spartan-6 FPGA Triple-Rate SDI Core Ports (Cont d) Port Name I/O Width Description tx_mode1 In 2 tx_bit_rate In 1 tx_level_b_3g In 1 tx_insert_crc In 1 tx_insert_ln In 1 tx_insert_edh In 1 tx_insert_vpid In 1 This input port selects the transmitter SDI mode for GTP transceiver 1. If this instance is primary and there is an associated secondary core, both tx_mode0 and tx_mode1 must be connected. If this instance is secondary or there is no secondary core, only the mode for the transceiver to which this instance is connected needs to be driven. 00 = HD-SDI (including dual link HD-SDI) 01 = SD-SDI 10 = 3G-SDI 11 = Invalid This port indicates the bit rate for transmitter clocks. 0 = Divide by 1 bit rate 1 = Divide by bit rate In 3G-SDI mode, this input determines whether the module is configured for level A (level = Low) or for level B (level = High). In 3G-SDI mode, this input must be properly controlled to produce legal 3G-SDI data streams. When this input is High, the transmitter generates and inserts CRC values on each video line in HD-SDI and 3G-SDI modes. When this input is Low, CRC values are not generated and inserted. This input is ignored in SD-SDI mode. When this input is High, the transmitter inserts line numbers after the EAV in each video line. The line number must be supplied on the tx_line_a and tx_line_b input ports. This input is ignored in SD-SDI mode. When this input is High, the transmitter generates and inserts EDH packets in every field in SD-SDI mode. When this input is Low, EDH packets are not inserted. This input is ignored in HD-SDI and 3G-SDI modes. When this input is High, ST 352 packets are inserted into the data streams, otherwise the packets are not inserted. ST 352 packets are mandatory in 3G-SDI and dual link HD-SDI modes and optional in HD-SDI and SD-SDI modes Spartan-6 FPGA Triple-Rate SDI User Guide

23 Spartan-6 FPGA Triple-Rate SDI Core Top-Level Module Table 3-1: Spartan-6 FPGA Triple-Rate SDI Core Ports (Cont d) Port Name I/O Width Description tx_overwrite_vpid In 1 tx_video_a_y_in In 10 tx_video_a_c_in In 10 tx_video_b_y_in In 10 If this input is High, ST 352 packets already present in the data streams are overwritten. If this input is Low, existing ST 352 packets are not overwritten. When transporting ST 372 dual link data streams on a 3G-SDI level B interface, existing ST 352 packets in the data streams must be updated to indicate that the interface is 3G-SDI rather than HD-SDI mode. This module updates these packets only when overwrite is High. So, unless the ST 352 packets are being updated externally to the triple-rate SDI core, this input must be High when transmitting in 3G-SDI level B-DL mode. This is the data stream A Y input. The data on this port depends on the SDI mode: SD-SDI: The multiplexed Y/C data stream enters the module on this port. HD-SDI: The Y data stream enters the module on this port. 3G-SDI level A: Data stream 1, as defined by SMPTE 425, enters the module on this port. Dual link HD-SDI or 3G-SDI level B-DL: The Y data stream of link A enters the module on this port. 3G-SDI level B-DS: The Y data stream of HD-SDI signal 1 enters the module on this port. This is the data stream A C input. The data on this port depends on the SDI mode: SD-SDI: Unused. HD-SDI and 3G-SDI level A: The C data stream enters the module on this port. Dual link HD-SDI or 3G-SDI level B-DL: The C data stream of link A enters the module on this port. 3G-SDI level B-DS: The C data stream of HD-SDI signal 1 enters the module on this port. This is the data stream B Y input: The data stream on this port depends on the SDI mode: Dual link HD-SDI or 3G-SDI level B-DL: The Y data stream of link B enters the module on this port. 3G-SDI level B-DS: The Y data stream of HD-SDI signal 2 enters the module on this port. For other SDI modes, this input port is unused. Spartan-6 FPGA Triple-Rate SDI User Guide 23

24 Chapter 3: Core Architecture Table 3-1: Spartan-6 FPGA Triple-Rate SDI Core Ports (Cont d) Port Name I/O Width Description tx_video_b_c_in In 10 tx_line_a In 11 tx_line_b In 11 tx_vpid_byte1 In 8 tx_vpid_byte2 In 8 tx_vpid_byte3 In 8 This is the data stream B C input: The data stream on this port depends on the SDI mode: Dual link HD-SDI or 3G-SDI level B-DL: The C data stream of link B enters the module on this port. 3G-SDI level B-DS: The C data stream of HD-SDI signal 2 enters the module on this port. For other SDI modes, this input port is unused. The current line number must be provided to the module through this port if either ST 352 VPID packet insertion is enabled (tx_insert_vpid = High) or if HD-SDI and 3G-SDI line number insertion is enabled (tx_insert_ln = High). SD-SDI only uses 10-bit line numbers, so bit 10 of the port must be 0 in SD-SDI mode. In SD-SDI mode, this input is only used for ST 352 VPID packet insertion. If tx_insert_vpid is Low, this input port is ignored in SD-SDI mode. The line number must be valid at least one clock cycle before the start of the HANC space (by the XYZ word of the EAV) and must remain valid during the entire HANC interval. This input is the only line number input used for SD-SDI, HD-SDI, and 3G-SDI level A modes. For 3G-SDI level B mode, a second line number input port, tx_line_b, is also provided. For video formats where the picture line number is different from the transport line number, the value supplied on this port must be the transport line number. This second line number input port is used only for 3G-SDI level B mode. This additional line number port allows the two separate HD-SDI signals to be vertically unsynchronized in level B-DS mode. When using either 3G-SDI level B-DL or B-DS, this port must be given a valid line number input. This input port has the same timing and requirements described for tx_line_a. This value is inserted as the first user data word of the ST 352 packet. It must be valid during the entire HANC interval. This value is inserted as the second user data word of the ST 352 packet. It must be valid during the entire HANC interval. This value is inserted as the third user data word of the ST 352 packet. It must be valid during the entire HANC interval Spartan-6 FPGA Triple-Rate SDI User Guide

25 Spartan-6 FPGA Triple-Rate SDI Core Top-Level Module Table 3-1: Spartan-6 FPGA Triple-Rate SDI Core Ports (Cont d) Port Name I/O Width Description tx_vpid_byte4a In 8 tx_vpid_byte4b In 8 tx_vpid_line_f1 In 11 tx_vpid_line_f2 In 11 tx_vpid_line_f2_en In 1 This value is inserted as the fourth user data word of the ST 352 packet. This word is used for the ST 352 packets inserted into SD-SDI, HD-SDI, and 3G-SDI level A data streams. For 3G-SDI level B and dual link HD-SDI modes, this value is used for the ST 352 packet inserted into Y channel of link A only. This input must be valid during the entire HANC interval. This value is inserted as the fourth user data word of ST 352 packets inserted in the Y channel of link B for 3G-SDI level B and dual link HD-SDI modes only. This input value is not used for SD-SDI, HD-SDI, or 3G-SDI level A modes. This input must be valid during the entire HANC interval. The ST 352 packet is inserted in the HANC space of the line number specified by this input port. For interlaced video, this input port specifies a line number in field 1. For progressive video, this specifies the only line in the frame where the packet is inserted. The input value must be valid during the entire HANC interval. If tx_insert_vpid is Low, this input is ignored. For interlaced video, an ST 352 packet is inserted on the line number in field 2 indicated by this value. For progressive video, this input port must be disabled by holding the tx_vpid_line_f2_en port Low. The input value must be valid during the entire HANC interval. This input is ignored if either tx_insert_vpid or tx_vpid_line_f2_en is Low. This input controls whether or not ST 352 packets are inserted on the line indicated by line_f2. For interlaced video, this input must be High. For progressive video, this input must be Low. For progressive video transported on an interlaced transport, such as 1080p 60 Hz transported by either 3G-SDI level B-DL or dual link HD-SDI, ST 352 packets must be inserted into both fields of the interlaced transport, so this input must be High. This input must be valid during the entire HANC interval. This input is ignored if tx_insert_vpid is Low. Spartan-6 FPGA Triple-Rate SDI User Guide 25

26 Chapter 3: Core Architecture Table 3-1: Spartan-6 FPGA Triple-Rate SDI Core Ports (Cont d) Port Name I/O Width Description tx_ds1a_out Out 10 tx_ds2a_out Out 10 tx_ds1b_out Out 10 This is the link A data stream 1 output. The data stream output on this port contains ST 352 packets if tx_insert_vpid is High. If the application needs to insert ancillary data packets, they should be inserted into the data stream output on this port. The resulting data stream then should be supplied to the tx_ds1a_in port. The data on this port depends on the SDI mode: SD-SDI: Multiplexed Y/C data stream. HD-SDI: Y data stream. 3G-SDI level A: Data stream 1. Dual link HD-SDI or 3G-SDI level B-DL: Y data stream of link A. 3G-SDI level B-DS: Y data stream of HD-SDI signal 1. This is the link A data stream 2 output. The data stream output on this port contains ST 352 packets if tx_insert_vpid is High. If the application needs to insert ancillary data packets, they should be inserted into the data stream output on this port. The resulting data stream then should be supplied to the tx_ds2a_in port. The data on this port depends on the SDI mode: SD-SDI: Unused. HD-SDI: C data stream. 3G-SDI level A: Data stream 2. Dual link HD-SDI or 3G-SDI level B-DL: C data stream of link A. 3G-SDI level B-DS: C data stream of HD-SDI signal 1. This is the link B data stream 1 output. The data stream output on this port contains ST 352 packets if tx_insert_vpid is High. If the application needs to insert ancillary data packets, they should be inserted into the data stream output on this port. The resulting data stream then should be supplied to the tx_ds1b_in port. The data on this port depends on the SDI mode: Dual link HD-SDI or 3G-SDI level B-DL: Y data stream of link B. 3G-SDI level B-DS: Y data stream of HD-SDI signal 2. For other SDI modes, this input port is unused Spartan-6 FPGA Triple-Rate SDI User Guide

27 Spartan-6 FPGA Triple-Rate SDI Core Top-Level Module Table 3-1: Spartan-6 FPGA Triple-Rate SDI Core Ports (Cont d) Port Name I/O Width Description tx_ds2b_out Out 10 tx_use_dsin In 1 tx_ds1a_in In 10 tx_ds2a_in In 10 This is the data stream B C input: The data stream on this port depends on the SDI mode: Dual link HD-SDI or 3G-SDI level B-DL: the C data stream of link B enters the module on this port. 3G-SDI level B-DS: The C data stream of HD-SDI signal 2 enters the module on this port. For other SDI modes, this input port is unused. This input controls the source of the data streams sent by the transmitter. When this input is High, the sources of the transmitted data streams are the tx_ds1a_in, tx_ds2a_in, tx_ds1b_in, and tx_ds2b_in input ports. When this input is Low, the source of the transmitted data streams are internal to the core, coming directly from the video payload ID insertion function. When the application needs to insert ancillary data, the tx_use_dsin port is driven High to allow the application to modify the data streams and provide the modified data streams to the transmitter on the tx_dsxx_in ports. When no ancillary data insertion is required, the tx_use_dsin input is driven Low, and the tx_dsxx_in ports are ignored. This is the link A data stream 1 input. This port is ignored if tx_use_dsin is Low. If tx_use_dsin is High, this port supplied a data stream to be transmitted. The data stream supplied on this port depends on the SDI mode: SD-SDI: Multiplexed Y/C data stream. HD-SDI: Y data stream. 3G-SDI level A: Data stream 1. Dual link HD-SDI or 3G-SDI level B-DL: Y data stream of link A. 3G-SDI level B-DS: Y data stream of HD-SDI signal 1. This is the link A data stream 2 input. This port is ignored if tx_use_dsin is Low. If tx_use_dsin is High, this port supplied a data stream to be transmitted. The data stream supplied on this port depends on the SDI mode: SD-SDI: Unused. HD-SDI and 3G-SDI level A: The C data stream enters the module on this port. Dual link HD-SDI or 3G-SDI level B-DL: C data stream of link A. 3G-SDI level B-DS: C data stream of HD-SDI signal 1. Spartan-6 FPGA Triple-Rate SDI User Guide 27

28 Chapter 3: Core Architecture Table 3-1: Spartan-6 FPGA Triple-Rate SDI Core Ports (Cont d) Port Name I/O Width Description tx_ds1b_in In 10 tx_ds2b_in In 10 tx_ce_align_err Out 1 tx_slew Out 1 This is the link B data stream 1 input. This port is ignored if tx_use_dsin is Low. If tx_use_dsin is High, this port supplied a data stream to be transmitted. The data stream supplied on this port depends on the SDI mode: Dual link HD-SDI or 3G-SDI level B-DL: Y data stream of link B. 3G-SDI level B-DS: Y data stream of HD-SDI signal 2. For other SDI modes, this input port is unused. This is the link B data stream 2 input. This port is ignored if tx_use_dsin is Low. If tx_use_dsin is High, this port supplied a data stream to be transmitted. The data stream supplied on this port depends on the SDI mode: Dual link HD-SDI or 3G-SDI level B-DL: C data stream of link B. 3G-SDI level B-DS: C data stream of HD-SDI signal 2. For other SDI modes, this input port is unused. This output indicates problems with the 5/6/5/6 clock cycle cadence on the tx_ce clock enable in SD-SDI mode. In SD-SDI mode, the tx_ce signal must follow a regular 5/6/5/6 clock cycle cadence. If it does not, the SD-SDI bitstream is formed incorrectly. The tx_ce_align_err signal goes High if the cadence is incorrect. This port is only valid in SD-SDI mode. This output port can drive the slew rate control pin of the external SDI cable driver to correctly switch it between slow slew rate for SD-SDI and high slew rate for HD-SDI and 3G-SDI. GTP Transceiver Ports gtp_bufgtpclk In 2 These two inputs carry the output clocks from the GTP transceiver. The source is GTPCLKOUT from the GTP transceiver. This must be buffered through BUFIO2 components between the GTP transceiver and this input port. Bit 0 is the TX output clock derived by dividing the GTP REFCLK. It is used to produce TX user clocks. Bit 1 is the RX recovered clock. It is used to produce the RX user clocks Spartan-6 FPGA Triple-Rate SDI User Guide

29 Spartan-6 FPGA Triple-Rate SDI Core Top-Level Module Table 3-1: Spartan-6 FPGA Triple-Rate SDI Core Ports (Cont d) Port Name I/O Width Description gtp_rxusrclk Out 1 gtp_rxusrclk2 Out 1 gtp_txusrclk Out 1 gtp_txusrclk2 Out 1 gtp_rxreset Out 1 gtp_resetdone In 1 gtp_rxbufstatus2 In 1 gtp_rxcdrreset Out 1 gtp_rxbufreset Out 1 gtp_rxdata In 20 gtp_gtpreset_in In 1 Output user clock at 1/10th the RX serial bit rate. This is derived from the gtp_bufgtpclk[1] input and is buffered with a BUFG inside the core. The nominal frequency is 297 MHz for 3G-SDI, and MHz for HD-SDI and SD-SDI. This is used to drive the RXUSRCLK input of the GTP transceiver. Output user clock at 1/20th the RX serial bit rate. This is derived from the gtp_bufgtpclk[1] input and is buffered with a BUFG inside the core. The nominal frequency is 148 MHz for 3G-SDI, and MHz for HD-SDI and SD-SDI. This is used to drive the RXUSRCLK2 input of the GTP transceiver, and also as the pipeline clock for processing parallel RX data. Output user clock at 1/10th the TX serial bit rate. This is derived from the gtp_bufgtpclk[0] input and is buffered with a BUFG inside the core. The nominal frequency is 297 MHz for 3G-SDI and SD-SDI, and MHz for HD-SDI. This is used to drive the TXUSRCLK input of the GTP transceiver. Output user clock at 1/20th the TX serial bit rate. This is derived from the gtp_bufgtpclk[0] input and is buffered with a BUFG inside the core. The nominal frequency is 148 MHz for 3G-SDI and SD-SDI, and MHz for HD-SDI. This is used to drive the TXUSRCLK2 input of the GTP transceiver, and also as the pipeline clock for processing parallel TX data. Connect this port to the RXPRESET_IN port of the GTP transceiver. Connect this port to the RESETDONE_OUT port of the GTP transceiver. Connect this port to bit 2 of the RXBUFSTATUS_OUT port of the GTP transceiver. Connect this port to the RXCDRRESET_IN port of the GTP transceiver. Connect this port to the RXBUFRESET_IN port of the GTP transceiver. Connect this port to the RXDATA_OUT port of the GTP transceiver. Asserting this input High causes the gtp_gtpreset port to be asserted High, resetting the GTP transmitter. This input should be kept Low for normal operation. Spartan-6 FPGA Triple-Rate SDI User Guide 29

30 Chapter 3: Core Architecture Table 3-1: Spartan-6 FPGA Triple-Rate SDI Core Ports (Cont d) Port Name I/O Width Description gtp_gtpreset Out 1 gtp_txbufstatus1 In 1 gtp_txplllkdet In 1 gtp_txreset Out 1 gtp_txdata Out 20 gtp_drpclk In 1 gtp_drpdo In 16 gtp_drdy In 1 gtp_daddr Out 8 gtp_di Out 16 gtp_den Out 1 gtp_dwe Out 1 rxusrclk_locked Out 1 txusrclk_locked Out 1 Connect this port to the GTPRESET_IN port of the GTP transceiver. Connect this port to bit 1 of the TXBUFSTATUS_OUT port of the GTP transceiver. Connect this port to the PLLLKDET_OUT port of the GTP transceiver. Connect this port to the TXRESET_IN port of the GTP transceiver. Connect this port to the TXDATA_IN port of the GTP transceiver. This clock input must be driven by the same clock that drives the DCLK port of the GTP transceiver. This clock must meet the DRP clock frequency requirements listed in DS162, Spartan-6 FPGA Data Sheet: DC and Switching Characteristics. Because the drpclk is also used internally by the receiver SDI bit rate detector, the drpclk frequency must be a fixed-frequency clock. It must not change frequencies when the SDI bit rate changes. Also, the frequency of this clock must match the value of the DRPCLK_FREQ parameter/generic of the Triple-Rate SDI core. Connect this port to the DRPDO_OUT port of the GTP transceiver. Connect this port to the DRDY_OUT port of the GTP transceiver. Connect this port to the DADDR_IN port of the GTP transceiver. Connect this port to the DI_IN port of the GTP transceiver. Connect this port to the DEN_IN port of the GTP transceiver. Connect this port to the DWE_IN port of the GTP transceiver. This output indicates the lock status of the PLL used to create the RX user clocks gtp_rxusrclk and gtp_rxusrclk2. 0 = Unlocked 1 = Locked This output indicates the lock status of the PLL used to create the TX user clocks gtp_txusrclk and gtp_txusrclk2. 0 = Unlocked 1 = Locked 30 Spartan-6 FPGA Triple-Rate SDI User Guide