AN 776: Intel Arria 10 UHD Video Reference Design

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1 AN 776: Intel Arria 10 UHD Video Reference Design Subscribe Send Feedback Latest document on the web: PDF HTML

2 Contents Contents 1 Intel Arria 10 UHD Video Reference Design Intel Arria 10 UHD Video Reference Design Features Intel Arria 10 UHD Reference Design Getting Started Hardware and Software Requirements for the Intel Arria 10 UHD Video Reference Design Downloading and Installing the Intel Arria 10 UHD Reference Design Connecting up the Intel Arria 10 UHD Reference Design Hardware Compiling the Intel Arria 10 UHD Reference Design Running the Intel Arria 10 UHD Video Reference Design on the Hardware Compiling the Intel Arria 10 UHD Reference Design Software Intel Arria 10 UHD Video Reference Design Functional Description Intel Arria 10 UHD Video Reference Design s Intel Arria 10 UHD Video Reference Design Clocks Software Operation Intel Arria 10 UHD Video Reference Design Resource Utilization Intel Arria 10 UHD Video Reference Design Document Revision History

3 1 Intel Arria 10 UHD Video Reference Design The Intel Arria 10 ultra-high-definition (UHD) video reference design integrates the Intel HDMI 2.0 video connectivity IP core with a video processing pipeline based on Intel FPGA IP from the Intel Video and Image Processing Suite. The design delivers high-quality up-, down-, and cross-conversion (UDX) highdefinition and UHD video streams. The design is highly software and hardware configurable, enabling rapid system configuration and redesign. The reference design targets Intel Arria 10 devices and uses the latest 4K ready IP cores from the Video and Image Processing Suite in the Intel Quartus Prime Design Suite v17.1. The reference design supports Intel Quartus Prime Pro Edition and Intel Quartus Prime Standard Edition Related Links Intel HDMI IP Core User Guide 1.1 Intel Arria 10 UHD Video Reference Design Features Files for targeting Intel Arria 10 GX FPGA Development Kit Input: HDMI 2.0 connectivity supports from 720x480 up to 3840x2160 resolution at any frame rate up to and including 60 fps. Supports both RGB and YCbCr (4:4:4, 4:2:2 and 4:2:0) colour formats at the input. Software automatically detects the input format and sets up the processing pipeline appropriately. Output: HDMI 2.0 connectivity selectable for either 1080p or 2160p resolution at 60 fps. DIP switches set the required output color format (10-bit RGB, YCbCr-4:4:4 or 8-bit YCbCr-4:2:2) Input and output hot-plugging support. Single 10-bit RGB processing pipeline with software configurable up and down scaling. 12x12 tap down-scaler 16x16 phase, 4x4 tap up-scaler Triple buffer video frame buffer provides frame rate conversion from a variable input frame rate to the fixed output rate of 60 fps. Mixer with alpha-blending allowing OSD icon overlay. Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. *Other names and brands may be claimed as the property of others. ISO 9001:2008 Registered

4 This reference design does not support audio. Related Links Avalon Interface Specifications Information about Avalon-MM and Avalon-ST interfaces Video and Image Processing Suite User Guide Information about Avalon-ST video interface 1.2 Intel Arria 10 UHD Reference Design Getting Started Hardware and Software Requirements for the Intel Arria 10 UHD Video Reference Design on page 4 Downloading and Installing the Intel Arria 10 UHD Reference Design on page 5 Connecting up the Intel Arria 10 UHD Reference Design Hardware on page 7 Compiling the Intel Arria 10 UHD Reference Design on page 10 Running the Intel Arria 10 UHD Video Reference Design on the Hardware on page 10 Compiling the Intel Arria 10 UHD Reference Design Software on page Hardware and Software Requirements for the Intel Arria 10 UHD Video Reference Design The reference design requires the following hardware: Intel Arria 10 GX FPGA Development Kit, including the DDR4 Hilo Daughter Card Bitec HDMI 2.0 FMC daughter card HDMI 2.0 source that produces up to 3840x2160p60 RGB and YCbCr video HDMI 2.0 sink that displays up to 3840x2160p60 RGB and YCbCr video The reference design pro version requires the following software: Windows or Linux OS The Intel Quartus Prime Design Suite v17.1 that includes: Intel Quartus Prime Pro Edition Platform Designer Nios II EDS Intel FPGA IP Library (including the Video and Image Processing Suite) The reference design standard version requires the following software: Windows or Linux OS The Intel Quartus Prime Design Suite v17.0 that includes: Intel Quartus Prime Standard Edition Platform Designer (Standard) Nios II EDS Intel FPGA IP Library (including the Video and Image Processing Suite) Note: The reference design only works with these versions of Intel Quartus Prime 4

5 Related Links Arria 10 GX FPGA Development Kit Bitec HDMI FMC Daughter Card Downloading and Installing the Intel Arria 10 UHD Reference Design 1. Download the project file udx10.par from the Intel Design Store. 2. Install the template from the command line: a. Open the Intel Quartus Prime software. b. Click File > New Project Wizard. c. Enter a working directory and project name, for example top. d. Click Next. e. the Project Type page, select Project Template. f. Click Next. g. the Design Templates page, click 2. Install the Design Template. Figure 1. New Project Wizard h. Specify the installation directory. 5

6 Figure 2. Design template Installation i. Click OK. When the installation completes, the software creates the Intel Quartus Prime top.qsf and top.qpf files and all other files for the design. Related Links Intel Design Store Installation Files for the Intel Arria 10 UHD Reference Design Table 1. Files and Directories File or Directory Name Description build_ip.tcl PLL_SYS.qsys qsys_vip_pipeline.qsys qsys_vip_pipeline.sopcinfo top.qpf and top.qsf udx10.v ip (Pro version only) ip\hdmi_subsys \hdmi_subsys_alt_hdmi_example_design \alt_hdmi_example_design\rtl i2c_master i2c_slave Not used. This file shows the flow to build the design from the original Platform Designer files. The PLL that generates the system clocks for the top-level design. The Platform Designer (Standard) system containing the video processing pipeline for the reference design along with the Nios II processor and its associated components. The information file for the qsys_vip_pipline Platform Designer system and the Nios II software project in Eclipse. The Intel Quartus Prime project and settings files for the reference design. The top-level HDL file for this reference design. Contains design IP. The HDMI design example provides the connectivity related hardware and software IP components to the reference design. This rtl directory contains the generated IP blocks (e.g. hdmi_rx, hdmi_rx, clock_control) for the HDMI design example. Directory containing the I2C interface from the HDMI source. You can access this Avalon-MM slave interface from the Nios II processor. Directory containing the I2C interface associated with the HDMI Rx core. The I2C slave has interfaces to the EDID RAM and the SCDC interface on the HDMI Rx core. continued... 6

7 1 Intel Arria 10 UHD Video Reference Design File or Directory Name Description ip\hdmi_subsys \hdmi_subsys_alt_hdmi_example_design \alt_hdmi_example_design\rtl\i2c_slave\edid_ram \edid_ram The HDMI sink s EDID table interface and contents files. The design builds the Platform Designer system in to the edid_ram directory. non_acds_ip IP not available in the Intel FPGA IP library. non_acds_ip\debounce.v non_acds_ip\alt_vip_icon_generate Non-IP library cores that the reference design uses. Including the debounce block to connect to the pushbuttons. master_image - master_image\udx10.sof A pre-built.sof image of the reference design. Use to test the design without having to compile and build it first. sdc Contains the.sdc constraints files. software software\vip_control_src.zip A.zip file containing the software source tree. software\vip_control/mem_init Directory containing the prebuilt RAM contents for the Nios II processor. software\script\build_sw.sh Run this shell script to generate the BSP and executable file from the Nios II source files Connecting up the Intel Arria 10 UHD Reference Design Hardware Figure 3. Intel Arria 10 UHD Reference Design Hardware The photo does not shows the Intel Arria 10 FPGA development board blue heatsink to allow you to see the Hilo daughter card position AN 776: Intel Arria 10 UHD Video Reference Design 7

8 1. Fit the DDR4 Hilo card to the Intel Arria 10 GX FPGA development board. 2. Fit the Bitec HDMI 2.0 FMC card to the Intel Arria 10 GX FPGA development board using FMC Port B. 3. Ensure the power switch (SW1) is turned off, then connect the power connector. 4. Connect a USB-Blaster II download cable to your computer and to the MicroUSB Connector (J3) on the Intel Arria 10 GX FPGA development board. 5. Attach a HDMI 2.0 cable between the HDMI source and the Rx port of the Bitec HDMI 2.0 FMC card and ensure the source is active. 6. Attach a HDMI 2.0 cable between the HDMI display and the Tx port of the Bitec HDMI 2.0 FMC card and ensure the display is active. 7. Turn on board using SW Board Status Lights, DIP Switches, and Pushbuttons The Intel Arria 10 GX FPGA Development board has eight status lights, each of which contains both red and green LEDs, and three push-buttons that the Intel Arria 10 UHD Reference Design uses. Figure 4. Location of Board Status Lights, DIP Switches, and Pushbuttons Reset DIP Switches PB 0 PB 1 PB 2 LCD FMC Card Intel Arria10 GX FPGA board Table 2. LED Status Lights While the reference design is running on the Intel Arria 10 GX FPGA development board, the board s status lights display the current status of the system. Each status light position contains a combined red and green LED. Description Green LEDs 0 HDMI Rx IO Pll locked continued... 8

9 LED Description 1 HDMI Rx Rx ready 2 HDMI Rx locked 3 HDMI Rx oversampling 4 HDMI Tx IO Pll locked 5 HDMI Tx Rx ready 6 HDMI Tx locked 7 HDMI Tx oversampling Red LEDs 0 DDR4 EMIF calibration not completed 1 DDR4 EMIF calibration fail 7 HDMI Tx format no supported. Table 3. Push Buttons While the reference design runs on the Intel Arria 10 GX FPGA development board, use the push-buttons to control the operation of the design. The DIP switches and push-buttons are next to the FMC daughter card and the LCD display. DIP switch settings take effect only after reset. Pushbutton Description PB0 PB1 PB2 Change scaling mode Change output resolution Toggle the Icon display on/off The design software operates in any one of three scaling modes that serve to demonstrate the scaling required to transfer from the current input resolution to the current output resolution. The scaling modes are passthrough, upscaling/clip and downscaling. Use PB0 to cycle through the scaling modes in turn. The design can generate either 1920x1080p60 or 3840x2160p60 output resolutions. Use PB1 to toggle between these resolutions. The design displays an Icon in the top-right corner of the screen by default. Use PB2 to switch this icon display on and off as required. Table 4. DIP Switches Switch and Position Description SW1 Off Default Output Resolution 4Kp p60 SW2 SW3 Output Color Space Off Off RGB Off YCbCr 4:2:2 Off YCbCr 4:4:4 continued... 9

10 Switch and Position Description SW8 Off Figure 5. DIP Switches Terminal Message Output Off The figure shows the position of the switch in white. ON 4kp Default Output Resolution 1080p60 RGB Output Color Space YcbCr 4 :2 :2 YcbCr 4 :4 :4 OFF Terminal Message Output ON Compiling the Intel Arria 10 UHD Reference Design Intel also provides a precompiled udx10.sof file as part of the project file in the master_image directory. Download and install the reference design. 1. In the Intel Quartus Prime software, open the project file top.qpf, which the installation generates. 2. Click Processing Start Compilation. The compilation creates the top.sof file in the output_files directory. Related Links Downloading and Installing the Intel Arria 10 UHD Reference Design Running the Intel Arria 10 UHD Video Reference Design on the Hardware 1. Download the.sof image, in the Intel Quartus Prime software, click Tools Programmer. 2. In the Programmer window, click Add File, then: 10

11 1 Intel Arria 10 UHD Video Reference Design 3. a. To use the precompiled.sof included with the design, select the.sof in the master_image directory. b. To use your compiled.sof, select the.sof in the output_files directory. Start the Nios II terminal to display status messages during its operation, by typing this command on the command line: nios2-terminal When the.sof loads and the terminal program is running, examine the status lights. If you see any red status lights, the DDR4 memory configuration has a failure, so check the seating of the DDR4 card in the Hilo socket. An image appears on the display. Figure 6. Example Image This figure shows an example image with the output resolution set to 1080p and shows the alpha blended logo in the top-right corner of the screen. For this example image the input is a black and white sawtooth test pattern Compiling the Intel Arria 10 UHD Reference Design Software The example code for the design is in the vip_control_src.zip file in the software directory. Install the reference design You can follow the steps to compile the design software, which allows you to debug the design. Or you can run the Intel-provided script. To run the script: 1. In Windows Explorer, in the software directory, unzip the vip_software_src.zip file to generate a vip_software_src directory with all of the necessary software files. 2. In a terminal from the script directory run the shell script build_sw.sh, which generates an executable vip_control.elf in the vip_control directory. AN 776: Intel Arria 10 UHD Video Reference Design 11

12 Note: this scripts overwrites files in the vip_control directory. Edit any source files in the vip_control_src directory only. STEPS: 1. Ensure the qsys_vip_pipeline.sopcinfo file, which the software build process requires, is in the Quartus project directory. If you cannot find the file, ensure you installed the reference design. 2. Navigate to the Intel Quartus Prime project directory. 3. Start Nios II software Build Tools for Eclipse: in the Intel Quartus Prime software, click Tools Nios II software Build Tools for Eclipse. 4. Select the software directory as the workspace folder and click OK to create a new workspace. 5. Click File New Nios II Application and BSP from Template. The Nios II Application and BSP from Template dialog box appears. 12

13 Figure 7. Nios II Application and BSP from Template 6. In the SOPC Information File box, select the qsys_vip_pipeline.sopcinfo file. The Nios II SBT for Eclipse fills in the CPU name with the processor name from the.sopcinfo file.. 7. In the Project name box, type vip_control. 8. Select Blank Project from the Templates list and then click Next. 13

14 9. Select Create a new BSP project based on the application project template with the project name vip_control_bsp and turn on Use default location. 10. Click Finish to create the application and the BSP based on the.sopcinfo file. After the BSP generates, the vip_control and vip_control_bsp projects appear in the Project Explorer tab. 11. In windows Explorer, in the software directory, unzip the vip_software_src.zip file to generate a vip_software_src directory with all of the necessary software files. 12. Copy all these software files and the vip directory from the vip_control_src directory and in the Eclipse Project Explorer tab on the vip_control folder rightclick and select Paste. Do not click on vip_control_bsp. 13. In the Project Explorer window, right-click vip_control_bsp and select Nios II BSP Editor. 14

15 Figure 8. BSP Editor 14. Turn on enable_small_c_library and enable_reduced_device_drivers, click Generate then Exit. 15. Select Project > Build All to generate the file vip_control.elf in the software/vip_control directory. 16. To build the mem_init file for the the Intel Quartus Prime compilation, right click on vip_control in the Project Explorer window and select Make Targets > Build, then select mem_init_generate and click on Build. The Intel Quartus Prime software generates the qsys_vip_pipeline_cpu_ram.hex file in the software/vip_control/ mem_init directory. Related Links Downloading and Installing the Arria 10 UHD Reference Design 1.3 Intel Arria 10 UHD Video Reference Design Functional Description A Platform Designer system, qsys_vip_pipeline.qsys, contains the video pipeline IP and the Nios II processor components. The design associates the remaining components at the top-level with the HDMI Rx and HDMI Tx IP cores and support logic. The design comprises a single video processing path between the HDMI input and the HDMI output. 15

16 Figure 9. Block Diagram The diagram shows the incoming video from the HDMI source on the left. The design processes the video through the video pipeline from left to right before passing the video out to the HDMI sink on the right. HDMI Source From FMC Card Quartus Prime Project (HDL) EDID I 2 C HDMI RX Platform Designer System Clocked Video Input Pipeline Stream Cleaner Nios II Processor Clipper Scaler (Downscale) DDR and EMIF Frame Buffer Scaler (Upscale) Icon Mixer I 2 C Clocked Video Output HDMI TX To FMC Card HDMI Sink GPIO Input Chroma Resampler Input Color Space Converter Deinterlacer Output Color Space Converter Output Chroma Resampler GPIO Reconfig Master Transceiver Reconfiguration Arbitration HDMI Source to HDMI Rx The Bitec HDMI FMC card provides a buffer for the HDMI 2.0 signal from the HDMI source then the HDMI Rx IP core processes the signal. The HDMI Rx IP processes the incoming HDMI signal without any software intervention. The resulting video signal from the HDMI Rx IP is in a clocked video interface format. The reference design configures the HDMI Rx for 8-bit output. Logic between the HDMI Rx and clocked video input bit extends each color plane to 10-bit. Clocked Video Input The clocked video input processes the clocked video interface signal from the HDMI Rx IP core and converts it to Altera proprietary Avalon-ST Video signal format. This signal format strips all horizontal and vertical blanking information from the video leaving only active picture data. The Avalon-ST Video stream through the processing pipe is two pixels in parallel with three symbols per pixel. The clocked video input provides clock crossing for the conversion from the variable rate clocked video signal from the HDMI Rx core to the fixed clock rate for the video IP pipeline. Stream Cleaner The stream cleaner ensures that the Avalon-ST Video signal passing to the processing pipeline is error free. Hot-plugging of the HDMI source can cause the design to present incomplete frames of data to the clocked video input core, which can generate errors in the resulting Avalon-ST Video stream. Chroma Resampler (Input) The input chroma resampler changes the chroma sampling format between 4:4:4, 4:2:2 and 4:2:0 to 4:4:4 based on the input from the software. To provide higher visual quality, chroma resamplers use the most computationally expensive filtered algorithm. 16

17 Color Space Converter (Input) The Input color space converter transforms input video data (RGB or YCbCr) to RGB color space based on the runtime setting from software. Scaling and mixing sections of the pipeline accepts only RGB format. Adding a color space converter to the pipeline enables the design to accept nonrgb formats at the input. The software automatically detects the nonrgb formats and sets up the processing blocks appropriately. Clipper The clipper selects an active area from the incoming video stream and discards the remainder. The software control defines the region to select. Deinterlacer The deinterlacer converts the interlaced input to progressive and supports passthrough of progressive video at up to 4K resolutions. The deinterlacer uses a vertical interpolation algorithm (bob). Scaler (Downscale) The first scaler in the pipeline downscales. The downscaler precedes the frame buffer in the processing pipeline. When performing a downscale operation (rather than just passthrough), the scaler does not continuously generate pixels. The scaler should not pass downscaled video stream directly to a mixer because the mixer requires the pixels to be generated continuously at its inputs. The frame buffer provides a buffer for the pixels generated by the downscaler and gives them to the mixer in an acceptable, continuous stream. Frame Buffer The frame buffer uses the DDR4 memory to perform triple buffering that allows the video and image processing pipeline to perform frame rate conversion between the incoming and outgoing frame rates. The output frame rate is fixed at 60 fps, but the design can use any input frame rate up to 60 fps. Scaler (Upscale) The second scaler in the pipeline upscales. You should insert a frame buffer between the clipper and the upscaler, when performing vertical clip and an upscale operation. The frame buffer regulates the flow of video data between bursts of clipper output data and the bursts of backpressure from the upscaler input. In this system configuration, the clipper cannot operate with irregular backpressure. The frame buffer provides a buffer of the video stream so that the clipper can generate a stream of continuous pixels. Mixer The mixer generates a fixed size black background image that the Nios II processor programs to match the size of the current output image. The mixer has two inputs. The first input connects to the upscaler to allow the design to show the output from the current video pipeline. The second input connects to the Icon generator block. The design only enables the mixer's first input when it detects active, stable video at the clocked video input. Thus, the design maintains a stable output image at the output while hot-plugging at the input. The design alpha blends the second input to the mixer, connected to the Icon generator, over both the background and video pipeline images with 50% transparency. 17

18 Color Space Converter (Output) The output color space converter transforms the input RGB video data to either RGB or YCbCr color space based on the runtime setting from software. Chroma Resampler (Output) The output chroma resampler converts the format from 4:4:4 to one of 4:4:4, 4:2:2 and 4:2:0 and is set by the software. The output chroma resampler also uses filtered algorithm to achieve high-quality video. Clocked Video Output The clocked video output converts the Avalon-ST Video stream to the clocked video format. The design passes the clocked video format to the HDMI transmit IP core. The clocked video output adds horizontal and vertical blanking and synchronisation timing information to the video. The Nios II processor programs the relevant settings in the clocked video output depending on the output resolution. The clocked video output converts the clock crossing from the fixed clock to the variable rate of the clock video output. HDMI Tx The reference design configures the HDMI Tx for 8-bit output. Logic between the Clocked Video Output IP and HDMI Tx removes the two LSBs from each 10-bit color plane output from the clocked video output. Transceiver Reconfiguration Arbitration The transceiver reconfiguration arbitration controls the sequence of the transmit and receive reconfiguration accesses in a first come first served basis and merges accesses to the same native PHY. Reconfiguration Master The reconfiguration master allows the Nios II processor to reconfigure the HDMI Tx to the required output resolution. The software file xcvr_gpll_rcfg.c in the software/vip_control_src directory includes software routines to control the reconfiguration process. The main software source file (main.cpp) sets the required output resolution using the set_output_resolution function. Setting a new output resolution requires you reprogram the Clocked Video Output IP with the relevant timing parameters before reconfiguring the HDMI Tx. System Peripherals The system contains the following components to provide information about the status of the design and to support run-time user input: A JTAG UART (part of the Platform Designer System) to display software printf output. LEDs to display system status. Push-button switches to allow switching between video output resolutions and to allow control of the software running on the Nios II Processor. DIP switches 18

19 Related Links Altera High-Definition Multimedia Interface (HDMI) IP Core User Guide Video and Image Processing Suite User Guide Information about Avalon-ST video interface Intel Arria 10 UHD Video Reference Design s You can change the default compile-time parameters of the video pipeline components to change the operation of the design. Table 5. Clocked Video Input s Bits per pixel per color plane 10 Number of color planes 3 Number of pixels in parallel 2 Use control port Table 6. Stream Cleaner s Bits per pixel per color plane 10 Number of color planes 3 Number of pixels transmitted in 1 clock cycle 2 Maximum frame width 3840 Maximum frame height 2160 Enable control slave port How user packets are handled Discard all user packets received Table 7. Chroma Resampler II (Input) Maximum input frame width 4096 Maximum input frame height 2160 Number of pixels transmitted in 1 clock cycle 2 Run-time control Add extra pipelining registers How user packets are handled Pass all user packets to output Table 8. Color Space Converter II (Input) Bits per Pixel per color plane 10 Number of pixels transmitted in 1 clock cycle 2 continued... 19

20 Run-time control Add extra pipelining registers How user packets are handled No user packets allowed Table 9. Clipper s Maximum input frame width 3840 Maximum input frame height 2160 Number of pixels transmitted in 1 clock cycle 2 Run-time control Add extra pipelining registers How user packets are handled No user packets allowed Table 10. Deinterlacer II Maximum frame width of interlaced content 1920 Maximum frame height of the generated progressive content 1080 Number of color planes 3 Bits per pixel per color plane 10 Pixels in parallel 2 Deinterlacing algorithm Vertical interpolation ( Bob ) Table 11. Scaler (Down) s Number of pixels in parallel 2 Bits per symbol 10 Symbols in parallel 3 Enable runtime control of output frame size and edge/blur thresholds Maximum input frame width 3840 Maximum input frame height 2160 Maximum output frame width 3840 Maximum output frame height 2160 Scaling algorithm POLYPHASE Vertical filter taps 12 Horizontal filter taps 12 Load scaler coefficients at runtime continued... 20

21 Add extra pipelining registers Reduced control slave register readback How user packets are handled No user packets allowed Table 12. Frame Buffer s Maximum frame width 3840 Maximum frame height 2160 Number of color planes 3 Bits per pixel per color plane 10 Pixels in parallel 2 Frame dropping Frame repeating Drop invalid frames Table 13. Scaler (Up) s Number of pixels in parallel 2 Bits per symbol 10 Symbols in parallel 3 Enable runtime control of output frame size and edge/blur thresholds Maximum input frame width 3840 Maximum input frame height 2160 Maximum output frame width 3840 Maximum output frame height 2160 Scaling algorithm POLYPHASE Vertical filter taps 4 Horizontal filter taps 4 Add extra pipelining registers How user packets are handled No user packets allowed Table 14. Mixer s Number of inputs 2 Alpha Blending Enable Register Avalon-ST ready signals Colorspace (used for background layer) RGB continued... 21

22 Pattern Uniform background Maximum output frame width 3840 Maximum output frame height 2160 Bits per pixel per color plane 10 Number of pixels transmitted in 1 clock cycle 2 How user packets are handled Discard all user packets received Table 15. Color Space Converter II (Output) Bits per Pixel per color plane 10 Number of pixels transmitted in 1 clock cycle 2 Run-time control Add extra pipelining registers How user packets are handled No user packets allowed Table 16. Chroma Resampler II (Output) Maximum input frame width 4096 Maximum input frame height 2160 Number of pixels transmitted in 1 clock cycle 2 Run-time control Add extra pipelining registers How user packets are handled No user packets allowed Table 17. Clocked Video Output s Image width / Active pixels 3840 Image height / Active lines 2160 Bits per pixel per color plane 10 Number of color planes 3 Number of pixels in parallel 2 Pixel fifo size 2048 Fifo level at which to start output 2047 Use control port 22

23 1.3.2 Intel Arria 10 UHD Video Reference Design Clocks Table 18. Clocks Name Source Frequency (MHz) Usage clk_fpga_b3_p board PLL 100 Source clock for PLL.qsys. VIP_CLK PLL.qsys 300 All of the Video IP blocks within the Platform Designer design qsys_vip_pipeline use this clock. CPU_CLK PLL.qsys 100 CPU subsystem within the qsys_vip_pipeline Platform Designer system and the management clock interfaces within the HDMI reconfiguration logic. ddr4_pll_ref_clk board PLL 133 DDR4 EMIF reference clock. refclk_fmcb_p board PLL Programmable input clock from clock-chip Si5338 on board. Software running on Nios II processor programs the Si5338 via an I2C interface to generate this MHz clock. hdmi_rx_vid_clk HDMI Rx IP <= 297 The video rate clock generated by the HDMI Rx IP core. Clocks the clocked video interface to the Clocked Video Input IP core in the video pipeline. hdmi_rx_ls_clk HDMI Rx IP <= 297 The link speed clock generated by the HDMI Rx IP core. Clocks the auxiliary data interface out of the core: audio, general control packet, AVI, VSI etc. hdmi_tx_vid_clk HDMI Tx IP <= 297 The video rate clock generated by the HDMI Tx IP core. Clocks the clocked video interface from the Clocked Video Output IP core in the video pipeline into the HDMI Tx IP core. hdmi_tx_ls_clk HDMI Tx IP <= 297 The link speed clock generated by the HDMI Tx IP core. Clocks the auxiliary data interfaces in to the core: audio, general control packet, AVI, VSI etc Software Operation The Intel Arria 10 UHD Video Reference Design software determines the current input resolution and input status automatically from the clocked video input. The software running on the Nios II processor: Programs the on-board clocking chip Si5338 via I2C to generate MHz HDMI Tx reference clock Initializes the video IP cores Processes the following events: HDMI Tx hot-plug Output resolution changes because of push-button control Stable input video availability Scaling mode control via push-button control During a Tx hot-plug, the design reads the HDMI sink s EDID to ensure it can process the user requested output format. If the connected sink cannot process 4Kp60, the design sets the output format to 1080p60. Likewise, if the sink cannot process YCbCr, the design sets the output format to RGB. If the connected HDMI sink cannot process the user selected output format, the red status light 7 illuminates to indicate the condition. 23

24 Use the push-button switches on the Intel Arria 10 GX FPGA development board to control the scaling operations that the video processing pipeline performs and to set the output video resolution. The mixer provides a stable output image using its software programmable size background image. When the design detects a stable input stream from the clock video input block, the design enables the processing pipeline up to the mixer and the design overlays it for the mixer to show. The design overlays the OSD Icon over both the background and processed video image. Press push-button PB2 to turn off the OSD Icon. The video processing pipeline converts the input image size and output image size depending on the scaling. You control the scaling using the push-buttons. Related Links Board Status Lights, DIP Switches, and Pushbuttons on page Intel Arria 10 UHD Video Reference Design Resource Utilization Table 19. Resource Utilization Targeting Intel Quartus Prime version ALMs Total Registers RAM Blocks DSP Blocks 37,700 84, Intel Arria 10 UHD Video Reference Design Document Revision History Date Version Changes January Updated for Intel Quartus Prime v17.1 Added support for YCbCr video Deleted.sdc file Removed refclk_sdi_p clock; added refclk_fmcb_p Removed duplicate stream cleaner parameters table. Added default design settings via DIP switch. Added support for deinterlacer. August Initial release. 24

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