ECE 545 Digital System Design with VHDL Lecture 1B. Digital Logic Refresher Part B Sequential Logic Building Blocks

Transcription

1 ECE 545 igital System esign with VHL Lecture B igital Logic Refresher Part B Sequential Logic Building Blocks

2 Lecture Roadmap Sequential Logic Sequential Logic Building Blocks Flip-Flops, Latches Registers, Shift Registers Counters RAM 2

3 Textbook References Sequential Logic Review Stephen Brown and Zvonko Vranesic, Fundamentals of igital Logic with VHL esign, 2 nd or 3 rd Edition Chapter 7 Flip-flops, Registers, Counters, and a Simple Processors ( , only) OR your undergraduate digital logic textbook (chapters on sequential logic) 3

4 Sequential Logic Building Blocks some slides modified from: Brown and Vranesic, Fundamentals of igital Logic with VHL esign, 2 nd Edition S. andamudi, Fundamentals of Computer Organization and esign 4

5 Introduction to Sequential Logic Output depends on the current input and the internal state Past inputs effects the internal state Sequential circuits consist typically of Storage elements (flip-flop, latch, register, RAM, etc.) Combinational logic 5

6 Introduction (cont d) Main components of a typical synchronous sequential circuit (synchronous = uses a clock to keep circuits in lock step) INPUT PRESENT STATE S(t) COMBINATIONAL LOGIC STATE-HOLING STORAGE ELEMENTS (e.g. FLIP-FLOPS) OUTPUT NEXT STATE S(t+) CLOCK 6

7 State-Holding Memory Elements Latch versus Flip Flop Latches are level-sensitive: whenever clock is high, latch is transparent Flip-flops are edge-sensitive: data passes through (i.e. data is sampled) only on a rising (or falling) edge of the clock Latches cheaper to implement than flip-flops Flip-flops are easier to design with than latches In this course, primarily use flip-flops 7

8 Latch vs. Flip-Flop CLK CLK Latch transparent when clock is high CLK CLK Samples on rising edge of clock 8

9 latch Graphical symbol Clock Truth table Clock (t+) (t) Timing diagram Clock t t 2 t 3 t 4 Time 9

10 flip-flop Graphical symbol Clock Truth table Clk (t+) (t) (t) Timing diagram Clock t t 2 t 3 t 4 Time

11 Flip-Flop with Asynchronous Set and Reset Set Reset Bubble on the symbol means active-low When Set =, set to When Set =, do nothing When Reset =, set to When Reset =, do nothing Set and Reset also known as Preset and Clear respectively In this circuit, Set and Reset are asynchronous changes immediately when preset or clear are active, regardless of clock

12 Flip-Flop with Synchronous Reset Reset Clear Clock CLK Reset (asynchronous Reset) (synchronous Reset) Asynchronous active-low Reset: immediately clears to Synchronous active-low Reset: clears to on rising-edge of clock 2

13 Register (3) (3) CLK (2) (2) 4 4 CLK () () CLK () () CLK Clock In typical nomenclature, a register is a name for a collection of flip-flops used to hold a bus All flip-flops of a register share the same clock and control signals 3

14 Shift Register Sin 3 2 Sout Clk (a) Circuit Clk Sin SHIFT REGISTER Sout t Sin 3 2 Sout= t t 2 t 3 t 4 t 5 t 6 t 7 4

15 4-bit Shift Registers: symbols a) b) Enable 4 Enable 4 Sin Sout Load Sin Clock Clock

16 Shift Register with Serial Input and Serial Output Sin (3) (2) () Sout=() Clock En En En En Enable 6

17 Shift Register with Parallel Load and Parallel Output Load (3) Sin (2) () () Clock Enable (3) (2) () () 7

18 Synchronous Up Counter enable load 2 3 carry 2 3 clock Enable (synchronous): when high enables the counter, when low counter holds its value Load (synchronous) : when load =, load the desired value into the counter Output carry: indicates when the counter rolls over 3 downto, 3 downto is how to interpret MSB to LSB 8

19 Random Access Memory (RAM) More efficient than registers for storing large amounts of data Can read and write to RAM Addressable memory RAM dimensions are: (number of words) x (bits per word) Address is m bits, data is n bits 2 m x n-bit RAM Example: address is 5 bits, data is 8 bits 32 x 8 RAM Write Enable (WE) When set, writing takes place at the next rising edge of the clock n m IN AR WE CLK RAM OUT n 9

20 Block RAM Waveforms REA_FIRST mode 2

21 Block RAM Waveforms WRITE_FIRST mode 2

22 Block RAM Waveforms NO_CHANGE mode 22

23 ual-port RAM Two sets of input ports {INA, ARA, WEA} {INB, ARB, WEB} n INA OUTA n Two corresponding outputs OUTA OUTB m ARA WEA One memory matrix n INB RAM OUTB n Possible operations: Read from two memory locations Write to two different memory locations Read from a memory location and write to a memory location (different or the same) m ARB WEB CLK 23