Wafer Thinning and Thru-Silicon Vias

Transcription

1 Wafer Thinning and Thru-Silicon Vias The Path to Wafer Level Packaging

2 Summary A new dry etching technology Atmospheric Downstream Plasma (ADP) Etch Applications to Packaging Wafer Thinning Cavity Etch 3-D Packaging Vias through Silicon Wafers All Silicon Die Packages Wafer Level Packaging

3 Wafer Thinning Requirements Wafer fab processing thickness 200mm diameter = 725 µm 300mm diameter = 810 µm Wafer thickness for packaging Year 2000 = µm Year 2002 = µm Max Die Size Year 2000 = 20 x 20mm Year 2002 = 40 x 40mm

4 ADP System

5 ADP Simplifies Wafer Thinning No Device Protection Needed No Resist or Tape Application and removal No Defect Removal by Wet Etch 2-5 micron etch No Chemical Difficulties Handling Disposal Lower Chemical Cost

6 Schematic Plasma Source

7 Plasma Source

8 No-Touch Wafer Holding No contact between wafer and holder Wafer Temperature adjustable between 160 and 300 ºC Allows wafers bumped with eutectic Sn/Pb to be thinned without protective coating Thin flexible wafers held flat during processing

9 Grinding Marks Removal

10 Silicon Crystal Orientations

11 Silicon Surface Etched by ADP

12 Wafer Edge ADP Smoothing

13 Before ADP After ADP

14 Damage Free Dicing Controlled Depth Dicing Apply tape on front side (over dicing) Grind back of wafer ADP etch on back of the wafer to singulate dies

15 SEM Damage Free Dicing Sawed die shows edge chipping ADP singulated die has rounded and smooth edges

16 Damage Free Dicing Benefits: Rounded edges and corners Mechanical Strength High Reliability during Temperature shock and cycling Ultra-thin die capability 20µm dies demonstrated Smooth edge helps pick-and-place

17 Stacked Dies in <1mm packages Ultra-thin packages strictly Japanese phenomena in the early 90s New US adoption of: Smart cards Memory cards Stacked dies desirable: Reduce loop height Minimize footprint

18 Stacked Wire Bonded Dies

19 Why 3-D Packages and Wafer Stacking? Electrical performance: Reduced interconnection length. Short connections is the most effective method to improve system speed. Gang processing: Lower labor cost Familiar wafer fab equipment Improved reliability:

20 The number of transistors double every 2nd year

21 Die area doubles every 5.5 years Lineal side dimension doubles every 11 years

22 System Bandwidth Limits Performance Chip Clock rates: Much faster than board level Determined by semiconductor architecture Interconnect length << wavelength Bus clock rates: High Speed outside chip requires transmission lines Parallel operation necessary 100 MHz bus clock --> 763 MBs on 32 bit bus

23 Array of vias (backside of wafer)

24 Test Substrate Layout - GDSII plot

25 Thru-Si Test Substrate

26 Interconnect Bump

27 What makes through Silicon vias tick?

28 Via Etch Masking

29 ADP Via Etch

30 ADP Via Etch (continued)

31 ADP Back Etch of via

32 Stackable Via

33 Tru-CSP face-to-face ICs

34 Stacked Chips: Tru-CSP

35 3-D Wafer Level Packaging

36 ADP Etch Aluminum Mask

37 Early Stage of ADP Via Etch

38 Via Hemispherical Shape

39 Wet Etched Via

40 Work in Progress Anisotropic Etching Model to predict shape of cavities Reliability Thermal Through the Silicon vias Thin Silicon Electrical Performance RLC characterization Model for CAD insertion

41 Summary of 3-D Development Short term goals: Bumped wafers All Silicon package Tiled wafers Wafer level packaging Long Term goals: 3-D Wafer Level Packaging Stacked dies Wafer level