The CHIME Pathfinder and Correlator. Matt Dobbs for the CHIME Collaboration
|
|
- Susanna Brooks
- 6 years ago
- Views:
Transcription
1 The CHIME Pathfinder and Correlator Matt Dobbs for the CHIME Collaboration
2 Intense Competitive Sports Atmosphere in BC Bridge tournament taking place this week at the Days Inn, Penticton. DRAO
3 Cosmic Sound Start: z=0.01 End: z=0.62 Simulation Video: Nick Gnedin & Dave McGinnis (Fermilab), DRAO
4 Pathfinder ADC ADC ADC Cartoon: 1 cylinder with 12 feeds summed into 3 digitizers. Pathfinder will have 64 feeds x 2 pol x 2 cylinders. Matt.Dobbs@McGill.ca, DRAO
5 Single Dish vs. Interferometer vs. CRT ( 50K) 0.3 o ( 0.3 o ) 2 Size = (100m) 2 = 0.5m T Feed = 50K 100m 0.6 o ( 4 50K) ( o ) 2 Matt.Dobbs@McGill.ca, DRAO
6 DRAO
7 Aliasing & Fringe Stopping (for non-equatorial CRT) each lobe fringe-stops at a different rate. Matt.Dobbs@McGill.ca, DRAO
8 tile DRAO
9 DRAO
10 DRAO
11 Analog Beam Forming Cannot adjust (G, ) after-the-fact. Initial calibration/stability essential. just one beam per digitizer Adjusting phase steers the beam 1 Digitizer per Feed FFT correlated: cannot adust (G, ) after-the-fact N 2 correlated: can calibrate offline Hybrid Trades FLOPS for ease-of-calibration (money for robustness) Large scales: cannot adust (G, ) after-the-fact Small scales, FFT correlated: dito. Small scales N 2 correlated: can calibrate offline. For fixed N digitizer (=cost) allows to trade survey area for angular resolution Time hydrid (not shown, applies to middle & bottom) Can N 2 correlate for a small fraction of time or frequency-bandwidth, and use this to correct (G, ) for FFT correlation. Matt.Dobbs@McGill.ca, DRAO
12 -> x Hybrid Can also N 2 correlate specific pairs, like each feed with a pseudorandom source. Provides time-stability calibration for gain, phase creating a static beams. Matt.Dobbs@McGill.ca, DRAO
13 Beam Forming One Feed Beam pattern of one feed (Analog) Sum feeds to shape beam, increase sensitivity Equivalent to throwing away all but one digitally formed beam Cost saving anti-aliasing measure. Can choose deep (north) vs wide (equatorial). 8 Feeds Summed (Digital) beam forming, divides beams into several One Channel from 16 Digitizer Beam Former (This example, 128 feeds, 16 digitizers, w=16m cylinder) Plots From Dave McGinnis simulation code, Fermilab Matt.Dobbs@McGill.ca, DRAO
14 McGinnis Sim Code, Fermilab (this sim: two 8x25m cylinders with 64 feeds integrating for 3 years, showing just one frequency slice) Matt.Dobbs@McGill.ca, DRAO
15 Pathfinder Forecast Plot: Kiyoshi Masui DRAO
16 Baselines Uniform feed spacing: Unique feed spacing for each cylinder: 16 feeds across 40m DRAO
17 Tool Kit Angular resolution requirement determines collecting area: 100m x 100m for BAO at z=3 Cost drives # of digitizer channels. # feeds to sum into a single digitizer Trades off survey speed (wide) for cost Steering primary beam north (south) trades deep for wide. Can choose between FFT beamforming Full N 2 correlation Trades cost (compute power) for calibration robustness. Can do full N 2 for fraction of time or bandwidth. Matt.Dobbs@McGill.ca, DRAO
18 CHIME Dataflow DRAO
19 Channelizer/Beamformer/Correlator Digitize Analog Signals Channelize (FFT in time) Assemble data from each frequency bin in one place FFT Beam-form along cylinder Correlate between cylinders Or do the full N 2, if cost permits. Matt.Dobbs@McGill.ca, DRAO
20 Networking (similar to ASKAP implementation) Example using DRAO Kermode FPGA board, with ATCA backplane Data assembled in 3 hops Uses low-cost integrated FPGA transceivers Can be implemented with low-cost FPGA demo boards with PCIe backplane for CHIME Pathfinder Matt.Dobbs@McGill.ca, DRAO
21 Digitizer/Channelizer/Beamformer Digitizer hardware being constructed now at McGill. Firmware under test for Channelizer, networking. DRAO
22 Cost of the full N 2 Correlation Full CHIME ~ 5 Cyl, 256 dual pol feeds per cyl 2560 Digitized Signals to Correlate ch at 1 MHz 4 COMPLEX 400 MHz = 5243 TFLOP 2 John referred to this scenario simply as ouch yesterday. GPU Radeon 6990 (Available Yesterday, sitting in Siever s desktop today) ~5 TFLOP / $1K / 400W 2 FLOP = 1 multiply + 1 addition 2000 GPU boards, $2M cost, $0.7M/year electricity. Pathfinder ~ 2 Cyl, 64 dual pol feeds per cyl COMPLEX 400 ch at 1 MHz 400 MHz = 52.4 TFLOP 20 GPU boards, $20K cost, $7K/year electricity. Matt.Dobbs@McGill.ca, DRAO
23 CHIME Digitizer Boards (with J-F Cliche, Adam Gilbert) 8 Channels at 1.2 GSPS 24 GBPS IO Standard FMC interface, Mates to DRAO Kermode board Xilinx V6 Demo Boards Use Casper and inhouse firmware Matt.Dobbs@McGill.ca, DRAO
24 Summary Cylinders are a flexible medium for instrument design especially if the Fourier modes of your signal are confined, as is the case for the BAO. CHIME Pathfinder: 2 cylinder instrument to demonstrate CRT concepts, with a good short at providing first Hydrogen Intensity mapping probe of BAO. Prototyping systems now. Matt.Dobbs@McGill.ca, DRAO
SKA-LTIUM Altium Live Summit 2017
SKA-LTIUM Altium Live Summit 2017 PRESENTER: Omer Mahgoub WHAT IS SKA? Global non-profit Organisation Headquarters in Manchester, United Kingdom Ten member countries WHAT ARE THEY DOING? SKA - Square Kilometre
More informationTelescope Concepts for Very Large Arrays. John D Bunton Workshop on Novel Telescopes for 21cm Cosmology June 2011
Telescope Concepts for Very Large Arrays John D Bunton Workshop on Novel Telescopes for 21cm Cosmology 12-16 June 2011 Early Radio Astronomy L Parkes 64m 1961 Power meter Sea Cliff Interferometer 1948
More informationGetting Started with the LabVIEW Sound and Vibration Toolkit
1 Getting Started with the LabVIEW Sound and Vibration Toolkit This tutorial is designed to introduce you to some of the sound and vibration analysis capabilities in the industry-leading software tool
More informationBEAMFORMING AND CALIBRATION ARCHITECTURES USING THE CASPER SYSTEM
MCCT-SKADS Technical Workshop The SKA and Digital Signal Processing 9 th - 13 th November 2009, The University of Manchester, UK BEAMFORMING AND CALIBRATION ARCHITECTURES USING THE CASPER SYSTEM Giovanni
More informationUnderstanding Sampling rate vs Data rate. Decimation (DDC) and Interpolation (DUC) Concepts
Understanding Sampling rate vs Data rate. Decimation (DDC) and Interpolation (DUC) Concepts TIPL 4701 Presented by Jim Seton Prepared by Jim Seton 1 Table of Contents Input Data Rates Why lower data rates
More informationEXOSTIV TM. Frédéric Leens, CEO
EXOSTIV TM Frédéric Leens, CEO A simple case: a video processing platform Headers & controls per frame : 1.024 bits 2.048 pixels 1.024 lines Pixels per frame: 2 21 Pixel encoding : 36 bit Frame rate: 24
More informationni.com Digital Signal Processing for Every Application
Digital Signal Processing for Every Application Digital Signal Processing is Everywhere High-Volume Image Processing Production Test Structural Sound Health and Vibration Monitoring RF WiMAX, and Microwave
More informationTHE DIAGNOSTICS BACK END SYSTEM BASED ON THE IN HOUSE DEVELOPED A DA AND A D O BOARDS
THE DIAGNOSTICS BACK END SYSTEM BASED ON THE IN HOUSE DEVELOPED A DA AND A D O BOARDS A. O. Borga #, R. De Monte, M. Ferianis, L. Pavlovic, M. Predonzani, ELETTRA, Trieste, Italy Abstract Several diagnostic
More informationPlease feel free to download the Demo application software from analogarts.com to help you follow this seminar.
Hello, welcome to Analog Arts spectrum analyzer tutorial. Please feel free to download the Demo application software from analogarts.com to help you follow this seminar. For this presentation, we use a
More informationPrepSKA WP2 Meeting Software and Computing. Duncan Hall 2011-October-19
PrepSKA WP2 Meeting Software and Computing Duncan Hall 2011-October-19 Imaging context 1 of 2: 2 Imaging context 2 of 2: 3 Agenda: - Progress since 2010 October - CoDR approach and expectations - Presentation
More informationMCP Signal Extraction and Timing Studies. Kurtis Nishimura University of Hawaii LAPPD Collaboration Meeting June 11, 2010
MCP Signal Extraction and Timing Studies Kurtis Nishimura University of Hawaii LAPPD Collaboration Meeting June 11, 2010 Outline Studying algorithms to process pulses from MCP devices. With the goal of
More informationDevelopment of beam-collision feedback systems for future lepton colliders. John Adams Institute for Accelerator Science, Oxford University
Development of beam-collision feedback systems for future lepton colliders P.N. Burrows 1 John Adams Institute for Accelerator Science, Oxford University Denys Wilkinson Building, Keble Rd, Oxford, OX1
More informationLOW POWER DIGITAL EQUALIZATION FOR HIGH SPEED SERDES. Masum Hossain University of Alberta
LOW POWER DIGITAL EQUALIZATION FOR HIGH SPEED SERDES Masum Hossain University of Alberta 0 Outline Why ADC-Based receiver? Challenges in ADC-based receiver ADC-DSP based Receiver Reducing impact of Quantization
More informationThe ATLAS Tile Calorimeter, its performance with pp collisions and its upgrades for high luminosity LHC
The ATLAS Tile Calorimeter, its performance with pp collisions and its upgrades for high luminosity LHC Tomas Davidek (Charles University), on behalf of the ATLAS Collaboration Tile Calorimeter Sampling
More informationCASPER Workshop. Tutorial 4: Wideband Pocket Correlator
CASPER Workshop Tutorial 4: Wideband Pocket Correlator Dev. By : W. New (Version 1) Doc. By : Irappa M. Halagali, Mekhala V. Muley & Shelton Gnanaraj J. (version 2) Expected completion time: 2hrs Contents:
More informationSpectrum Analyser Basics
Hands-On Learning Spectrum Analyser Basics Peter D. Hiscocks Syscomp Electronic Design Limited Email: phiscock@ee.ryerson.ca June 28, 2014 Introduction Figure 1: GUI Startup Screen In a previous exercise,
More informationLow Level RF for PIP-II. Jonathan Edelen LLRF 2017 Workshop (Barcelona) 16 Oct 2017
Low Level RF for PIP-II Jonathan Edelen LLRF 2017 Workshop (Barcelona) 16 Oct 2017 PIP-II LLRF Team Fermilab Brian Chase, Edward Cullerton, Joshua Einstein, Jeremiah Holzbauer, Dan Klepec, Yuriy Pischalnikov,
More informationFront End Electronics
CLAS12 Ring Imaging Cherenkov (RICH) Detector Mid-term Review Front End Electronics INFN - Ferrara Matteo Turisini 2015 October 13 th Overview Readout requirements Hardware design Electronics boards Integration
More informationAn FPGA Based Solution for Testing Legacy Video Displays
An FPGA Based Solution for Testing Legacy Video Displays Dale Johnson Geotest Marvin Test Systems Abstract The need to support discrete transistor-based electronics, TTL, CMOS and other technologies developed
More informationProspect and Plan for IRS3B Readout
Prospect and Plan for IRS3B Readout 1. Progress on Key Performance Parameters 2. Understanding limitations during LEPS operation 3. Carrier02 Rev. C (with O-E-M improvements) 4. Pre-production tasks/schedule
More informationStatus of readout electronic design in MOST1
Status of readout electronic design in MOST1 Na WANG, Ke WANG, Zhenan LIU, Jia TAO On behalf of the Trigger Group (IHEP) Mini-workshop for CEPC MOST silicon project,23 November,2017,Beijing Outline Introduction
More informationCalibrate, Characterize and Emulate Systems Using RFXpress in AWG Series
Calibrate, Characterize and Emulate Systems Using RFXpress in AWG Series Introduction System designers and device manufacturers so long have been using one set of instruments for creating digitally modulated
More informationFeedback Control of SPS E-Cloud/TMCI Instabilities
Feedback Control of SPS E-Cloud/TMCI Instabilities C. H. Rivetta 1 LARP Ecloud Contributors: A. Bullitt 1, J. D. Fox 1, T. Mastorides 1, G. Ndabashimiye 1, M. Pivi 1, O. Turgut 1, W. Hofle 2, B. Savant
More informationADF-2 Production Readiness Review
ADF-2 Production Readiness Review Presented by D. Edmunds 11-FEB-2005 The ADF-2 circuit board is part of the new Run IIB Level 1 Calorimeter Trigger. The purpose of this note is to provide the ADF-2 Production
More informationSVT DAQ. Per Hansson Adrian HPS Collaboration Meeting 10/27/2015
SVT DAQ Per Hansson Adrian HPS Collaboration Meeting 10/27/2015 Overview Trigger rate improvements Optimized data format Shorter APV25 shaping time Single event upset monitor Data integrity Plans 2 Deadtime
More informationPractical Application of the Phased-Array Technology with Paint-Brush Evaluation for Seamless-Tube Testing
ECNDT 2006 - Th.1.1.4 Practical Application of the Phased-Array Technology with Paint-Brush Evaluation for Seamless-Tube Testing R.H. PAWELLETZ, E. EUFRASIO, Vallourec & Mannesmann do Brazil, Belo Horizonte,
More informationSPS BPM system renovation. Roadmap & Milestones
SPS BPM system renovation Roadmap & Milestones Synopsis Introduction and Overview: Andrea Infrastructures Fibres: Simao Cables: Joel Electronics Analogue Front-End: Manfred Digital Front-End: Manoel Back-End:
More informationZebra2 (PandA) Functionality and Development. Isa Uzun and Tom Cobb
Zebra2 (PandA) Functionality and Development Isa Uzun and Tom Cobb Control Systems Group 27 April 2016 Outline Part - I ZEBRA and Motivation Hardware Architecture Functional Capabilities Part - II Software
More informationTrigger synchronization and phase coherent in high speed multi-channels data acquisition system
White Paper Trigger synchronization and phase coherent in high speed multi-channels data acquisition system Synopsis Trigger synchronization and phase coherent acquisition over multiple Data Acquisition
More informationAR SWORD Digital Receiver EXciter (DREX)
Typical Applications Applied Radar, Inc. Radar Pulse-Doppler processing General purpose waveform generation and collection Multi-channel digital beamforming Military applications SIGINT/ELINT MIMO and
More informationA TARGET-based camera for CTA
A TARGET-based camera for CTA TeV Array Readout with GSa/s sampling and Event Trigger (TARGET) chip: overview Custom-designed ASIC for CTA, developed in collaboration with Gary Varner (U Hawaii) Implementation:
More informationNanoGiant Oscilloscope/Function-Generator Program. Getting Started
Getting Started Page 1 of 17 NanoGiant Oscilloscope/Function-Generator Program Getting Started This NanoGiant Oscilloscope program gives you a small impression of the capabilities of the NanoGiant multi-purpose
More informationDesign and Implementation of an AHB VGA Peripheral
Design and Implementation of an AHB VGA Peripheral 1 Module Overview Learn about VGA interface; Design and implement an AHB VGA peripheral; Program the peripheral using assembly; Lab Demonstration. System
More informationTHE WaveDAQ SYSTEM FOR THE MEG II UPGRADE
Stefan Ritt, Paul Scherrer Institute, Switzerland Luca Galli, Fabio Morsani, Donato Nicolò, INFN Pisa, Italy THE WaveDAQ SYSTEM FOR THE MEG II UPGRADE DRS4 Chip 0.2-2 ns Inverter Domino ring chain IN Clock
More informationDRS Application Note. Integrated VXS SIGINT Digital Receiver/Processor. Technology White Paper. cwcembedded.com
Technology White Paper DRS Application Note tegrated VXS SIGINT Digital Receiver/Processor Figure 1: DRS Tuner and Curtiss-Wright DSP Engine troduction This application note describes a notional Signals
More informationFront End Electronics
CLAS12 Ring Imaging Cherenkov (RICH) Detector Mid-term Review Front End Electronics INFN - Ferrara Matteo Turisini 2015 October 13 th Overview Readout requirements Hardware design Electronics boards Integration
More informationMFAA Array Prototypes
MFAA Array Prototypes Pieter Benthem - ASTRON Marco Drost - ASTRON Intro Array Prototypes SOW EMBRACE SKA Karoo site environmental prototypes (Marco Drost) SKA Karoo site array verification system Convince?
More informationZynq platform and related instruments
Libera Single Pass E / Matjaž Žnidarčič, 12.10.2012 Zynq platform and related instruments Peter Leban, DEELS, June 2017, Paris Content Peter's project Company's projects (continuation) (continuation) LAST
More informationField Programmable Gate Arrays (FPGAs)
Field Programmable Gate Arrays (FPGAs) Introduction Simulations and prototyping have been a very important part of the electronics industry since a very long time now. Before heading in for the actual
More informationOscilloscopes, logic analyzers ScopeLogicDAQ
Oscilloscopes, logic analyzers ScopeLogicDAQ ScopeLogicDAQ 2.0 is a comprehensive measurement system used for data acquisition. The device includes a twochannel digital oscilloscope and a logic analyser
More informationLMH0340/LMH0341 SerDes EVK User Guide
LMH0340/LMH0341 SerDes EVK User Guide July 1, 2008 Version 1.05 1 1... Overview 3 2... Evaluation Kit (SD3GXLEVK) Contents 3 3... Hardware Setup 4 3.1 ALP100 BOARD (MAIN BOARD) DESCRIPTION 5 3.2 SD340EVK
More informationChoosing an Oscilloscope
Choosing an Oscilloscope By Alan Lowne CEO Saelig Company (www.saelig.com) Post comments on this article at www.nutsvolts.com/ magazine/article/october2016_choosing-oscilloscopes. All sorts of questions
More informationNutaq. PicoDigitizer-125. Up to 64 Channels, 125 MSPS ADCs, FPGA-based DAQ Solution With Up to 32 Channels, 1000 MSPS DACs PRODUCT SHEET. nutaq.
Nutaq Up to 64 Channels, 125 MSPS ADCs, FPGA-based DAQ Solution With Up to 32 Channels, 1000 MSPS DACs PRODUCT SHEET QUEBEC I MONTREAL I N E W YO R K I nutaq.com Nutaq The PicoDigitizer 125-Series is a
More informationmmwave Radar Sensor Auto Radar Apps Webinar: Vehicle Occupancy Detection
mmwave Radar Sensor Auto Radar Apps Webinar: Vehicle Occupancy Detection Please note, this webinar is being recorded and will be made available to the public. Audio Dial-in info: Phone #: 1-972-995-7777
More informationLLRF at SSRF. Yubin Zhao
LLRF at SSRF Yubin Zhao 2017.10.16 contents SSRF RF operation status Proton therapy LLRF Third harmonic cavity LLRF Three LINAC LLRF Hard X FEL LLRF (future project ) Trip statistics of RF system Trip
More informationMassive MIMO Eight things to consider when testing antenna arrays
Massive_MIMO_misc_5216-2018-92_v0100indd 1 eguide Version 0100 Massive MIMO Eight things to consider when testing antenna arrays 15102018 09:14:29 Massive MIMO makes it possible to increase data throughput
More informationCombating Closed Eyes Design & Measurement of Pre-Emphasis and Equalization for Lossy Channels
Combating Closed Eyes Design & Measurement of Pre-Emphasis and Equalization for Lossy Channels Why Test the Receiver? Serial Data communications standards have always specified both the transmitter and
More informationCombating Closed Eyes Design & Measurement of Pre-Emphasis and Equalization for Lossy Channels
Combating Closed Eyes Design & Measurement of Pre-Emphasis and Equalization for Lossy Channels Why Test the Receiver? Serial Data communications standards have always specified both the transmitter and
More informationTechniques for Extending Real-Time Oscilloscope Bandwidth
Techniques for Extending Real-Time Oscilloscope Bandwidth Over the past decade, data communication rates have increased by a factor well over 10X. Data rates that were once 1Gb/sec and below are now routinely
More informationModeling and Implementing Software-Defined Radio Communication Systems on FPGAs Puneet Kumar Senior Team Lead - SPC
Modeling and Implementing Software-Defined Radio Communication Systems on FPGAs Puneet Kumar Senior Team Lead - SPC 2012 The MathWorks, Inc. 1 Agenda Integrated Model-Based Design to Implement SDR on FPGA
More informationPROJECT DESCRIPTION. Project Name. Broader Impact. Real Time Simulator for ILC RF and CryoModules
Project Name PROJECT DESCRIPTION Real Time Simulator for ILC RF and CryoModules Personnel and Institution(s) requesting funding Nigel Lockyer (Professor) University of Pennsylvania Anna Grassellino (1st
More informationUpdate on DAQ for 12 GeV Hall C
Update on DAQ for 12 GeV Hall C Brad Sawatzky Hall C Winter User Group Meeting Jan 20, 2017 SHMS/HMS Trigger/Electronics H. Fenker 2 SHMS / HMS Triggers SCIN = 3/4 hodoscope planes CER = Cerenkov(s) STOF
More informationRDBE: 2 nd Generation VLBI Digital Backend System. Alan Whitney MIT Haystack Observatory
RDBE: 2 nd Generation VLBI Digital Backend System Alan Whitney MIT Haystack Observatory 1 st generation DBE development at Haystack DBE1 (developed 2004-2006) Hardware is based on a flexible FPGA-based
More informationOF AN ADVANCED LUT METHODOLOGY BASED FIR FILTER DESIGN PROCESS
IMPLEMENTATION OF AN ADVANCED LUT METHODOLOGY BASED FIR FILTER DESIGN PROCESS 1 G. Sowmya Bala 2 A. Rama Krishna 1 PG student, Dept. of ECM. K.L.University, Vaddeswaram, A.P, India, 2 Assistant Professor,
More informationFPGA Development for Radar, Radio-Astronomy and Communications
John-Philip Taylor Room 7.03, Department of Electrical Engineering, Menzies Building, University of Cape Town Cape Town, South Africa 7701 Tel: +27 82 354 6741 email: tyljoh010@myuct.ac.za Internet: http://www.uct.ac.za
More informationWhat s New in Raven May 2006 This document briefly summarizes the new features that have been added to Raven since the release of Raven
What s New in Raven 1.3 16 May 2006 This document briefly summarizes the new features that have been added to Raven since the release of Raven 1.2.1. Extensible multi-channel audio input device support
More informationWhat to look for when choosing an oscilloscope
What to look for when choosing an oscilloscope Alan Tong (Pico Technology Ltd.) Introduction For many engineers, choosing a new oscilloscope can be daunting there are hundreds of different models to choose
More informationSérgio Rodrigo Marques
Sérgio Rodrigo Marques (on behalf of the beam diagnostics group) sergio@lnls.br Outline Introduction Stability Requirements General System Requirements FOFB Strategy Hardware Overview Performance Tests:
More informationATCA-based LLRF System for XFEL
ATCA-based LLRF System for XFEL Demonstration at FLASH Waldemar Koprek, DESY for the XFEL LLRF team Outline Introduction to ATCA LLRF System for the European XFEL Demonstration at FLASH Measurements Introduction
More informationL11/12: Reconfigurable Logic Architectures
L11/12: Reconfigurable Logic Architectures Acknowledgements: Materials in this lecture are courtesy of the following people and used with permission. - Randy H. Katz (University of California, Berkeley,
More informationQUICK START GUIDE FOR DEMONSTRATION CIRCUIT /12/14 BIT 10 TO 105 MSPS ADC
LTC2280, LTC2282, LTC2284, LTC2286, LTC2287, LTC2288 LTC2289, LTC2290, LTC2291, LTC2292, LTC2293, LTC2294, LTC2295, LTC2296, LTC2297, LTC2298 or LTC2299 DESCRIPTION Demonstration circuit 851 supports a
More informationESE534: Computer Organization. Today. Image Processing. Retiming Demand. Preclass 2. Preclass 2. Retiming Demand. Day 21: April 14, 2014 Retiming
ESE534: Computer Organization Today Retiming Demand Folded Computation Day 21: April 14, 2014 Retiming Logical Pipelining Physical Pipelining Retiming Supply Technology Structures Hierarchy 1 2 Image Processing
More informationRF Technology for 5G mmwave Radios
RF Technology for 5G mmwave Radios THOMAS CAMERON, PhD Director of Wireless Technology 09/27/2018 1 Agenda Brief 5G overview mmwave Deployment Path Loss Typical Link Budget Beamforming architectures Analog
More informationRFI MITIGATING RECEIVER BACK-END FOR RADIOMETERS
RFI MITIGATING RECEIVER BACK-END FOR RADIOMETERS Phaneendra Bikkina 1, Qingjun Fan 2, Wenlan Wu 1, Jinghong Chen 2 and Esko Mikkola 1 1 Alphacore, Inc., 2 University of Houston 2017 CASPER Workshop Pasadena,
More informationBe ahead in 5G. Turn visions into reality.
e n e Be ahead in 5G. Turn visions into reality. 5G test solutions ) www.rohde-schwarz.com/5g 20937_003_5G Flyer_3606-8620-32_V0100_170310.indd 3 5G test challenge: Measuring new 5G systems 5G challenges
More informationS op o e p C on o t n rol o s L arni n n i g n g O bj b e j ctiv i e v s
ET 150 Scope Controls Learning Objectives In this lesson you will: learn the location and function of oscilloscope controls. see block diagrams of analog and digital oscilloscopes. see how different input
More informationModular Block Converter Systems
Modular Block Converter Systems The Modular Block Converter System eliminates system downtime and maximizes ease of repair by providing fully modular systems for up conversion or down conversion. Critical
More informationSignal Stability Analyser
Signal Stability Analyser o Real Time Phase or Frequency Display o Real Time Data, Allan Variance and Phase Noise Plots o 1MHz to 65MHz medium resolution (12.5ps) o 5MHz and 10MHz high resolution (50fs)
More informationUnderstanding and Calculating Probability of Intercept
Application Note 74-0046-160517 Understanding and Calculating Probability of Intercept This application note explains the Probability of Intercept (POI) pertaining to a radio-frequency (RF) signal analyser,
More informationAntenna system Status & progress report
Antenna system Status & progress report Brian Corey (MIT Haystack), for the antenna work package group 18 December 2006 MWA-LFD Project Meeting in Melbourne 1 General specifications Tunable frequency range
More informationHigh Performance Raster Scan Displays
High Performance Raster Scan Displays Item Type text; Proceedings Authors Fowler, Jon F. Publisher International Foundation for Telemetering Journal International Telemetering Conference Proceedings Rights
More informationThe AuroraScience Project
The AuroraScience Project F. S. Schifano 1 1 University of Ferrara and INFN-Ferrara November 25-26, 2009 F. S. Schifano (Univ. and INFN of Ferrara) The AuroraScience Project November 25-26, 2009 1 / 24
More informationVHDL Design and Implementation of FPGA Based Logic Analyzer: Work in Progress
VHDL Design and Implementation of FPGA Based Logic Analyzer: Work in Progress Nor Zaidi Haron Ayer Keroh +606-5552086 zaidi@utem.edu.my Masrullizam Mat Ibrahim Ayer Keroh +606-5552081 masrullizam@utem.edu.my
More informationCOMMISSIONING OF THE ALBA FAST ORBIT FEEDBACK SYSTEM
COMMISSIONING OF THE ALBA FAST ORBIT FEEDBACK SYSTEM A. Olmos, J. Moldes, R. Petrocelli, Z. Martí, D. Yepez, S. Blanch, X. Serra, G. Cuni, S. Rubio, ALBA-CELLS, Barcelona, Spain Abstract The ALBA Fast
More informationBeam Position Monitor Developments at PSI
Paul Scherrer Institut V. Schlott for the PSI Diagnostics Section Wir schaffen Wissen heute für morgen Beam Position Monitor Developments at PSI Overview Motivation European XFEL BPM Systems SwissFEL BPM
More informationA Proof of Concept - Challenges of testing high-speed interface on wafer at lower cost
A Proof of Concept - Challenges of testing high-speed interface on wafer at lower cost How to expand the bandwidth of the cantilever probe card Sony LSI Design Inc. Introduction Design & Simulation PCB
More informationTrigger Cost & Schedule
Trigger Cost & Schedule Wesley Smith, U. Wisconsin CMS Trigger Project Manager DOE/NSF Review May 9, 2001 1 Baseline L4 Trigger Costs From April '00 Review -- 5.69 M 3.96 M 1.73 M 2 Calorimeter Trig. Costs
More informationInside Digital Design Accompany Lab Manual
1 Inside Digital Design, Accompany Lab Manual Inside Digital Design Accompany Lab Manual Simulation Prototyping Synthesis and Post Synthesis Name- Roll Number- Total/Obtained Marks- Instructor Signature-
More informationLab # 9 VGA Controller
Lab # 9 VGA Controller Introduction VGA Controller is used to control a monitor (PC monitor) and has a simple protocol as we will see in this lab. Kit parts for this lab 1 A closer look VGA Basics The
More informationL12: Reconfigurable Logic Architectures
L12: Reconfigurable Logic Architectures Acknowledgements: Materials in this lecture are courtesy of the following sources and are used with permission. Frank Honore Prof. Randy Katz (Unified Microelectronics
More informationRF considerations for SwissFEL
RF considerations for H. Fitze in behalf of the PSI RF group Workshop on Compact X-Ray Free Electron Lasers 19.-21. July 2010, Shanghai Agenda Introduction RF-Gun Development C-band development Summary
More informationFirst evaluation of the prototype 19-modules camera for the Large Size Telescope of the CTA
First evaluation of the prototype 19-modules camera for the Large Size Telescope of the CTA Tsutomu Nagayoshi for the CTA-Japan Consortium Saitama Univ, Max-Planck-Institute for Physics 1 Cherenkov Telescope
More informationPrototyping Solutions For New Wireless Standards
Prototyping Solutions For New Wireless Standards Christoph Juchems IAF Institute For Applied Radio System Technology Berliner Str. 52 J D-38104 Braunschweig Germany www.iaf-bs.de Introduction IAF Institute
More informationIntra-train Longitudinal Feedback for Beam Stabilization at FLASH
Intra-train Longitudinal Feedback for Beam Stabilization at FLASH Ch. Behrens 1), M.-K. Bock 1), M. Felber 1), P. Gessler 1), K. Hacker 1), W. Koprek 1), H. Schlarb 1), S. Wesch 1), C.Schmidt 1), S. Schulz
More informationM598. Radeon E8860 (Adelaar) Video & Graphics PMC. Aitech
Single Width PMC PCI-X 64-bit @ 133 MHz Host Interface AMD Radeon E8860 (Adelaar) GPU 6 Independent Graphics Heads 2 GB GDDR5 Analog Inputs Analog and Digital Outputs Full Switching Capabilities Capture
More informationSilicon PhotoMultiplier Kits
Silicon PhotoMultiplier Kits Silicon PhotoMultipliers (SiPM) consist of a high density (up to ~ 10 3 /mm 2 ) matrix of photodiodes with a common output. Each diode is operated in a limited Geiger- Müller
More informationRealizing Waveform Characteristics up to a Digitizer s Full Bandwidth Increasing the effective sampling rate when measuring repetitive signals
Realizing Waveform Characteristics up to a Digitizer s Full Bandwidth Increasing the effective sampling rate when measuring repetitive signals By Jean Dassonville Agilent Technologies Introduction The
More informationQUICK START GUIDE FOR DEMONSTRATION CIRCUIT /12/14 BIT 10 TO 65 MSPS DUAL ADC
LTC2286, LTC2287, LTC2288, LTC2290, LTC2291, LTC2292, LTC2293, LTC2294, LTC2295, LTC2296, LTC2297, LTC2298 or LTC2299 DESCRIPTION Demonstration circuit 816 supports a family of s. Each assembly features
More informationAbout... D 3 Technology TM.
About... D 3 Technology TM www.euresys.com Copyright 2008 Euresys s.a. Belgium. Euresys is a registred trademark of Euresys s.a. Belgium. Other product and company names listed are trademarks or trade
More information5G New Radio Technology and Performance. Amitava Ghosh Nokia Bell Labs July 20 th, 2017
5G New Radio Technology and Performance Amitava Ghosh Nokia Bell Labs July 20 th, 2017 1 Performance : NR @ sub 6 GHz 2 Motivation: Why 5G New Radio @ sub 6GHz Ubiquitous coverage for mmtc and URLLC Access
More informationTechnical Article MS-2714
. MS-2714 Understanding s in the JESD204B Specification A High Speed ADC Perspective by Jonathan Harris, applications engineer, Analog Devices, Inc. INTRODUCTION As high speed ADCs move into the GSPS range,
More informationLogic Analysis Basics
Logic Analysis Basics September 27, 2006 presented by: Alex Dickson Copyright 2003 Agilent Technologies, Inc. Introduction If you have ever asked yourself these questions: What is a logic analyzer? What
More informationTerahertz focal plane arrays for astrophysics and remote sensing
Terahertz focal plane arrays for astrophysics and remote sensing Christopher Groppi Arizona State University School of Earth and Space Exploration Emission at 115 GHz from the CO molecule was first detected
More informationBenchtop Portability with ATE Performance
Benchtop Portability with ATE Performance Features: Configurable for simultaneous test of multiple connectivity standard Air cooled, 100 W power consumption 4 RF source and receive ports supporting up
More informationLogic Analysis Basics
Logic Analysis Basics September 27, 2006 presented by: Alex Dickson Copyright 2003 Agilent Technologies, Inc. Introduction If you have ever asked yourself these questions: What is a logic analyzer? What
More informationThe hybrid photon detectors for the LHCb-RICH counters
7 th International Conference on Advanced Technology and Particle Physics The hybrid photon detectors for the LHCb-RICH counters Maria Girone, CERN and Imperial College on behalf of the LHCb-RICH group
More informationFRONT-END AND READ-OUT ELECTRONICS FOR THE NUMEN FPD
FRONT-END AND READ-OUT ELECTRONICS FOR THE NUMEN FPD D. LO PRESTI D. BONANNO, F. LONGHITANO, D. BONGIOVANNI, S. REITO INFN- SEZIONE DI CATANIA D. Lo Presti, NUMEN2015 LNS, 1-2 December 2015 1 OVERVIEW
More informationCommissioning and Initial Performance of the Belle II itop PID Subdetector
Commissioning and Initial Performance of the Belle II itop PID Subdetector Gary Varner University of Hawaii TIPP 2017 Beijing Upgrading PID Performance - PID (π/κ) detectors - Inside current calorimeter
More informationCMS Conference Report
Available on CMS information server CMS CR 1997/017 CMS Conference Report 22 October 1997 Updated in 30 March 1998 Trigger synchronisation circuits in CMS J. Varela * 1, L. Berger 2, R. Nóbrega 3, A. Pierce
More informationData Converters and DSPs Getting Closer to Sensors
Data Converters and DSPs Getting Closer to Sensors As the data converters used in military applications must operate faster and at greater resolution, the digital domain is moving closer to the antenna/sensor
More information