Lab 13: FPGA Circuit Realization Ian Callahan

Transcription

1 Callahan 1 Lab 13: FPGA Circuit Realization Ian Callahan (ipc8@pitt.edu) Purpose The goal of this lab was to implement the circuit description from Lab 12 and implement it on a Field Programmable Gate Array (FPGA). A FPGA is a single chip that is capable of realizing various chips at once. FPGAs contain several different programmable logic blocks and a system of reconfigurable connections that allow all of the blocks to be wired together (Wikipedia). FPGAs are capable of very simple operations, like AND, XOR, and addition, as well as complex operations, such as flip-flops and blocks of memory. For this lab, the FPGA can be configured to do operations that are based off of inputs and code by the user. The user can use switches or push buttons to input data into the system, and the FPGA can display the results through several LEDs. In this lab, we set out to create an ALU on the FPGA. To do so, we had to create pin assignments for each of the inputs. We also had to write VHDL code for some of the circuit components. We had to test the FPGA to ensure that the circuit was able to produce the same results as that of Lab 12. We were able to upload the code of instructions to the FPGA through a USB cable. The procedure for the lab was as follows: Procedure 1. First we uploaded the files we created from Lab 12 and created a new project on Quartus II. We used these files as a basis for creating our FPGA circuitry. We also copied the file N:\MaxLab\addons\DispBin.vhd into the folder with all of the files needed. 2. Next, we replaced the 4- bit latch using 7474 D flip-flops with a single latch component. We then updated the schematic. We also removed the 7-segment displays from our schematic. 3. Now we began to program the FPGA. To program the FPGA, we needed to complete the following steps: a. We had to return to our main schematic. b. We had to choose the following path of Quartus II: File Project Set Project to Current File c. Next, we had to choose Assign Device. i. We selected Device Family = CycloneII. ii. We selected Device = EP2C35F672C6. d. We then compiled the schematic. e. Finally, we clicked start. 4. The next step that we had to complete was to specify the pins on the FPGA chip that would be associated with the inputs and outputs of our design. To assign the pins, we had to do the following: a. Choose Assign Assignment Editor. b. In Category we had to choose Pin. c. We then double clicked the entry in the To column to choose the port name for our design.

2 Callahan 2 d. We the double clicked the entry in Location column to choose the pin number on the FPGA chip. e. We repeated c and d for all of our pin assignments. 5. For the lab, we had to assign certain inputs and outputs to specific things. The inputs had to all be programmed to either toggle switches or pushbuttons along the bottom of the Altera DE2 board. The pushbuttons are normally high. We had to have the results outputted through two of the LEDs on the chip and we had to have the read and write addresses displayed by two LEDs. 6. With all of the pins assigned, it was time to upload the program to the FPGA for testing. We got an Altera DE2 board, an AC adapter for power, and a USB cable to connect the chip to the computer. We switched the RUN-PROG switch to the RUN position. In Quartus II, we choose Tools Programmer. We chose the FPGA as the hardware and chose JTAG mode. Finally, we clicked Add File to select our project.sof file and clicked start. We tested the FPGA to ensure functionality. 7. With the ALU circuit loaded and tested on the FPGA, we began to replace parts of the schematic with VHDL code. We began by generating the code for the decoder for the 7- segment displays. We deleted one of the 7-segment decoder from the schematic and replaced it with the DispBin.sym that we were given. Once we compiled and tested the new program, we replaced the other 7-segment decoder with the VHDL code. 8. Next, we edited the VHDL code for the decoders so that it shows the hexadecimal characters A, b, C, d, E, and F to represent 10 through 15. We then we re-simulated the ALU and verified operation on the FPGA. 9. With the decoder functioning, we replaced the 4x2:1 multiplexer, 4-bit latch, and address counters with VHDL that we wrote. We wrote the code, compiled it, created a symbol for it, and intergrated it into the circuitry. After each part was replaced, we tested the waveform, uploaded the code to the FPGA, and verified operation. Results For this lab, there are no circuit elements. The only thing used is an Altera DE2 board. We began by uploading the schematic and waveform from Lab 12. The circuit schematic is shown in Figure 1. The waveform is shown in Figure 2. Figure 1: This figure illustrates the schematic created in Quartus II from Lab 12.

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4 Callahan 4 Figure 2: These illustrates the circuit performing four different operations based on the schematic from Lab 12. With the files uploaded, we assigned the pins for the FPGA. Toggle switches were used for the following inputs: CLR, DN, L_EN, Din[3..0], S[3..0], Cn, M, and In_Sel. Pushbuttons were used for W_UP, R_UP, and W_EN. LEDs were used to display the write address and the read address. 7-segment LED displays were used to display the output of the register and the result of the ALU. Table 1 shows the inputs, signal names, pin numbers and pin descriptions for the FPGA. Input Signal Name Pin Number Pin Description CLR SW[0] PIN_N25 Toggle Switch[0] DN SW[1] PIN_N26 Toggle Switch[1] L_EN SW[2] PIN_P25 Toggle Switch[2] D[0] SW[3] PIN_AE14 Toggle Switch[3] D[1] SW[4] PIN_AF14 Toggle Switch[4] D[2] SW[5] PIN_AD13 Toggle Switch[5] D[3] SW[6] PIN_AC13 Toggle Switch[6] S[0] SW[7] PIN_C13 Toggle Switch[7] S[1] SW[8] PIN_B13 Toggle Switch[8] S[2] SW[9] PIN_A13 Toggle Switch[9] S[3] SW[10] PIN_N1 Toggle Switch[10] Cn SW[11 PIN_P1 Toggle Switch[11] M SW[12] PIN_P2 Toggle Switch[12] In_Sel SW[13] PIN_T7 Toggle Switch[13] W_UP KEY[0] PIN_O26 Pushbutton[0] R_UP KEY[1] PIN_N23 Pushbutton[1] W_EN KEY[2] PIN_P23 Pushbutton[2] LED1[0] HEX0[0] PIN_AF10 Seven Segment Digit 0[0] LED1[1] HEX0[1] PIN_AB12 Seven Segment Digit 0[1] LED1[2] HEX0[2] PIN_AC12 Seven Segment Digit 0[2] LED1[3] HEX0[3] PIN_AD11 Seven Segment Digit 0[3] LED1[4] HEX0[4] PIN_AE11 Seven Segment Digit 0[4] LED1[5] HEX0[5] PIN_V14 Seven Segment Digit 0[5] LED1[6] HEX0[6] PIN_V13 Seven Segment Digit 0[6] LED2[0] HEX1[0] PIN_V20 Seven Segment Digit 1[0] LED2[1] HEX1[1] PIN_V21 Seven Segment Digit 1[1] LED2[2] HEX1[2] PIN_W21 Seven Segment Digit 1[2]

5 Callahan 5 LED2[3] HEX1[3] PIN_Y22 Seven Segment Digit 1[3] LED2[4] HEX1[4] PIN_AA24 Seven Segment Digit 1[4] LED2[5] HEX1[5] PIN_AA23 Seven Segment Digit 1[5] LED2[6] HEX1[6] PIN_AB24 Seven Segment Digit 1[6] WQ[0] LEDG[7] PIN_Y18 LED Green[7] WQ[1] LEDG[8] PIN_Y12 LED Green[8] RQ[0] LEDG[5] PIN_U17 LED Green[5] RQ[1] LEDG[6] PIN_AA20 LED Green[6] Table 1: This table illustrates the inputs, signal names, pin numbers and pin descriptions for the FPGA. With the pin assignments completed, we began to replace parts of the schematic with the VHDL equivalent. We started by replacing the LED decoders with the VHDL given to us. The code is shown in Figure 3. We then modified the code so that the code displays hexadecimal characters. That code is shown in Figure 4. We tested the code after both changes and the waveform from Figure 2 did not change. Figure 3: This figure shows the original VHDL code for the LED decoder.

6 Callahan 6 Figure 4: This figure illustrates the VHDL code for the modified LED decoder. After we replaced the decoder, we wrote the VHDL code for the multiplexer. To write the code for the multiplexer, we first wrote code for one multiplexer and then wrote code for a 4x2:1 multiplexer. Figure 5 shows the code for the single multiplexer and Figure 6 shows the code for the implemented multiplexer. The waveform from Figure 2 did not change by implementing the VHDL code.

7 Callahan 7 Figure 5: This figure shows the VHDL code for a single multiplexer. Figure 6: This figure shows the VHDL code for the 4x2:1 multiplexer. Next we created the VHDL code for the 4-bit latch. We created the code for a single latch and implemented it in the code for a 4-bith latch. Figure 7 illustrates the code for the single latch and Figure 8 illustrates the code for the 4-bit latch. The schematic and the FPGA were tested and there was no change in the waveform from Figure 2 or with the functionality of the FPGA.

8 Callahan 8 Figure7: This figure shows the code for a single bit latch. Figure 8: This figure shows the VHDL code for the 4-bit latch. Finally, we created the VHDL code for the address counters. Figure 9 illustrates the code for the address counters. The schematic and the FPGA were tested and there was no change in the waveform from Figure 2 or with the functionality of the FPGA.

9 Callahan 9 Figure 9: This figure illustrates the VHDL code for the address counters. The final schematic that was uploaded to the FPGA is shown in Figure 10. The FPGA and the waveform shown in Figure 2 did not change functionality at any point of the changes. The waveforms were not shown after each testing in this report due to redundancy. Figure 10: This figure illustrates the final schematic with all of the VHDL equivalent circuits. Conclusion The purpose of this lab was to recreate an ALU by using an FPGA. To do so, we uploaded the schematic and waveform from Lab 12. We then assigned inputs and outputs of the schematic to the FPGA. We replaced parts of the program with VHDL code. After each part of the schematic was replaced, the waveform and the FPGA were tested to ensure functionality. In the end, the FPGA produced the same output as the ALU from Lab 12. Professor Helen Li s lecture slides References

10 Callahan 10 "Field Programmable Gate Array." Wikipedia. Wikimedia Foundation. Web. 19 Apr Lab Partner: Brandon Jones