PROCESSOR BASED TIMING SIGNAL GENERATOR FOR RADAR AND SENSOR APPLICATIONS

Transcription

1 PROCESSOR BASED TIMING SIGNAL GENERATOR FOR RADAR AND SENSOR APPLICATIONS Application Note

2 ABSTRACT... 3 KEYWORDS... 3 I. INTRODUCTION... 4 II. TIMING SIGNALS USAGE AND APPLICATION... 5 III. FEATURES AND IMPLEMENTATION... 6 IV. IMPLEMENTATION RESULTS V. CONCLUSION VI. REFERENCES VII. AUTHOR PROFILE:

3 ABSTRACT The objective of this paper is to present the architecture design and implementation of an Application Specific Processor based hardware module called Timing Signal Generator (TSG) for pulsed RADAR (Radio Detection and Ranging) and Image Sensor applications. It is a digital, programmable, application-specific, control timing signal generator. This module is a slave controller which receives configuration and instructions through 16 bit simple user interface. Depending on the instructions a control signal is generated for a fixed duration or ever lasting repetitive one. It is designed, implemented and validated using Very High Speed Integrated Circuit (VHSIC) Hardware Description Language (VHDL) on Xilinx Kintex 7 Field Programmable Gate Array (FPGA) 7k325tffg The simulation results using Questasim simulator and the timing signals captured in the FPGA using Xilinx Chipscope Logic analyzer verify the effectiveness of the implemented TSG. KEYWORDS FPGA, RADAR, PRI, Image Sensors, Application Specific Processor, Timing Signal Generator. 3

4 I. INTRODUCTION Timing signals are control signals which indicate either the start or end of certain events like enabling disabling of systems, windowing for data to be captured, read or write operations or sequence of control signals. Timing signals are generated in the hardware depending on the system requirements. If the requirements change hardware needs to be changed, which further increases the design and verification efforts. In order to counter this limitation, this paper proposes application specific, two stage pipelined, and processor based implementation of timing signal generation. Required timing signal is generated by the processor depending on the instruction given to it. Thus, if the requirements change then the only change required will be the change of instructions and not of the hardware. Moreover TSG implemented has the capability to change the timing signals on the fly by just changing the instructions in the instruction memory. The paper is organized as follows: Section II describes the usage and applications of timing signals. Section III describes its design and implementation. Section IV provides simulation and hardware results. Conclusions are detailed in Section V. 4

5 II. TIMING SIGNALS USAGE AND APPLICATION Pulsed RADAR has following basic control timing signals as shown in figure 1 repeated at a Pulse Repetitive Interval (PRI) rate. Tx pulse marks the duration of transmission of a pulse of electromagnetic waves during a designated time slot. Tx Control is an extended TX pulse having front and back porch extensions to take care of rise time requirements of the Travelling Wave Tube Amplifier (TWTA) transmitting the amplified modulated electromagnetic waves as well as to protect receiver by removing receiver input through a switch during this period. Rx Data window is the time window with a precisely defined timing relationship with the transmitted pulse to receive the echo back. In addition to these basic signals, depending on the requirements there are other intra-pri calibrations timing pulses. In case of beam-steered antennas, beam switching signals are also required. Front Porch Tx_pulse Back Porch PRI Tx_control Rx_window Intra_PRI_pulses Figure 1 RADAR Timing Signals Diagram Camera gets the capture command and the image sensor is exposed by the exposure window. Strobe pulse provides the sensor with the illumination and finally at the exposure conclusion, the image from the sensor is transferred to the frame grabber. Capture Command Exposure strobe Charge transfer Video output Figure 2 Camera Timing Signals Diagram Timing signals are responsible for controlling the digital subsystems. For many systems timing signals changes from application to application. And in some systems it is required to change them on the fly. For an instance in above two examples, in case of radars the echo relation with respect to the transmitted pulse changes from object to object. In case of camera the exposure and illumination time duration and relation can change. Considering all this a processor based generic timing signal generator is proposed and implemented. 5

6 III. FEATURES AND IMPLEMENTATION A. TSG Architectures TSG designed is capable of generating Timing signals of programmable widths, programmable polarity, synchronous to rising and falling edges of any signal, generating pulses with sync divider capability, generating pulses with variable widths at every sync or repetitive syncs. Timing signal having frequency half of TSG clock can also be generated. It is also possible to change Timing signals on-the fly by changing the instructions. Each Timing signal is generated by an Application Specific TSG Processor depending on the instruction given to it. The user interface to configure the TSG is designed to support maximum of 16 processors and thus 16 timing signals. User interface can be modified to support any no of processors. The block diagram of the Timing Signal Generator (TSG) with a specific case of 8 TSG processors is shown in the figure 3 below. There is an array of 8 RAMs each of 24 x 64, associated with each processor. RAM holds the 21 bit instructions to be executed by the processors. Each processor has a capability to generate an independent timing signal without a sync reference or generate a timing signal with respect to 2 input sync signals. The two input sync signals can be generated either from external sync or internally by any of the other TSG processor. In figure 3, one of the TSG processor takes the role of generating sync pulses. The other 7 processors generate timing signals which are either free running or synchronized to sync depending upon the instruction fed to it. There is a register bank of 9 registers. In all, these 9 registers forms 10, 16 bit registers. User interface which is simple 16 bit read-write interface communicates with this register bank. Control register, current sync register, instruction register, index register, on-off value register and on-off index register are common to all the eight processors, while each bit of ram chip select register, update register and hardware update mask register corresponds to each of the 16 processors. Instruction from the instruction register is loaded to the ram location pointed by instruction index register into all the Rams whose chip select bit is enabled. Processors Program Counter is reset to 0 and it stops executing instruction whenever its corresponding chip select bit is enabled. It starts fetching and executing instruction when global enable bit in control register is 1 and its corresponding chip select bit is 0. TSG also has 8, 16 bit off and 8, 16 bit on count registers. Value in the off on register is written to one of these 16 register as indicated by the value in off on index register. Each of the off and on count values corresponds to one of the eight processors. Each processor updates their off and on count values whenever update bit is set in the update register or on rising edge of the hardware update signal. Update from hardware signal by each processor can be masked by setting their respective bit in hardware update mask register. 6

7 Din[7:0] addr[15:0] dout[7:0] clk Reset_n rd wr cs clk_tsg Sync_tsg_in Control Reg Current Sync Reg Instruction Reg Instruction Index Reg Ram chip select reg Off-On Value Reg Off-On Index Reg Update Reg Hw Update Mask Reg u-controller clock domain synchronizer s Micro controller Interface. Sync mux Off_on_value [15:0] Crnt sync no [15:0] Off_on_index [7:0] Offon_update Hw_updt_mask en Sync_tsg_dir TSG clock domain synchronize rs Sync counter Sync 2 flops TSG Top Update_sw2 Hw_updt_msk2 Instruction [23:0] Inst_index [7:0] Ram_cs0 Ram_cs1 Ram_cs2 Ram_cs3 Ram_cs4 Ram_cs5 Ram_cs6 Ram_cs7 Off_count0, on_count0 Off_count1, on_count1 8 off Off_count2, on_count2 reg[15:0] Off_count3, on_count3 & Off_count4, on_count4 8 on Off_count5, on_count5 reg[15:0] Off_count6, on_count6 Off_count7, on_count7 enable Enable_rising sync1 sync2 Off_count0 On_count0 Ram_cs0 Off_count1 On_count1 Ram_cs1 Off_count2 On_count2 Ram_cs2 Off_count3 On_count3 Ram_cs3 Off_count4 On_count4 Ram_cs4 Off_count5 On_count5 Ram_cs5 Sync Processor TSG Processor 1 TSG Processor 2 TSG Processor 3 TSG Processor 4 TSG Processor 5 Instr_in0[23:0] Addr0[5:0] Instr_in1[23:0] Addr1[5:0] Instr_in2[23:0] Addr2[5:0] Instr_in3[23:0] Addr3[5:0] Instr_in4[23:0] Addr4[5:0] Instr_in5[23:0] Addr5[5:0] RAM 0 RAM 1 RAM 2 RAM 3 RAM 4 RAM 5 Inst_Index[5:0] Ram_cs0 Inst_Index[5:0] Ram_cs1 Inst_Index[5:0] Ram_cs2 Inst_Index[5:0] Ram_cs3 Inst_Index[5:0] Ram_cs4 Inst_Index[5:0] Ram_cs5 SYNC Sig_out1 Sig_out2 Sig_out3 Sig_out4 Sig_out5 External_sig Update_external Ex_sig 2 flops Update external 2 flops Update_ex1 Update_ex2 Update Ex_sig1 Ex_sig2 Update Off_count6 On_count6 Ram_cs6 Off_count7 On_count7 Ram_cs7 TSG Processor 6 TSG Processor 7 Instr_in6[23:0] Addr6[5:0] Instr_in7[23:0] Addr7[5:0] RAM 6 RAM 7 Inst_Index[5:0] Ram_cs6 Inst_Index[5:0] Ram_cs7 Sig_out6 Sig_out7 Control Register (TSG_CNTL) Figure 3 TSG Block Diagram with 8 TSG processors Its zeroth bit if 1, enable the TSG else disable it. Its first bit is for sync selection. If 0-External sync is used then 1-Internal sync from sync processor will be used for timing signal generation. Current sync number (TSG_STS) This register gives current sync number of the sync generated by sync generator module. When the TSG is enabled this register count is incremented on every sync cycle else its value is 0. Instruction Register (TSG_INSTR_15_0, 23_16) 7

8 These two 16 bit registers forms the 21 bit instruction code to be loaded into instructions ram at location given in the Instruction Index Register. Instruction Index Register (TSG_ INSTR _INDEX) This register provides the location of ram where the Instruction in the two instruction registers has to be loaded. Ram chip select Register (TSG_RCS) Each bit of this register provides the chip select for the 16 Instruction rams. Instruction from the Instruction register is written to the ram whose chip select bit is high at the location pointed by Instruction index register. Off-On Value Register (TSG_OFFON) 16 bit Off or On count value. Off-On Index Register (TSG_OFFON _INDEX) This register provides the location of one of the register out of 32 (16 for off and 16 for on) where the off or on value corresponding to each processor has to be loaded. Update Register (TSG_ UPDATE) Each bit of this register provides the off - on count values update signal for the 16 TSG Processors. When its 1 off on counts are updated by respective TSG Processor then the TSG processors clears them after the update. This register provides software update control in addition to the hardware update signal. Hardware update mask Register (TSG_HWUDMSK) Each bit corresponds to each of the 16 TSG Processors. This bit provides masking of the hardware update signal. If set to 1 off and on count values are updated only on corresponding software update bit and hardware update is neglected. B. TSG Processor TSG processor is an application specific 16 bit - RISC processor which outputs a timing signal. It is a Two stage pipelined processor with stages: 1) Instruction fetch and 2) Instruction Decode and Execute. It is designed to generate timing signals of variable no of pulses, of variable pulse widths and of variable periods which are either free running or synchronized with sync signals. It has 15 different instructions out of which 5 are data load instructions, 4 event waiting, 2 count waiting instructions, 3 jump instructions and 1 permanent wait instruction. These 15 instructions are of 5 types: 5 data load instructions are single clock executable, 4 event waiting instructions and 2 count wait instructions causes the processor to enter into halt state until the event happens or count completes, 3 jump instructions causing processor to fetch next instruction from jump address and permanent wait instruction causes the processor to enter into permanent halt. Instruction format is shown in figure 4, while detailed explanation of each instruction is shown in table 1. It has 8, 16 bit 8

9 dedicated counters for counting events, to generate delay and for looping purposes. As each TSG signal is generated and updated by the processor independently without affecting others, it makes the TSG very generic. Detailed architecture diagram is shown in figure 5. Figure 4 Instruction Format Instruction Mnemonic Opcode Instruction Usage Wait for sync rising edge * No S WSRE0 No 0 (0/1) (0000) (16bit no) Wait for sync falling edge * No S WSFE0 No 1 (0/1) (0001) (16bit no) Wait for sync falling edge * No S WSFE0 No 1 (0/1) (0001) (16bit no) Wait for sync1 rising edge * No S WSRE1 No 2 (0/1) (0010) (16bit no) Wait for sync1 falling edge * No S WSFE1 No 3 (0/1) (0011) (16bit no) Wait for on count S WONC 4 (0/1) (0100) (16 0 s) Wait for off count S WOFC 5 (0/1) (0101) (16 0 s) Signal value set S V 6 (0/1) (0110) (16 0 s) On count load value S ONCL Val 7 (0/1) (0111) (16bit value) Off count load value S OFCL Val 8 (0/1) (1000) (16bit value) Generic count load value S GCL0 Val 9 (0/1) (1001) (16bit value) Generic count1 load value S GCL1 Val A (0/1) (1010) (16bit value) Jump to Address S JMP Addr B (0/1) (1011) (10 0 s, 6 bit addr) Decrement generic count, Jump if not zero to given address else to nxt address Decrement generic count1, Jump if not zero to given address else to nxt address S DJNZ0 Addr C (0/1) (1100) (10 0 s, 6 bit addr) S DJNZ1 Addr D (0/1) (1101) (10 0 s, 6 bit addr) Wait S W E (0/1) (1110) (16 0 s) TABLE 1: Instructions 9

10 TSG Processor 16 bit - 2 Stage Pipelined, Application Specific RISC processor Ex_reset Clk_tsg Off_count On_count Ram_cs Enable Reset synchronizer U cntrl clk to TSG clk synchronizers Off_count2 On_count2 Ram_cs2 off_cnt_dn on_cnt_dn gen_cnt_dn gen_cnt_dn1 sync_rise_dn sync_fall_dn Exsig_rise_dn Exsig_fall_dn opcode Jump _addr PC Increment PC PC reg Addr[5:0] Instruction Fetch Update Update Update1 synchronized to sync Off count load Off_count_p Off counter opcode off_cnt_dn Off_count_instr Enable_rising sync1 sync2 On count load On_count_p opcode On counter generic counter generic counter1 Sync rise counter Sync fall counter Off_count_instr opcode on_cnt_dn Generic_cnt gen_cnt_dn Generic_cnt1 gen_cnt_dn1 sync_rise_dn sync_fall_cnt sync_fall_dn sync_rise_cnt opcod e Off_count_ instr On_count_instr Generic_cnt Generic_cnt1 Jump_ addr sync_fall_cnt Exsig_ rise_ cnt Exsig _fall_ cnt Instruction decoder Sig_out Instruction Decode & Execute exsig1 exsig2 exsig rise counter Exsig_rise_cnt Exsig_rise_dn exsig fall counter Exsig_fall_cnt Exsig_fall_dn Figure 5 TSG Processor C. TSG Capabilities 1. Sync generation continuous or for fix numbers with variable pulse widths Figure 6 - Timing Signal Type 1 Instruction continuous sync generation: 1 WONC 0 WOFC 0 JMP 0 Instruction sync generation for 9 numbers: 0 GCL0 8 0 WOFC 1 WONC 0 DJNZ0 1 0 W 10

11 2. Timing Signal generation with respect to rising or falling edge at every sync or in multiples of sync with off and on programmability Instructions timing signal 1: 0 WSFE0 0 0 WOFC 1 WONC 0 JMP 1 Instructions timing signal 2: 1 WSRE0 1 1 WONC 0 WOFC 1 JMP 1 Figure 7 - Timing Signal Type 2 3. Timing Signal which remains high for x numbers and low for y numbers of sync Instructions timing signal: 0 WSRE0 1 1 WSRE0 2 0 JMP 0 Figure 8 - Timing Signal Type 3 11

12 4. Timing Signal generated for x numbers and not for y numbers of sync Instructions timing signal: 1 GCL0 3 1 WSFE0 0 1WONC 0 WOFC 1 DJNZ 1 1 WSFE0 2 1 JMP 1 Figure 9 - Timing Signal Type 4 5. Timing signal generation with variable no of pulses with variable pulse widths at every sync or in multiple of sync Instructions timing signal: 0 GCL0 3 0 WSFE0 0 1WONC 0 WOFC 0 DJNZ 2 0 WSFE0 0 0 JMP 0 Figure 10 - Timing Signal Type 5 12

13 IV. IMPLEMENTATION RESULTS A. Simulation result: Figure 11 - Timing signals simulation waveform Figure 11 shows simulated waveform for eight timing signals generated by their respective eight processors. Sync_tsg_out is the sync signal generated by a TSG processor. Sig_out 2 to 6 are timing signals generated by five TSG processor in a relation with Sync_tsg_out signal. Sig_out 0 and 1 are random control signals having no relation with any sync signal. B. Synthesis Report - Device utilization summary Kintex 7: Device utilization summary for a TSG processor is as below: Slice Logic Utilization: Number of Slice Registers 167 out of % Number of Slice LUTs 263 out of % Number used as Logic: 263 out of % Slice Logic Distribution: Number of LUT Flip Flop pairs used 263 Number with an unused Flip Flop 96 out of % Number with an unused LUT 0 out of 263 0% Number of fully used LUT-FF pairs 167 out of

14 Device utilization summary for the architecture of figure 3 consisting of 8 processors is as below: Slice Logic Utilization: Number of Slice Registers 1047 out of % Number of Slice LUTs 1416 out of % Number used as Logic 1416 out of % Slice Logic Distribution: Number of LUT Flip Flop pairs used 1500 Number with an unused Flip Flop 453 out of % Number with an unused LUT 84 out of % Number of fully used LUT-FF pairs 963 out of % Specific Feature Utilization: Number of Block RAM/FIFO 8 out of 445 1% Number using Block RAM only 8 C. Chipscope Analyzer result: Figure 12 - Timing signals Chipscope Analyzer waveform 14

15 V. CONCLUSION Design and implementation of Application Specific, 2 stage pipelined, processor based control timing signal generator is discussed and explained in detail. Architecture of the processor is discussed with its various instructions and their formats. The main advantage of processor based TSG is its configurability, as it can be used to generate any timing signal which is either free running or in relation to some external sync signals. Moreover any change in timing requirements can be easily implemented on the fly by just changing the instructions instead of changing the hardware. Verification results through simulation waveform shows its effectiveness in generating timing signals. TSG validated in Xilinx Kintex 7 FPGA by capturing and observing the timing signals in the Xilinx Chipscope analyzer confirms the simulation results. Device utilization summary indicates that the implemented processor based TSG is highly hardware efficient consuming only 167 registers and 263 LUTs per processor. Configurable timing signal generation capability, fewer and easy assembly codes, fewer hardware resources, pipelined real time performance, excellent precision and capability of generating timing signal half of clock frequency makes the processor based TSG highly efficient and useful for control timing signals generation for any applications. 15

16 VI. REFERENCES [1] Mrs. Anudeepa S. Kholapure,Dr. Arvind Agarwal, Mrs. Shikha Nema, Design of a Timing Signal Generator (TSG) for RADAR using FPGA, Second International Conference on Emerging Trends in Engineering and Technology, ICETET-09. [2] John L. Hennessy and David A. Patterson, Computer Architecture A Quantitative Approach, 4th ed., Morgan Kaufmann Publishers, 2011 [3] Petar Borisov Minev, Valentina Stoianova Kukenska, Implementation of Soft-Core Processors In FPGAs, International Scientific Conference, November 2007, GABROVO. [4] Xilinx Kintex 7 Data Sheet, DS182 (v2.9) June 20, [5] Xilinx KC705 Evaluation Board User Guide, UG810 (v1.5) July 11, 2014 VII. Author Profile: Mufaddal Saifee works at einfochips as Senior Engineer. Mufaddal has experience in ASIC and FPGA design cycle. He has worked on complete FPGA system implementation flow covering micro-architecture design, RTL coding, gate level simulation, synthesis, PAR and timing closure. He has designed and implemented various Pipelined Application Specific Processors. He has worked on variety of projects covering applications in domains like video processing, networking, DSP and TMR-Avionics. 16