CXA2006Q. Digital CCD Camera Head Amplifier

Transcription

1 Digital CCD Camera Head Amplifier CXA2006Q Description The CXA2006Q is a bipolar IC developed as a head amplifier for digital CCD cameras. This IC provides the following functions: correlated double sampling, AGC for the CCD signal, GCA for the lowband chroma signal, AMP for high-band chroma and line signals, A/D sample and hold, blanking, A/D reference voltage, and an output driver. 32 pin QFP (Plastic) Features High sensitivity made possible by a high-gain AGC amplifier Blanking function provided for the purpose of calibrating the CCD output signal black level Regulator output pin provided for A/D converter reference voltage Built-in GCA and AMP for amplifying video signals (chroma and line signals) from external sources Built-in sample-and-hold circuits (for camera signals and for video signals) required by external A/D converters Absolute Maximum Ratings Supply voltage VCC 14 V Operating temperature Topr 20 to +75 C Storage temperature Tstg 65 to +150 C Allowable power dissipation PD 640 mw Operating Conditions Supply voltage VCC1, 2, to 5 V Applications Digital CCD cameras Structure Bipolar silicon monolithic IC Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. 1 E94X41B8X-PS

2 CAM/VIDEO PB/REC CH/C PS VSHP 3 OUTCP DRVOUT CPDM 1 SHD SHP VCC1 CCDEVE AGCCONT N.C. CXA2006Q Block Diagram and Pin Configuration PIN AGCCP DIN 26 SH1 SH2 SH3 AGC PF AGCCP CAMSH BK 15 CPOB VCC2 27 COSCP1 14 XRS N.C. 28 COSCP2 REF BOTTOM REF TOP 13 PBK IN/CH IN CP CENTER BIAS IN/CH SW AMP VI SW VISH C/V SW OFFSET SW OFFSET VRT RFCONT 31 CH/C DC VRB CENTER BIAS GCA DRV PBRFC 32 9 VCC3 MODE SWITCHING OUTCP

3 Pin Description Pin No. (VCC1, 2, 3 = 4.75V) Symbol Pin voltage Equivalent circuit Description 1 CAM /VIDEO 25µA 25µA Camera and video signal selector. 2 PB/REC 3 CH/C VTH = 1.35V k 1.35V 24k 27k Chroma signal and composite video signal selector. High-band chroma signal and low-band chroma signal selector. 4 PS Power save mode. Sampling 16.25k 5 VSHP VTH = 1.32V V Sample-and-hold pulse input for video. Sampling 2mA 6.25k 400µA Ground. 7 OUTCP Approx. 2V 4µA 66k 1.27V 0µA 200µA 16k 24k 1.1k 0k 7 Capacitor connection for OUTCP which clamps the output minimum level in modes which pass the composite video signal. (Recommended value: 0.1µF) 3

4 Pin No. Symbol Pin voltage Equivalent circuit Description 0µA 4mA 8 DRVOUT Camera mode (CAM) VRB 200mV < black level < VRB + 300mV Composite video mode (IN) VRB + 0mV Chroma mode (CH, C) Center voltage = (VRT VRB)/2 1.5mA SW mA 2.1V SW2 8 DRVOUT 30k p Driver output for A/D converter capable of DC coupling. Dynamic range = 2Vp-p SW1 SW Mode CH, C CAM IN OFFSET 0: Closed 1: Open VCC3 VCC1 VCC2 VCC Power supply. 2V regulator output. VRB 2.0V 2V 13.75k 2k 0µA Be sure to decouple this pin near the IC pins to prevent the oscillation and external noise when this pin is not used. (Recommended capacitor value: 4.7µF) 11 VRT 4.0V 4V 3.75k 20k 0µA 1.1k 0µA 3k 0µA 11 4V regulator output. Be sure to decouple this pin near the IC pins to prevent the oscillation and external noise when this pin is not used. (Recommended capacitor value: 4.7µF) 4

5 Pin No. Symbol Pin voltage Equivalent circuit Description 66k 0µA 0µA Controls the output offset during camera mode. 12 OFFSET 0 to 24k 23k 1.1k 12 When 0V: less than (VRB 200mV) When 3.0V: greater than (VRB + 300mV) 25µA 25µA Camera signal preblanking pulse input. 13 PBK VTH = 1.35V Active: ow 13 24k 68k 1.35V 27k Active when ow only during camera mode. Calibrates the black level of the AGC output waveform. When PBK is ow, the DRVOUT potential is forced to 2V. VTH = 2.16V 12.25k XRS Sampling 2.16V.25k 5p 0µA 2.5mA Camera signal sample-and-hold pulse input. 15 CPOB VTH = 1.45V Active: ow k 0µA 66k 1.45V 29k Clamp pulse used to clamp the optical black portion of the camera signal after it passes through the AGC amplifier. 5

6 Pin No. Symbol Pin voltage Equivalent circuit Description 1.1k 2k 16 AGCCP Approx. 16 AGC clamp capacitor. (Recommended value: 0.1µF) 50µA 2k 20µA AGC gain control. 18 AGCCONT 0 to 3.0V 18 4k 20k 38k When 0V: 8dB (Minimum gain) When 3.0V: 38dB (Maximum gain) 40µA 40µA 20µA 20µA 20µA 20µA CCDEVE DIN input CCD signal black level: approx. 2.7V 40µA 19 Enables monitoring of the SHD output camera signal. 21 SHP VTH = 2.38V 2.38V 25k Preset level sampleand-hold pulse input. 22 SHD Sampling 25k 40µA 670µA Data level sampleand-hold pulse input. 6

7 Pin No. Symbol Pin voltage Equivalent circuit Description 1.1k 1.1k 66k 24 CPDM VTH = 1.45V Active: ow 24 85µA 85µA 1.45V 29k Clamp pulse used to clamp the dummy pixel portion of the input CCD signal PIN DIN Black level: approx. 2.7V µA µA 14k 36k 2k 2k CCD signal input. 1k IN/CH Clamp potential during IN mode: approx. 2.4V During CH mode: approx. 2.7V 2.1V 200µA 2.7V 19k IN mode 0µA 2µA 0µA Common input for the composite video signal (IN) and high-band chroma signal (CH). 26k CH mode 7

8 Pin No. Symbol Pin voltage Equivalent circuit Description 50µA 50µA 41k Gain control for the low-band chroma signal (C). 31 RFCONT 0 to 3.0V 31 1k 42k 50µA 50µA 0.86V 9k When 0V: 3.5dB (Minimum gain) When 3.0V: 15.5dB (Maximum gain) k 32 PBRFC Approx. 2.94V 0µA 0µA ow-band chroma signal (C) input. 46k 18k 41k 8

9 Electrical Characteristics (Ta = 25 C, VCC1, 2 and 3 = 4.5V, VCC4 = OPEN) Item Symbol Conditions Min. Typ. Max. Unit Camera mode IDC AGCCONT = 0V, open between VRT and VRB CAM/VIDEO =, PB/REC = 0V, CH/C = 0V, PS = Current consumption INE mode CH mode ID IDCH Open between VRT and VRB CAM/VIDEO = 0V, PB/REC = 0V, CH/C = 0V, PS = Open between VRT and VRB CAM/VIDEO = 0V, PB/REC =, CH/C =, PS = ma C mode IPC RFCONT = 0V, open between VRT and VRB CAM/VIDEO = 0V, PB/REC =, CH/C = 0V, PS = PS mode IDP PS = 0V 6 13 Maximum gain A CONT max. DIN = 1µs, mvp-p pulse AGCCONT = Minimum gain A CONT min. DIN = 1µs, 600mVp-p pulse AGCCONT = 0V 8 db AGC Range of gain variance Dynamic range maximum Dynamic range minimum AGC G AGCmax. D AGCmin. D A CON max. A CON min. AGCCONT = CPOUT output signal at saturation level AGCCONT = 0V CPOUT output signal at saturation level V DRV Offset high Offset low CAOF high CAOF low VCC1, 2, 3 = 4.75V, OFFSET = camera mode VCC1, 2, 3 = 4.75V, OFFSET = 0V camera mode mv VRT DC level VRTO VCC1, 2, 3 = 4.75V with a 400Ω load REF VRB DC level VRBO VCC1, 2, 3 = 4.75V with a 400Ω load V VRT VRB VR VCC1, 2, 3 = 4.75V with a 400Ω load BK Offset BKOF BKOF (PBK = ) BKOF (PBK = 0V) mv AMP IN mode gain CH mode gain IN G CH G IN/CH = 3MHz, 500mVp-p, sine wave + offset voltage IN/CH = 3MHz, 500mVp-p, sine wave GCA C mode maximum gain C mode minimum gain RF CONmax. RF CONmin. RFCONT = 15kHz 80mVp-p sine wave RFCONT = 0V 15kHz 400mVp-p sine wave db 9

10 CAM/ VIDEO PB/ REC CH/C PS VSHP 3 OUTCP DRVOUT CPDM 1 SHD SHP VCC1 CCDEVE AGCCONT N.C. CXA2006Q Electrical Characteristics Measurement Circuit P1 P2 P3 VCC1 4.75V V12 0 to C4 1µF AC V5 VCC2 4.75V AC V3 V1 0 to 4.75V AC V4 OFF ON PIN 25 C3 1µF DIN 26 C1 0.1µF C µF VCC2 IN/ CH V2 0 to RFCONT 27 N.C. SW PBRFC 32 SH1 IN CP COSCP1 COSCP2 CENTER BIAS CENTER BIAS SH2 SH3 GCA MODE SWITCHING AGC PF AGCCP CAMSH REF BOTTOM DRV BK REF TOP IN/CH SW VI SW C/V SW OFFSET SW AMP VISH OUTCP CH/C DC AGCCP CPOB XRS PBK OFFSET VRT R3 400 VRB VCC3 C7 0.1µ SW6 VCC3 4.75V P4 P5 P6 V15 0 to C9 4.7 µ OFF ON C8 4.7µ SW1 SW2 H H V7 V8 SW3 H V9 SW4 H V P7 C5 0.1µ R2 22 R1 20k V13 C6 25p SW1 SW2 SW3 SW5 SW4 MODE H H OFF CAM H H ON H IN H H H OFF C H H CH POWER SAVE

11 Measurement Timing Chart 2µs 1H P4 (CPOB) P1 (CPDM) 2µs 1H 1.5V 1.5V P6 (PBK) 1H 1.5V V5 (DIN) Different for each test Equivalent to CCD signal black level V3 (CH) V4 (PBRFC) V1 + V3 (IN) Different for each test P2 (SHD) P3 (SHP) P5 (XRS) P7 (VSHP) 2.5V 11

12 CAM/ VIDEO PB/ REC CH/C PS VSHP 3 OUTCP DRVOUT PBK XRS CPOB CPDM 1 SHD SHP VCC1 CCDEVE AGCCONT N.C. CXA2006Q Application Circuit CPDM SHD SHP VCC V12 0 to µF PIN AGCCP C7 0.1µ CCD 1µF VCC DIN VCC2 N.C SH1 SH2 SH3 COSCP1 COSCP2 AGC PF AGCCP CAMSH REF BOTTOM BK REF TOP CPOB XRS PBK IN/CH IN/CH µF to RFCONT 31 PBRFC PBRFC µF IN CP CENTER BIAS CENTER BIAS GCA MODE SWITCHING IN/CH SW VI SW C/V SW OFFSET SW AMP VISH DRV OUTCP CH/C DC OFFSET VRT VRB VCC3 VCC 0 to 4.7µF 4.7µF VRB VRT VSHP 0.1µ 22 A/D IN A/D Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. 12

13 Description of Operation 1. Camera signal processing system Process the video signal processing pins as follows only in camera mode. <5> VSHP... Connect to. <7> OUTCP... Connect to. <29> IN/CH... Connect to. <31> RFCONT... Connect to. <32> PBRFC... Connect to via the capacitor (approx. 0.01µF). Operating conditions The camera signal processing system operates when PS is high, CAM/VIDEO is low, PB/REC is low and CH/C is high, or when PS is high, CAM/VIDEO is high, PB/REC is low and CH/C is low. Camera signal processing system timing chart (when VCC = 4.75V) CCD output Sig interval OPB interval Idle transfer interval Sig interval Precharge level SHP SHD Signal level SH1 output SH2 output SH3 output CPDM (2µ dummy bit portion during the idle transfer interval) AGC output SH3 output N times SH2 output XRS CPOB (2µ during the OPB interval) Basic black level 2.16V [ 3] 2µs 2.7V [ 1] [ 2] 2.7V 2µs Black level CAMSH output PBK (µ during the idle transfer interval) 2.16V µs BK output CAMVISW output 2.16V [ 4] DRVOUT output [ 5] Approx. 2.65V when OFFSET = 13 Approx. 1.7 when OFFSET = 0V

14 CDS: The CCD signal from the CCD image sensor is input to PIN and DIN where correlated double sampling (CDS) is performed by SH1, SH2 and SH3. The precharge level of the CCD output signal is sampled, held and output by the SH2 output, and the signal level is sampled, held and output by the SH3 output. CDSCP: The CDSCP stabilizes the input signal DC level, clamps (CPDM) the input signal during the idle transfer interval for the purpose of eliminating the AGC input offset, and synchronizes the DC level ([ 1], [ 2]) of SH2 and SH3. AGC: The gain can be varied from 8 to 38dB by adjusting the AGCCONT voltage control VAGCCONT from 0 to. PF: A primary low-pass filter is installed for the purpose of eliminating unused bands and white noise and improving S/N. CAMSH: The CAMSH is used for camera signal processing system. It is a sample-and-hold circuit which synchronizes the data read-in timing for the external A/D. AGCCP: The basic black level is set ([ 3]) by clamping the AGC output waveform with the CPOB clock during the OPB interval. The AGCCP capacitance is connected to the AGCCP pin. BK: The black level is calibrated by blanking the black level signal of the AGC output waveform so that it does not fall below the basic black level and replacing the DC potential. ([ 4]) The signal is blanked when PBK is low. C/VSW: When the CAM/VIDEO, PB/REC, CH/C and PS pin voltages are set so that the camera signal processing system operates, C/VSW conducts the BK output (camera signal) into the DRV. In addition, when these voltages are set so that the video signal processing system operates, C/VSW conducts the VISH output (video signal) into the DRV. OFFSET SW: The OFFSET SW selects [OFFSET], [CH/CDC] or [OUTCP] as the offset adjustment input pin of the DRV block and activates these pins by selecting the CAM/VIDEO, PB/REC, CH/C and PS pin voltages. When the camera signal processing system is in camera mode, the OFFSET pin is conducted [OFFSET], allowing the camera signal offset to be adjusted. ([ 5]) When the video signal processing system is in IN mode, the OUTCP pin is conducted [OUTCP], clamping the video composite signal at its sync level and offsetting the signal. In addition, CH/C mode conducts the CH/C DC [CH/CDC], which gives center potential to the high-band chroma and low-band chroma signals of the video signal. DRV: DRV drives the external A/D. Camera and video (IN, CH, C modes) signals are input by switching C/VSW, and offset adjusted signals are output from DRVOUT pin. 14

15 REFBOTTOM, REFTOP: REFBOTTOM and REFTOP are reference voltage source for the external A/D. They are connected to VRT and VRB of the A/D, and 2V and 4V are supplied. MODE SWITCHING: MODE SWITCHING is a mode selection block which selects camera signal system or video signal system operation by selecting high or low potentials for the CAM/VIDEO, PB/REC, CH/C and PS pins. PS is the power save pin, and power save functions when this pin is low. 2. Video signal processing system Operating conditions The video signal processing system has three modes: IN signal mode, CH signal mode and C signal mode. The video signal processing system operates in IN signal mode when PS is high, CAM/VIDEO is high, PB/REC is low and CH/C is high, or when PS is high, CAM/VIDEO is low, PB/REC is low and CH/C is low. The video signal processing system operates in CH signal mode when PS is high, CAM/VIDEO is low, PB/REC is high and CH/C is high. The video signal processing system operates in C signal mode when PS is high, CAM/VIDEO is low, PB/REC is high and CH/C is low, or when PS is high, CAM/VIDEO is low, PB/REC is high and CH/C is high. Video signal processing system timing chart IN mode IN/CH input 2.4V AMP output 9.5dB VISP 2.1V DRVOUT output 2.1V 15

16 IN signal mode INCP: The video composite signal is input to IN/CH pin. INCP expands the input dynamic range, and sync tip clamps the input signal at 2.4V to allow full input. The input level and frequency are respectively 571mVp-p (Max.) and DC is up to 7MHz. INAMP: This is a fixed gain amplifier with a gain of 9.5dB. IN/CHSW: IN/CHSW switches between the IN signal and CH (high-band chroma) signal. The signals are switched according to the mode selection. VISH: The VISH is used for video signal processing system. It is a sample-and-hold circuit which synchronizes the data read-in timing for the external A/D. VISW: VISW switches between the IN, CH and C low-band chroma signals for the video signal processing system. The signals are switched according to the mode selection. OUTCP: OUTCP is a clamp circuit which operates when the IN signal is output to the DRV. The clamp potential is the sync portion, and is 2.1V. 16

17 CH (high-band chroma) signal mode CENTER BIAS: The video high-band chroma signal is input to IN/CH pin. CENTER BIAS expands the input dynamic range and sets a center DC bias so that the center potential of the SIN signal is 2.7V to allow full input. The input level and frequency are respectively 470mVp-p (Max.) and from 1 to 7MHz. CH/C DC: CH/C DC is a DC bias circuit which operates when the CH signal is output to the DRV. The DC bias potential is. CH mode IN/CH input 2.7V AMPOUT output 9.1dB VISH DRVOUT output 17

18 C (low-band chroma) signal mode CENTER BIAS: The video low-band chroma signal is input to PBRFC pin. CENTER BIAS expands the input dynamic range and sets a center DC bias so that the center potential of the SIN signal is 2.94V to allow full input. The input level and frequency are respectively 1490mVp-p (Max.) and DC is up to 1.5MHz. GCA: The GCA amplifier controls the gain of the C signal input to PBRFC. The gain can be varied from 0.4 to 20.5dB by adjusting the RFCONT voltage from 0 to. CH/C DC: CH/C DC is a DC bias circuit which operates when the C signal is output to the DRV. The DC bias potential is. C mode PBREC input 2.94V GCAOUT output 0.4 to 20.5dB VISH DRVOUT output 18

19 Gain [db] OFFSET [mv] Gain [db] CXA2006Q Example of Representative Characteristics CAM mode AGCCONT control supply voltage characteristics VAGCCONT vs. Gain VCC = 4.5V 20 VCC = 5.0V VAGCCONT [V] CAM mode OFFSET control supply voltage characteristics VOFFSET vs. OFFSET VCC = 4.5V VCC = 4.75V VCC = 5.0V VOFFSET [V] C mode RFGCA gain control supply voltage characteristics VRFCONT vs. Gain VCC = 4.5V VCC = 5.0V VRFCONT [V] 19

20 Gain [db] OFFSET [mv] Gain [db] CXA2006Q CAM mode AGCCONT control temperature characteristics (VCC = 4.75V) 40 AGCCONT vs. Gain 20 C 27 C 75 C VCC = 4.75V CAM mode OFFSET control temperature characteristics AGCCONT [V] VOFFSET vs. OFFSET 75 C 27 C 20 C VCC = 4.75V VOFFSET [V] C mode RFGCA gain control temperature characteristics VRFCONT vs. Gain C C 75 C VCC = 4.75V VRFCONT [V] 20

21 Gain [db] Gain [db] CXA2006Q CAM mode maximum signal amplitude temperature characteristics Ta vs. VOUT (camera mode) mingain (in = 0.4Vp-p) CH mode AMP gain temperature characteristics Ta vs. Gain (CH mode) 11 VOUT [Vp-p] VCC = 4.75V VCC = 4.75V Ta [ C] Ta [ C] C mode maximum signal amplitude temperature characteristics IN mode AMP gain temperature characteristics 3.50 Ta vs. VOUT (C mode) 11 Ta vs. Gain (C mode) VOUT [Vp-p] maxgain VCC = 4.75V Ta [ C] VCC = 4.75V Ta [ C] 21

22 2nd/3rd Harmonic Distortion [db] 2nd/3rd Harmonic Distortion [db] 2nd/3rd Harmonic Distortion [db] CXA2006Q VRT, VRB, DCOUT [V] VRT, VRB and output DC (CAM, IN, CH and C modes) temperature characteristics inoutdc Ta vs. VRT, VRB, DCOUT VRT COutDC CHOutDC VCC = 4.75V CamOutDC (cont = 1.0V) 2.00 VRB Ta [ C] CH mode 2nd/3rd harmonic distortion temperature characteristics Ta vs. 2nd /3rd harmonic distortion 2nd: OUT = 1.8Vp-p 2nd: OUT = 1.4Vp-p 3rd: OUT = 1.8Vp-p 3rd: OUT = 1.4Vp-p f = 5MHz VCC = 4.5V Ta [ C] 30 C mode 2nd/3rd harmonic distortion temperature characteristics Ta vs. 2nd/3rd harmonic distortion 30 IN mode 2nd/3rd harmonic distortion temperature characteristics Ta vs. 2nd/3rd harmonic distortion nd: IN = 800mVp-p, OUT = 1.8Vp-p 2nd: IN = 0mVp-p, OUT = 0.6Vp-p 3rd: IN = 800mVp-p, OUT = 1.8Vp-p rd: OUT = 1.8Vp-p 2nd: OUT = 1.8Vp-p 2nd: OUT = 1.4Vp-p 3rd: OUT = 1.4Vp-p rd: IN = 0mVp-p, OUT = 0.6Vp-p f = 700kHz VCC = 4.5V Ta [ C] f = 5MHz VCC = 4.5V Ta [ C] 22

23 0.50 (8.0) CXA2006Q Package Outline Unit: mm 32PIN QFP (PASTIC) 9.0 ± M to PACKAGE MATERIA EPOXY RESIN SONY CODE QFP-32P-01 EAD TREATMENT SODER PATING EIAJ CODE QFP032-P-0707 EAD MATERIA 42 AOY JEDEC CODE PACKAGE MASS 0.2g 23