CMOS Latches and Flip-Flops

Transcription

1 CMOS Latches and Flip-Flops João Canas Ferreira University of Porto Faculty of Engineering

2 Topics 1 General Aspects 2 Circuits based on positive feedback 3 Circuits based on charge storage João Canas Ferreira (FEUP) CMOS Latches and Flip-Flops / 30

3 Sequential digital circuits Two main data storage mechanisms: positive feedback electric charge storage João Canas Ferreira (FEUP) CMOS Latches and Flip-Flops / 30

4 Latch vs. register (flip-flop) D Q D Q Clk Clk Clk D Q Clk D Q Latch stores data while clock is low (level-sensitive circuit) Register stores date on rising clock edge (edge-triggered) João Canas Ferreira (FEUP) CMOS Latches and Flip-Flops / 30

5 Latches Source: [Rabaey03] João Canas Ferreira (FEUP) CMOS Latches and Flip-Flops / 30

6 Circuits with latches Latch N is transparent for φ = 0 Latch P is transparent for φ = 1 N Latch Logic P Latch Logic João Canas Ferreira (FEUP) CMOS Latches and Flip-Flops / 30

7 Timing parameters CLK t su t hold t Register D Q D stable data t CLK t c-q Q stable data t t su t hold t c-q t plogic t cd how long the input data must be stable before the active clock edge how long the input should remain stable after the active clock edge output propagation delay referred to the clock edge worst propagation delay through combinational logic smallest propagation delay through combinational logic (contamination delay) Conditions for correct operation: T t c q + t plogic + t su t cdreg + t cdlogic t hold João Canas Ferreira (FEUP) CMOS Latches and Flip-Flops / 30

8 Timining characterization t d-q D Q D Q clk clk t c-q t c-q João Canas Ferreira (FEUP) CMOS Latches and Flip-Flops / 30

9 Positive feedback implies bistability João Canas Ferreira (FEUP) CMOS Latches and Flip-Flops / 30

10 Topics 1 General Aspects 2 Circuits based on positive feedback 3 Circuits based on charge storage João Canas Ferreira (FEUP) CMOS Latches and Flip-Flops / 30

11 Latches based on multiplexers 1 Q 0 Q D 0 D 1 CLK Q=Clk Q Clk In negative latch CLK Q=Clk Q Clk In positive latch João Canas Ferreira (FEUP) CMOS Latches and Flip-Flops / 30

12 CMOS latch João Canas Ferreira (FEUP) CMOS Latches and Flip-Flops / 30

13 Latch: alternative implementation Only uses NMOS pass transistors Important: There should be no overlap of the clock signals João Canas Ferreira (FEUP) CMOS Latches and Flip-Flops / 30

14 Master-slave register Source: [Rabaey03] Two latches of opposite polarity (master: negative, slave: positive) The register is positive edge-triggered (active edge is the rising edge) João Canas Ferreira (FEUP) CMOS Latches and Flip-Flops / 30

15 Master-slave register: implementation Source: [Rabaey03] t su = 3 t pd_inv + t tp_dx t c q = t pd_inv + t tp_dx t hold = 0 Main issue: relatively large charge on the clock signal João Canas Ferreira (FEUP) CMOS Latches and Flip-Flops / 30

16 Propagation delay t c q (lh) = 23 ps FreePDK45 technology t c q (hl) = 26 ps João Canas Ferreira (FEUP) CMOS Latches and Flip-Flops / 30

17 Setup time simulation João Canas Ferreira (FEUP) CMOS Latches and Flip-Flops / 30

18 Setup time violation (simulation) João Canas Ferreira (FEUP) CMOS Latches and Flip-Flops / 30

19 Clock load reduction Source: [Rabaey03] I 2 and I 4 should be weak inverters (ratioed circuit) Reverse current is, typically, not a problem. João Canas Ferreira (FEUP) CMOS Latches and Flip-Flops / 30

20 Issue: clock signal overlap Source: [Rabaey03] There is a direct path between D and Q (overlap on the rising edge) Contention on node A Main solution: avoid overlapping clock signals or use pseudo-static register. João Canas Ferreira (FEUP) CMOS Latches and Flip-Flops / 30

21 Forcing the feedback loop Source: [Rabaey03] set/reset latch based on NOR gates fully asynchronous (is not a good match to the synchronous design style) João Canas Ferreira (FEUP) CMOS Latches and Flip-Flops / 30

22 SR latch with clock signal Source: [Rabaey03] Better for use in synchronous circuits Sizing problem: how should transistors M5-M6 and M7-M8 be sized? João Canas Ferreira (FEUP) CMOS Latches and Flip-Flops / 30

23 Dimensioning example M5 n1 s 0 0 NMOS + L=50n W= factor*90n M6 qbar clk n1 0 NMOS + L=50n W= factor*90n * FreePDK45 technology João Canas Ferreira (FEUP) CMOS Latches and Flip-Flops / 30

24 Topics 1 General Aspects 2 Circuits based on positive feedback 3 Circuits based on charge storage João Canas Ferreira (FEUP) CMOS Latches and Flip-Flops / 30

25 Static vs. dynamic latch Static Dynamic Source: [Rabaey03] João Canas Ferreira (FEUP) CMOS Latches and Flip-Flops / 30

26 Dynamic register Positive edge-triggered t setup < t x_gate t hold = 0 t c q < 2 t pinv +t x_gate Source: [Rabaey03] Clock overlap is a significant issue Source: [Rabaey03] t 0 0 < t T1 + t I1 + t T2 t 1 1 < t hold João Canas Ferreira (FEUP) CMOS Latches and Flip-Flops / 30

27 Pseudo-static latch Source: [Rabaey03] Much better noise immunity The feedback inverter must be weak. João Canas Ferreira (FEUP) CMOS Latches and Flip-Flops / 30

28 C 2 MOS latches and registers C 2 MOS: Clocked CMOS Source: [Rabaey03] Immune to clock overlap if the rise/fall times are sufficiently small. João Canas Ferreira (FEUP) CMOS Latches and Flip-Flops / 30

29 Behavior for overlapping clock signals At X: possible transition 0 1 At X: possible transition 1 0 (def. hold time) During the overlap only one of the pull-up or pull-down networks is active. João Canas Ferreira (FEUP) CMOS Latches and Flip-Flops / 30

30 References Some of the figures come from the book: Rabaey03 J. M. Rabaey et al, Digital Integrated Circuits, 2 nd edition,prentice Hall, João Canas Ferreira (FEUP) CMOS Latches and Flip-Flops / 30