# Logic Design II (17.342) Spring Lecture Outline

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1 Logic Design II (17.342) Spring 2012 Lecture Outline Class # 05 February 23, 2012 Dohn Bowden 1

2 Today s Lecture Analysis of Clocked Sequential Circuits Chapter 13 2

4 Administrative Admin for tonight Syllabus review Lab #1 is due TONIGHT February 23 rd Exam # 1 NEXT WEEK March 1 st Covers Chapters 11 and 12» Intro to sequential circuits» Latches and flip-flops» Registers and Counters Open book/open notes exam 4

5 Syllabus Review Week Date Topics Chapter Lab Report Due 1 01/26/12 Review of combinational circuits /02/12 Intro to sequential circuits. Latches and flip-flops /09/12 Registers and Counters /16/12 Registers and Counters continued /23/12 Analysis of Clocked Sequential Circuits /01/12 Examination /08/12 Derivation of State Graphs and Tables 14 X 03/15/12 NO CLASSES Spring Break 8 03/22/12 Reduction of State Tables State Assignments /29/12 Sequential Circuit Design /05/12 Circuits for Arithmetic Operations /12/12 Examination /19/12 State Machine Design with SM Charts /26/12 Course Project Build/Troubleshoot in Lab Project /03/12 Final Exam/Course Project Brief & Demo Demo 5

6 Questions? 6

7 Chapter 13 ANALYSIS OF CLOCKED SEQUENTIAL CIRCUITS 7

8 Objectives 8

9 Objectives 1. Analyze a sequential circuit by signal tracing 2. Given a sequential circuit write the next-state equations for the flip-flops and derive the state graph or state table Using the state graph determine the state sequence and output sequence for a given input sequence 3. Explain the difference between a Mealy machine and a Moore machine 4. Given a state table construct the corresponding state graph and conversely 9

10 Objectives 5. Given a sequential circuit or a state table and an input sequence Draw a timing chart for the circuit Determine the output sequence from the timing chart neglecting any false outputs 6. Draw a general model for a clocked Mealy or Moore sequential circuit Explain the operation of the circuit in terms of these models Explain why a clock is needed to ensure proper operation of the circuit 10

11 Analysis of Clocked Sequential Circuits 11

12 Analysis of Clocked Sequential Circuits Counter designs thus far were Fixed sequence of states No inputs other than a clock pulse that causes the state to change Will now consider sequential circuits that have additional inputs Circuit outputs and flip-flop states will now depend on the input sequence which is applied to the circuit 12

13 Analysis of Clocked Sequential Circuits Flip-flop state and output sequence can be determined by Signal tracing (small circuits) Construction of state graph or state table The output and state sequences can be determine Also they are useful for the design of sequential circuits 13

14 A Sequential Parity Checker 14

15 A Sequential Parity Checker Parity bit An extra bit added for purposes of error detection when binary data is transmitted or stored Odd parity the total number of 1 bits in the block including the parity bit is odd 15

16 Example 16

17 A Sequential Parity Checker Example if data is being transmitted in groups of 7 bits an eighth bit can be added to each group of 7 bits to make the total number of 1 s in each block of 8 bits an odd number 17

18 Design a Parity Checker Circuit 18

19 Design a Parity Checker Circuit Design a parity checker such that Serial data input Clock input Output of the circuit should be Z = 1 if the total number of 1 inputs received is odd Z = 0 indicates that an error in transmission has occurred 19

20 Design a Parity Checker Circuit Design a parity checker Block diagram 20

21 Design a Parity Checker Circuit Design a parity checker X is read at the time of the active clock edge X input must be synchronized with the clock so that it assumes its next value before the next active clock edge Clock required to distinguish consecutive 0's or 1's on the X input 21

22 Design a Parity Checker Circuit Design a parity checker X is read at the time of the active clock edge X input must be synchronized with the clock so that it assumes its next value before the next active clock edge Clock required to distinguish consecutive 0's or 1's on the X input Typical input and output waveforms 22

23 Design a Parity Checker Circuit Design a parity checker Typical input and output waveforms 23

24 Design a Parity Checker Circuit Design a parity checker Construct a state graph Circuit must "remember" whether the total number of 1 inputs received is even or odd Therefore two states are required Designate these states as S 0 even and S 1 odd number of 1 's received 24

25 Design a Parity Checker Circuit Design a parity checker Construct a state graph Circuit must "remember" whether the total number of 1 inputs received is even or odd Therefore two states are required Designate these states as S 0 even and S 1 odd number of 1 's received 25

26 Design a Parity Checker Circuit Design a parity checker Start in state S 0 initially zero 1's have been received If the circuit is in state S 0 even number of 1's received and X = 0 is received The circuit must stay in S 0 because the number of 1's received is still even 26

27 Design a Parity Checker Circuit Design a parity checker If X = 1 is received the circuit goes to state S 1 because the number of 1's received is then odd 27

28 Design a Parity Checker Circuit Design a parity checker If in state S 1 odd number of 1's received A zero input causes no state change A one causes a change to S 0 because the number of 1's received is then even 28

29 Design a Parity Checker Circuit Design a parity checker Z should be 1 whenever the circuit is in state S 1 odd number of 1's received The output is listed below the state on the state graph 29

30 Design a Parity Checker Circuit Design a parity checker Create a State Table from the State Graph 30

31 Design a Parity Checker Circuit Design a parity checker Create a State Table from the State Graph 31

32 Design a Parity Checker Circuit Design a parity checker If the present state is S 0 32

33 Design a Parity Checker Circuit Design a parity checker If the present state is S 0 The output is Z = 0 33

34 Design a Parity Checker Circuit Design a parity checker If the present state is S 0 The output is Z = 0 and If the input is X= 1 34

35 Design a Parity Checker Circuit Design a parity checker If the present state is S 0 The output is Z = 0 and If the input is X= 1 the next state will be S 1 35

36 Design a Parity Checker Circuit Design a parity checker Only two states therefore a single flip-flop (Q) is needed Use a T Flip-flop 36

37 Design a Parity Checker Circuit Design a parity checker Q = 0 correspond to S 0 Q = 1 correspond to S 1 37

38 Design a Parity Checker Circuit Design a parity checker Q = 0 correspond to S 0 Q = 1 correspond to S 1 Table shows the next state of flip-flop Q as a function of the present state and X 38

39 Design a Parity Checker Circuit Design a parity checker Q = 0 correspond to S 0 Q = 1 correspond to S 1 Table shows the next state of flip-flop Q as a function of the present state and X For T flip-flop T = 1 whenever Q and Q+ differ 39

40 Design a Parity Checker Circuit Design a parity checker Q = 0 correspond to S 0 Q = 1 correspond to S 1 Table shows the next state of flip-flop Q as a function of the present state and X For T flip-flop T = 1 whenever Q and Q+ differ T input must be 1 whenever X= 1 40

41 Design a Parity Checker Circuit Design a parity checker When X = 1 the flip-flop changes state after the falling edge of the clock 41

42 Design a Parity Checker Circuit Design a parity checker Final value of Z is 0 Because an even number of 1 's was received 42

43 Design a Parity Checker Circuit Design a parity checker If the final value of Z = 1 The flip-flop would need to be reset prior to next sequence 43

44 Analysis by Signal Tracing and Timing Charts 44

45 Analysis by Signal Tracing and Timing Charts We can analyze clocked sequential circuits to find the output sequence resulting from a given input sequence by Tracing 0 and 1 signals through the circuit 45

46 Analysis by Signal Tracing and Timing Charts The basic procedure to analyze the circuit is 1. Assume an initial state of the flip-flops All flip-flops reset to 0 unless otherwise specified 2. For the first input in the given sequence determine the circuit output(s) and flip-flop inputs 3. Determine the new set of flip-flop states after the next active clock edge 4. Determine the output(s) that corresponds to the new states 5. Repeat 2 3 and 4 for each input in the sequence 46

47 Analysis by Signal Tracing and Timing Charts For the analysis Construct a timing chart which shows the relationship between the Input signal the clock the flip-flop states and the circuit output The circuit output may change at the time the flip-flops change state or at the time the input changes Depends on the type of circuit 47

48 Types of Clocked Sequential Circuits 48

49 Types of Clocked Sequential Circuits Two types of clocked sequential circuits First the output depends only on the present state of the flipflops Second those in which the output depends on both the Present state of the flip-flops and On the value of the circuit inputs 49

50 Moore Machine 50

51 Moore Machine Moore machine Output of a sequential circuit is a function of the present state only Two examples 51

52 Moore Machine Moore machine The state graph for a Moore machine has the output associated with the state 52

53 Mealy Machine 53

54 Mealy Machine Mealy machine Output is a function of both the present state and the input Example 54

55 Mealy Machine Mealy machine The state graph for a Mealy machine has the output associated with the arrow going between states 55

56 Example Moore Circuit Analysis 56

57 Moore Circuit Analysis Analyze the circuit below input sequence X = Initial state is A = B = 0 and all state changes occur after the rising edge of the clock X input is synchronized with the clock so that it assumes its next value after each rising edge 57

58 Moore Circuit Analysis Analyze the circuit below input sequence X = Initial state is A = B = 0 Z is a function only of the present state Z = A B output will only change when the state changes Moore Circuit! 58

59 Analysis by Signal Tracing and Timing Charts RECALL The basic procedure to analyze the circuit is 1. Assume an initial state of the flip-flops All flip-flops reset to 0 unless otherwise specified 2. For the first input in the given sequence determine the circuit output(s) and flip-flop inputs 3. Determine the new set of flip-flop states after the next active clock edge 4. Determine the output(s) that corresponds to the new states 5. Repeat 2 3 and 4 for each input in the sequence 59

60 Moore Circuit Analysis Analyze the circuit below input sequence X = Initial state is A = B = 0 Initially X = 0 so D A = 1 and D B = 0 The state will change to A = 1 and B = 0 after the first rising clock edge 60

61 Moore Circuit Analysis Analyze the circuit below input sequence X = Initial state is A = B = 0 When the circuit is reset to its initial state A = B = 0 the initial output is Z = 0 because this initial 0 is not in response to any X input it should be ignored 61

62 Moore Circuit Analysis Analyze the circuit below input sequence X = Then X changes to 1... so D A = 0 D B = 1 and the state changes to AB = 01 after the second rising clock edge 62

63 Moore Circuit Analysis Analyze the circuit below input sequence X = After the state change X remains 1 so D A = D B = 1 and the next rising edge causes the state to change to 11 63

64 Moore Circuit Analysis Analyze the circuit below input sequence X = When X changes to 0 D A = 0 and D B = 1 and the state changes to AB = 01 on the fourth rising edge 64

65 Moore Circuit Analysis Analyze the circuit below input sequence X = Then with X= 1 D A = D B = 1 so the fifth rising clock edge causes the state to change to AB = 11 65

66 Moore Circuit Analysis Analyze the circuit below input sequence X = The resulting output sequence Z =

67 Example Mealy Circuit Analysis 67

68 Mealy Circuit Analysis Analyze the circuit below input sequence X= The input is synchronized with the clock so that input changes occur after the falling edge 68

69 Mealy Circuit Analysis Analyze the circuit below input sequence X= The output depends on both the input.. X and the flip-flop states A and B so Z may change either when the input changes or when the flip-flops change state 69

70 Mealy Circuit Analysis Analyze the circuit below input sequence X= Initially flip-flop states are A = 0 B = 0 If X= 1 the output is Z = 1 and J B = K A = 1 70

71 Mealy Circuit Analysis Analyze the circuit below input sequence X= After the falling edge of the first clock pulse B changes to 1 so Z changes to 0 If the input is changed to X = 0 Z will change back to 1 71

72 Mealy Circuit Analysis Analyze the circuit below input sequence X= Flip-flop inputs = 0... so no state change occurs with the second falling edge When X is changed to 1 Z becomes 0 and J A = K A = J B = 1 72

73 Mealy Circuit Analysis Analyze the circuit below input sequence X= A changes to 1 on the third falling clock edge Z changes to 1 73

74 Mealy Circuit Analysis Analyze the circuit below input sequence X= X is changed to 0 Z becomes 0 and no state change occurs with the fourth clock pulse 74

75 Mealy Circuit Analysis Analyze the circuit below input sequence X= X is changed to 0 Z becomes 0 and no state change occurs with the fourth clock pulse 75

76 Mealy Circuit Analysis Analyze the circuit below input sequence X= X is changed to 1 Z becomes 1 Because J A = K A = J B = K B = 1 the fifth clock pulse returns the circuit to the initial state 76

77 Mealy Circuit Analysis For Mealy circuits After the circuit has changed state and before the input is changed the output may temporarily assume an incorrect value which we call a false output False value arises when the circuit has assumed a new state but the old input associated with the previous state is still present 77

78 False Outputs Moore circuit can change slate only when the Flip-flops change state and not when the input changes therefore No false outputs can appear in a Moore circuit False outputs are often referred to as glitches and spikes 78

79 State Tables and Graphs 79

80 State Tables and Graphs Previous analysis works for small circuits and short input sequences However the construction of state tables and graphs provides a more systematic approach which is useful for the analysis of larger circuits and which leads to a general synthesis procedure for sequential circuits State table specifies the next state and output of a sequential circuit in terms of Its present state and input 80

81 State Tables and Graphs The following method can be used to construct the state table 1. Determine the flip-flop input equations and the output equations from the circuit 2. Derive the next-state equation for each flip-flop from its input equations using one of the following relations D flip-flop Q + = D (13-1) D-CE flip-flop Q + = D CE + Q CE (13-2) T flip-flop Q + = T Q (13-3) S-R flip-flop Q + = S + R Q (13-4) J-K flip-flop Q + = JQ + K Q (13-5) 81

82 State Tables and Graphs 3. Plot a next-state map for each flip-flop 4. Combine these maps to form the state table Such a state table which gives the next state of the flipflops as a function of their present state and the circuit inputs is frequently referred to as a transition table 82

83 Example State Tables and Graphs 83

84 State Tables and Graphs Example derive the state table for the circuit below 84

85 State Tables and Graphs Example con t derive the state table for the circuit below Moore sequential circuit 85

86 State Tables and Graphs Example con t derive the state table for the circuit below 1. The flip-flop input equations and output equation are D A = X B D B = X + A Z = A B 86

87 State Tables and Graphs Example con t derive the state table for the circuit below 2. The next-state equations for the flip-flops are A + = X B B + = X + A 87

88 State Tables and Graphs Example con t derive the state table for the circuit below 3. The corresponding maps are A + = X B B + = X + A 88

89 State Tables and Graphs Recall the next-state map for each flip-flop are combined to form the state table (transition table) The state table gives The next state of the flip-flops as a function of their present state and the circuit inputs 89

90 State Tables and Graphs Example con t derive the state table for the circuit below 4. Combine the state maps to form the transition table which gives the next state of both flip-flops (A + B + ) as a function of the present state and input A + B + AB X=0 X=1 Z

91 State Tables and Graphs Example con t derive the state table for the circuit below 4. con t the output function Z is then added to the table in this example the output depends only on the present state of the flipflops and not on the input so only a single output column is required Z = A B A + B + AB X=0 X=1 Z

92 State Tables and Graphs Example con t derive the state table for the circuit below 4. Let AB = 00 correspond to circuit state S 0 01 to S 1 11 to S 2 and 10 to S 3 A + B + AB X=0 X=1 Z Present Next State Present State X = 0 X = 1 Output(Z) S 0 S 3 S 1 0 S 1 S 0 S 2 1 S 2 S 1 S 2 0 S 3 S 2 S

93 State Tables and Graphs Example con t derive the state table for the circuit below 4. Let AB = 00 correspond to circuit state S 0 01 to S 1 11 to S 2 and 10 to S 3 A + B + AB X=0 X=1 Z Present Next State Present State X = 0 X = 1 Output(Z) S 0 S 3 S 1 0 S 1 S 0 S 2 1 S 2 S 1 S 2 0 S 3 S 2 S

94 State Tables and Graphs Example con t derive the state table for the circuit below 4. Construct State Graph Present Next State Present State X = 0 X = 1 Output(Z) S 0 S 3 S 1 0 S 1 S 0 S 2 1 S 2 S 1 S 2 0 S 3 S 2 S

95 State Tables and Graphs Example con t derive the state table for the circuit below 4. Each node represents a state of the circuit Present Next State Present State X = 0 X = 1 Output(Z) S 0 S 3 S 1 0 S 1 S 0 S 2 1 S 2 S 1 S 2 0 S 3 S 2 S

96 State Tables and Graphs Example con t derive the state table for the circuit below 4. Each node represents a state of the circuit corresponding output is placed in the circle below the state symbol Present Next State Present State X = 0 X = 1 Output(Z) S 0 S 3 S 1 0 S 1 S 0 S 2 1 S 2 S 1 S 2 0 S 3 S 2 S

97 State Tables and Graphs Example con t derive the state table for the circuit below 4. Each node represents a state of the circuit corresponding output is placed in the circle below the state symbol the arc joining two nodes is labeled with the value of X which will cause a state change between these nodes Present Next State Present State X = 0 X = 1 Output(Z) S 0 S 3 S 1 0 S 1 S 0 S 2 1 S 2 S 1 S 2 0 S 3 S 2 S

98 State Tables and Graphs Example FINAL derive the state table for the circuit below Present Next State Present State X = 0 X = 1 Output(Z) S 0 S 3 S 1 0 S 1 S 0 S 2 1 S 2 S 1 S 2 0 S 3 S 2 S

99 Example State Tables and Graphs 99

100 State Tables and Graphs Example derive the state table for the circuit below 100

101 State Tables and Graphs Example con t derive the state table for the circuit below Mealy sequential circuit 101

102 State Tables and Graphs Example con t derive the state table for the circuit below 1. The flip-flop input equations and output equation are 102

103 State Tables and Graphs Example con t derive the state table for the circuit below 2... We can construct the next-state and output equations from the circuit diagram 103

104 State Tables and Graphs Example con t derive the state table for the circuit below 2... We can construct the next-state and output equations from the circuit diagram A + = J A A + K A A = XBA + X A B + = J B B + K B B = XB + (AX) B = XB + X B + A B Z = X A B + XB + XA 104

105 State Tables and Graphs Example con t derive the state table for the circuit below 3. The corresponding maps are A + = J A A + K A A = XBA + X A B + = J B B + K B B = XB + (AX) B = XB + X B + A B Z = X A B + XB + XA 105

106 State Tables and Graphs Example con t derive the state table for the circuit below 4. con t Combine the state maps to form the transition table 106

107 State Tables and Graphs Example con t derive the state table for the circuit below 4. con t Let AB = 00 correspond to circuit state S 0 01 to S 1 11 to S 2 and 10 to S 3 107

108 State Tables and Graphs Example con t derive the state table for the circuit below 4. con t Construct State Graph input/output 108

109 State Tables and Graphs Example FINAL derive the state table for the circuit below 109

110 Example State Tables and Graphs 110

111 Serial Adder Analysis Analyze the operation of a serial adder that adds two n-bit binary numbers x i and y i Serial adder is similar to the parallel adder except that the binary numbers are fed in serially one pair of bits at a time and the sum is read out serially one bit at a time 111

112 Serial Adder Analysis Analyze the operation of a serial adder First x 0 and y 0 are fed in a sum digit s 0 is generated and the carry c 1 is stored 112

113 Serial Adder Analysis Analyze the operation of a serial adder At the next clock time x 1 and y 1 are fed in and added to c 1 to give the next sum digit s 1 and the new carry c 2 which is stored This process continues until all bits have been added 113

114 Serial Adder Analysis Analyze the operation of a serial adder A full adder is used to add the x i, y i and c i bits to form c i+1 and s i A D flip-flop is used to store the carry (c i+1 ) on the rising edge of the clock. The x i and y i inputs must be synchronized with the clock 114

115 Serial Adder Analysis Analyze the operation of a serial adder timing diagram for the serial adder Example add to give a sum of and a final carry of 0 115

116 Serial Adder Analysis Analyze the operation of a serial adder timing diagram for the serial adder Example add to give a sum of and a final carry of 0 116

117 Serial Adder Analysis Analyze the operation of a serial adder timing diagram for the serial adder Example add to give a sum of and a final carry of 0 117

118 Serial Adder Analysis Analyze the operation of a serial adder truth table for the full adder 120

119 Serial Adder Analysis Analyze the operation of a serial adder construct a state graph 121

120 Example Mealy Sequential Circuit With Two Inputs/Outputs 123

121 Mealy Sequential Circuit With Two Inputs/Outputs State table for a Mealy sequential circuit with two inputs and two outputs along with corresponding state graph The notation 00,01/00 on the arc from S 3 to S 2 means if X 1 = X 2 = 0 or X 1 = 0 and X 2 = 1 then Z 1 = 0 and Z 2 = 0 124

122 Construction and Interpretation of Timing Charts 125

123 Construction and Interpretation of Timing Charts Several important points concerning the construction and interpretation of timing charts are 1. When constructing timing charts note that a state change can only occur after the rising (or falling) edge of the clock 2. The input will normally be stable immediately before and after the active clock edge 126

124 Construction and Interpretation of Timing Charts 3. For a Moore circuit The output can change only when the state changes For a Mealy circuit The output can change when the input changes as well as when the state changes A false output may occur between the time the state changes and the time the input is changes to its new value 127

125 Construction and Interpretation of Timing Charts 4. False outputs are difficult to determine from the state graph So use either signal tracing through the circuit or Use the state table when constructing timing charts for Mealy circuits 128

126 Construction and Interpretation of Timing Charts 5. When using a Mealy state table for constructing timing charts the procedure is as follows (a) For the first input read the present output and plot it (b) Read the next state and plot it following the active edge of the clock pulse (c) Go to the row in the table which corresponds to the next state and read the output under the old input column and plot it this may be a false output (d) Change to the next input and repeat steps (a) (b) and (c) 129

127 Construction and Interpretation of Timing Charts 6. For Mealy circuits the best time to read the output is just before the active edge of the clock Because the output should always be correct at that time A false output may occur after the state has changed and before the input has changed 130

128 Example 131

129 Example The following example shows the relationships among the State graph State table Circuits and Timing chart The input sequence is X =

130 133

131 134

132 135

133 136

134 137

135 138

136 139

137 FINAL X = Z =

138 PREVIEW Synthesis Procedure 148

139 PREVIEW --- Synthesis Procedure The synthesis procedure for sequential circuits Opposite of the procedure used for analysis Starting with the specifications for the sequential circuit to be synthesized A state graph is constructed This graph is then translated to a state table and The flip-flop output values are assigned for each state The flip-flop input equations are then derived The logic diagram for the circuit is drawn Will be discussed in Chapters

140 General Models for Sequential Circuits 150

141 General Models for Sequential Circuits A sequential circuit can be divided conveniently into two parts The flip-flops which serve as memory for the circuit and The combinational logic which realizes the input functions for the flip-flops and the output functions The combinational logic may be implemented with Gates With a ROM or With a PLA 151

142 General Models for Sequential Circuits This circuit is a general model for a clocked Mealy sequential circuit with m inputs n outputs and k clocked D flip-flops used as memory This model emphasizes the presence of feedback in the sequential circuit because the flip-flop outputs are fed back as inputs to the combinational subcircuit 152

143 Clock Synchronization 153

144 Clock Synchronization The clock synchronizes the operation of the flip-flops and prevents timing problems Gates in the combinational subcircuit have finite propagation delays Finite time is required before the flip-flop inputs reach their final values Gate delays are not all the same If the next active clock edge does not occur until all flip-flop input signals have reached their final steady-state values The unequal gate delays will not cause any timing problems 154

145 Clock Synchronization All flip-flops which must change state do so at the same time in response to the active edge of the clock When the flip-flops change state The new flip-flop outputs are fed back into the combinational subcircuit No further change in the flip-flop states can occur until the next clock pulse 155

146 Minimum Clock Period (Sequential Circuit) 156

147 Minimum Clock Period - Sequential Circuit We can determine the fastest clock speed which is also the minimum clock period from the general model of the Mealy circuit Following the active edge of the clock the flip-flops change state and the flip-flop output is stable after the propagation delay (t p ) The new values of Q then propagate through the combinational circuit so that the D values are stable after the combinational circuit delay (t c ) Then the flip-flop setup time (t su ) must elapse before the next active clock edge 157

148 Minimum Clock Period - Sequential Circuit Thus the propagation delay in the flip-flops the propagation delay in the combinational subcircuit and the setup time for the flip-flops determine how fast the sequential circuit can operate and the minimum clock period is t clk (min) = t p + t c + t su This assumes that the X inputs are stable no later than t c + t su before the next active clock edge If this is not the case then we must calculate the minimum clock period by t clk (min) = t x + t c + t su Where t x is the time after the active clock edge at which the X inputs are stable 158

149 Minimum Clock Period - Sequential Circuit 159

150 General Model Clocked Moore Circuit 160

151 General Model - Clocked Moore Circuit The general model for the clocked Moore circuit is similar to the clocked Mealy circuit 161

152 General Model - Clocked Moore Circuit The output subcircuit is drawn separately as the output is only a function of the present state of the flip-flops and not a function of the circuit inputs 162

153 General Model - Clocked Moore Circuit The Moore circuit is similar to that of the Mealy except when inputs applied resulting outputs do not appear until after the clock causes the flip-flops to change state 163

154 General Model - Clocked Moore Circuit For sequential circuits with multiple inputs and outputs symbols represent each combination of input and output values Example below 164

155 General Model - Clocked Moore Circuit Let X = 0 represent input combination X 1 X 2 = 00 Let X= 1 represent X 1 X 2 = 01 etc Same representation with Z 165

156 General Model - Clocked Moore Circuit With these representations we can specify the behavior of any sequential circuit in terms of A single input variable X and A single output variable Z 166

157 General Model - Clocked Moore Circuit Table below specifies two functions the next-state function and the output function The next-state function designated (delta) gives the next state of the circuit the state after the clock pulse in terms of the present state (S) and the present input (X) S + = (S, X) 167

158 General Model - Clocked Moore Circuit The output function designated λ (lambda) gives the output of the circuit (Z) in terms of the present state (S) and input (X) Z = λ (S, X) 168

159 General Model - Clocked Moore Circuit Values of S + and Z can be determined from the state table From the table Next State Output 169

160 Lab 170

161 LABS Lab #1 is due TONIGHT February 23 rd Lab #2 will be available on March 8 th Due date MAY change from current due date on the syllabus 171

162 Next Week 172

163 Next Week Topics Exam #1 In two weeks Chapter 14 Derivation of State Graphs and Tables Pages

164 Home Work 174

165 Homework 1. Exam #1 preparation 2. Read Due in two weeks Chapter 14 Derivation of State Graphs and Tables Pages

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