CMOS Testing-2. Design for testability (DFT) Design and Test Flow: Old View Test was merely an afterthought. Specification. Design errors.

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1 Design and test CMOS Testing- Design for testability (DFT) Scan design Built-in self-test IDDQ testing ECE 261 Krish Chakrabarty 1 Design and Test Flow: Old View Test was merely an afterthought Specification Design errors Random defects Design Fabrication Synthesis, full-custom simulation, verification, test generation Testing Pass Accept Fail Reject ECE 261 Krish Chakrabarty 2

Design and Test Flow: New View Design and test are tightly coupled Specification Design errors Random defects Design for testability Fabrication Design improvements Process improvements Pass Testing

2 Design and Test Flow: New View Design and test are tightly coupled Specification Design errors Random defects Design for testability Fabrication Design improvements Process improvements Pass Testing Fail Diagnosis Accept Reject ECE 261 Krish Chakrabarty 3 Testing Sequential Circuits Difficult problem-internal states cannot be directly controlled and observed Long test sequences are necessary Solution: Scan design-simplify to combinational circuit testing Primary inputs (controllable) State inputs (not controllable) Combinational logic Registers Primary outputs (observable) State outputs (not observable) ECE 261 Krish Chakrabarty 4

3 Design for Test Design the chip to increase observability and controllability If each register could be observed and controlled, test problem reduces to testing combinational logic between registers. Better yet, logic blocks could enter test mode where they generate test patterns and report the results automatically. ECE 261 Krish Chakrabarty 5 Scan Design Make all flip-flops directly controllable and observable by adding multiplexers Popular design-for-test (DFT) technique-circuit is now combinational for testing purposes Primary inputs State inputs (controllable) Scan in Combinational logic Scan cells Primary outputs Scan out State outputs (observable) ECE 261 Krish Chakrabarty 6

Scan Design Convert each flip-flop to a scan register Only costs one extra multiplexer Normal mode: flip-flops behave as usual Scan mode: flip-flops behave as shift register Contents of flops can be

4 Scan Design Convert each flip-flop to a scan register Only costs one extra multiplexer Normal mode: flip-flops behave as usual Scan mode: flip-flops behave as shift register Contents of flops can be scanned out and new values scanned in ECE 261 Krish Chakrabarty 7 Data 0 (Functional) Scan in (Test data) Scan Cell Design D Q N/T = 1: Test mode N/T = 0: Normal mode Scan in N/T Clock D 0 D 1 D 2 D 3 Scan out N/T Clock Q 0 Q 1 Q 2 Q 3 ECE 261 Krish Chakrabarty 8

Scannable Flip-flops ECE 261 Krish Chakrabarty 9 Scan Design Separate input and output 4-bit scan registers Test sequence: {01100, 11011}, first 4 bits are

5 Scannable Flip-flops ECE 261 Krish Chakrabarty 9 Scan Design Separate input and output 4-bit scan registers Test sequence: {01100, 11011}, first 4 bits are for flip-flops Test data N/T Test responses Combinational circuit 1 0 Controllable primary input Scan chain/ Scan path N/T ECE 261 Krish Chakrabarty 10

Steps in Scan Testing N/T = 1: Scan in test pattern, hold appropriate bit pattern on controllable primary inputs N/T = 0: Apply test pattern to combinational circuit N/T=1: Scan out test responses

6 Steps in Scan Testing N/T = 1: Scan in test pattern, hold appropriate bit pattern on controllable primary inputs N/T = 0: Apply test pattern to combinational circuit N/T=1: Scan out test responses Scan provides complete controllability and observability Testing time? How many cycles? How to test scan registers? ECE 261 Krish Chakrabarty 11 Long Scan Chains Normal data Test data Scan chain Test vectors need to be translated to scan format ECE 261 Krish Chakrabarty 12

7 Built-in Self-test Built-in self-test lets blocks test themselves Generate pseudo-random inputs to comb. logic Combine outputs into a syndrome With high probability, block is fault-free if it produces the expected syndrome ECE 261 Krish Chakrabarty 13 Built-in Self Testing (BIST) Inputs Test generator (TGC) 0 1 Circuit under test (CUT) Response monitor (RM) Outputs Error Control On-chip test generator and response monitor ECE 261 Krish Chakrabarty 14

8 BIST: Advantages Lower cost due to elimination of external tester In-system, at-system, high-quality testing Faster fault detection, ease of diagnosis Overcomes pin limitations and related interfacing problems Reduces maintenance and repair costs at system level ECE 261 Krish Chakrabarty 15 BIST: Issues Test strategy (random, exhaustive, deterministic) Circuit partitioning Test pattern generation Exhaustive: counters Random: Linear-feedback shift registers (LFSRs) Deterministic: ROM, other methods? Response analysis Test control and scheduling ECE 261 Krish Chakrabarty 16 8

BIST Logic Circuits Linear-feedback shift-register (LFSR) Test patterns Multiple-input signature register (MISR) Test responses Signature ECE 261 Krish Chakrabarty 17 BIST

9 BIST Logic Circuits Linear-feedback shift-register (LFSR) Test patterns Multiple-input signature register (MISR) Test responses Signature ECE 261 Krish Chakrabarty 17 BIST Pattern Generation Linear Feedback Shift Register Shift register with input taken from XOR of state Pseudo-Random Sequence Generator Step Q ECE 261 Krish Chakrabarty

10 BIST Pattern Generation Linear Feedback Shift Register Shift register with input taken from XOR of state Pseudo-Random Sequence Generator Step ECE 261 Krish Chakrabarty 19 0 Q PRSG Linear Feedback Shift Register Shift register with input taken from XOR of state Pseudo-Random Sequence Generator Step ECE 261 Krish Chakrabarty 20 0 Q

11 PRSG Linear Feedback Shift Register Shift register with input taken from XOR of state Pseudo-Random Sequence Generator Step ECE 261 Krish Chakrabarty 21 0 Q PRSG Linear Feedback Shift Register Shift register with input taken from XOR of state Pseudo-Random Sequence Generator Step ECE 261 Krish Chakrabarty 22 0 Q

12 PRSG Linear Feedback Shift Register Shift register with input taken from XOR of state Pseudo-Random Sequence Generator Step Q ECE 261 Krish Chakrabarty PRPG Linear Feedback Shift Register Shift register with input taken from XOR of state Pseudo-Random Sequence Generator Step ECE 261 Krish Chakrabarty 24 0 Q

13 PRSG Linear Feedback Shift Register Shift register with input taken from XOR of state Pseudo-Random Sequence Generator Step 0 Q (repeats) ECE 261 Krish Chakrabarty 25 BILBO Built-in Logic Block Observer Combine scan with PRSG & signature analysis ECE 261 Krish Chakrabarty 26 1

Boundary Scan Testing boards is also difficult Need to verify solder joints are good Drive a pin to 0, then to Check that all connected pins get the values Through-hold boards used bed of nails SMT

14 Boundary Scan Testing boards is also difficult Need to verify solder joints are good Drive a pin to 0, then to Check that all connected pins get the values Through-hold boards used bed of nails SMT and BGA boards cannot easily contact pins Build capability of observing and controlling pins into each chip to make board test easier ECE 261 Krish Chakrabarty 27 Boundary Scan Example ECE 261 Krish Chakrabarty 28 1

15 Boundary Scan Interface IEEE JTAG standard Boundary scan is accessed through five pins TCK: test clock TMS: test mode select TDI: test data in TDO: test data out TRST*: test reset (optional) Chips with internal scan chains can access the chains through boundary scan for unified test strategy. ECE 261 Krish Chakrabarty 29 BIST in Industry Early days: AT&T (Lucent) incorporated BIST in hundreds of commercial chips Intel: 80386, Pentium, Pentium Pro Hardware overhead typically 15% of self-tested portion (around 5% for entire chip, e.g. 6% for the Pentium Pro) Regular embedded arrays (RAMs, PLAs) almost always tested using BIST: DEC Alpha, PowerPC BIST for irregular logic not so widespread ECE 261 Krish Chakrabarty 30 1

16 IDDQ Testing Based on current measurements, not voltage IDDQ = I DD quiescent In CMOS technology, quiescent current is very low Testing idea: check for faults by detecting current spikes Advantage: Massive observability, good for detecting shorts Disadvantage: slow, leakage current closer to quiescent current for deep submicron ECE 261 Krish Chakrabarty 31 1

Unit V Design for Testability

Unit V Design for Testability Outline Testing Logic Verification Silicon Debug Manufacturing Test Fault Models Observability and Controllability Design for Test Scan BIST Boundary Scan Slide 2 Testing