Based on slides/material by. Topic 14. Testing. Testing. Logic Verification. Recommended Reading:
|
|
|
- Gloria Carr
- 6 years ago
- Views:
Transcription
1 Based on slides/material by Topic 4 Testing Peter Y. K. Cheung Department of Electrical & Electronic Engineering Imperial College London!! K. Masselos J. Rabaey Digital Integrated Circuits: A Design Perspective, Prentice Hall!! D. Harris Weste and Harris, CMOS VLSI Design: A Circuits and Systems Perspective, Addison Wesley Recommended Reading:!! J. Rabaey et. al. Digital Integrated Circuits: A Design Perspective : Design Methodology Insert H URL: Weste and Harris, CMOS VLSI Design: A Circuits and Systems Perspective : Chapter 9 Topic 4 - Topic 4-2 Testing Logic Verification!! Testing is one of the most expensive parts of chips! Logic verification accounts for > 50% of design effort for many chips! Debug time after fabrication has enormous opportunity cost! Shipping defective parts can sink a company!! Example: Intel FDIV bug! Logic error not caught until > M units shipped! Recall cost $450M (!!!)!! Does the chip simulate correctly?! Usually done at HDL level! Verification engineers write test bench for HDL "!Can t test all cases "!Look for corner cases "!Try to break logic design!! Ex: 32-bit adder! Test all combinations of corner cases as inputs: "!0,, 2, 2 3 -, -, -2 3, a few random numbers!! Good tests require ingenuity Topic 4-3 Topic 4-4
2 Silicon Debug Shmoo Plots!! Test the first chips back from fabrication! If you are lucky, they work the first time! If not!! Logic bugs vs. electrical failures! Most chip failures are logic bugs from inadequate simulation! Some are electrical failures "!Crosstalk "!Dynamic nodes: leakage, charge sharing "!Ratio failures! A few are tool or methodology failures (e.g. DRC)!! Fix the bugs and fabricate a corrected chip!! How to diagnose failures?! Hard to access chips "! Picoprobes "! Electron beam "! Laser voltage probing "! Built-in self-test!! Shmoo plots! Vary voltage, frequency! Look for cause of electrical failures Topic 4-5 Topic 4-6 Manufacturing Test Validation and Test of Manufactured Circuits!! A speck of dust on a wafer is sufficient to kill chip!! Yield of any chip is < 00%! Must test chips after manufacturing before delivery to customers to only ship good parts!! Manufacturing testers are very expensive! Minimize time on tester! Careful selection of test vectors Goals of Design-for-Test (DFT) Make testing of manufactured part swift and comprehensive DFT Mantra Provide controllability and observability Components of DFT strategy! Provide circuitry to enable test! Provide test patterns that guarantee reasonable coverage Topic 4-7 Topic 4-8
3 Test Classification ability!! Diagnostic test! used in chip/board debugging! defect localization!! go/no go or production test! Used in chip production!! Parametric test! x e [v,i] versus x e [0,]! check parameters such as NM, Vt, tp, T Exhaustive test is impossible or unpractical Topic 4-9 Topic 4-0 Controllability/Observability!! Design the chip to increase observability and controllability!! If each register could be observed and controlled, test problem reduces to testing combinational logic between registers.!! Better yet, logic blocks could enter test mode where they generate test patterns and report the results automatically.!! Combinational Circuits: controllable and observable - relatively easy to determine test patterns!! Sequential Circuits: State! Turn into combinational circuits or use self-test!! Memory: requires complex patterns Use self-test Topic 4 - Topic 4-2
4 Generating and Validating Test-Vectors Fault Models!! Automatic test-pattern generation (ATPG)! for given fault, determine excitation vector (called test vector) that will propagate error to primary (observable) output! majority of available tools: combinational networks only! sequential ATPG available from academic research!! Fault simulation! determines test coverage of proposed test-vector set! simulates correct network in parallel with faulty networks!! Both require adequate models of faults in CMOS integrated circuits Most Popular - Stuck - at model! Covers almost all (other) occurring faults, such as opens and shorts.!, " : x sa" # : x sa0 or" x2 sa0" " : Z sa" Topic 4-3 Topic 4-4 Problem with stuck-at model: CMOS open fault Problem with stuck-at model: CMOS short fault Causes short circuit between Vdd and GND for A=C=0, B= Sequential effect Needs two vectors to ensure detection! Possible approach: Supply Current Measurement (IDDQ) but: not applicable for gigascale integration Other options: use stuck-open or stuck-short models This requires fault-simulation and analysis at the switch or transistor level - Very expensive! Topic 4-5 Topic 4-6
5 Test Pattern Generation Path Sensitization!! Manufacturing test ideally would check every node in the circuit to prove it is not stuck.!! Apply the smallest sequence of test vectors necessary to prove each node is not stuck.!! Good observability and controllability reduces number of test vectors required for manufacturing test.! Reduces the cost of testing! Motivates design-for-test Goals: Determine input pattern that makes a fault controllable (triggers the fault, and makes its impact visible at the output nodes) Fault enabling Fault propagation 0 sa0 0 Techniques Used: D-algorithm, Podem Topic 4-7 Topic 4-8 Test Example Test Approaches SA SA0!! A 3 {00} {0}!! A 2 {00} {0}!! A {000} {00}!! A 0 {00} {0}!! n {0} {00}!! n2 {00} {000}!! n3 {00} {00}!! Y {00} {0}!! Ad-hoc testing!! Scan-based Test!! Self-Test Problem is getting harder! increasing complexity and heterogeneous combination of modules in system -on-a-chip.! Advanced packaging and assembly techniques extend problem to the board level!! Minimum set: {000, 00, 00, 0, 00, 0} Topic 4-9 Topic 4-20
6 Ad-hoc Test Scan!! Convert each flip-flop to a scan register! Only costs one extra multiplexer!! Normal mode: flip-flops behave as usual!! Scan mode: flip-flops behave as shift register!! Contents of flops can be scanned out and new values scanned in Inserting multiplexer improves testability Topic 4-2 Topic 4-22 Scan-based Test Scannable Flip-flops Topic 4-23 Topic 4-24
7 Polarity-Hold SRL (Shift-Register Latch) Scan-based Test Operation Introduced at IBM and set as company policy Topic 4-25 Topic 4-26 Scan-Path Testing Boundary Scan!! Testing boards is also difficult! Need to verify solder joints are good "!Drive a pin to 0, then to "!Check that all connected pins get the values!! Through-hold boards used bed of nails!! SMT and BGA boards cannot easily contact pins!! Build capability of observing and controlling pins into each chip to make board test easier Partial-Scan can be more effective for pipelined datapaths Topic 4-27 Topic 4-28
8 Boundary Scan (JTAG) Boundary Scan Example Board testing becomes as problematic as chip testing Topic 4-29 Topic 4-30 Boundary Scan Interface Built-in Self-test!! Boundary scan is accessed through five pins! TCK: test clock! TMS: test mode select! TDI: test data in! TDO: test data out! TRST*: test reset (optional)!! Built-in self-test lets blocks test themselves! Generate pseudo-random inputs to comb. logic! Combine outputs into a syndrome! With high probability, block is fault-free if it produces the expected syndrome!! Chips with internal scan chains can access the chains through boundary scan for unified test strategy. Topic 4-3 Topic 4-32
9 Self-test PRSG!! Linear Feedback Shift Register! Shift register with input taken from XOR of state! Pseudo-Random Sequence Generator Step Q Rapidly becoming more important with increasing chip-complexity and larger modules (repeats) Topic 4-33 Topic 4-34 Linear-Feedback Shift Register (LFSR) Signature Analysis Counts transitions on single-bit stream $ Compression in time Pseudo-Random Pattern Generator Topic 4-35 Topic 4-36
10 BILBO BILBO Application Topic 4-37 Topic 4-38 BILBO Memory Self-Test!! Built-in Logic Block Observer! Combine scan with PRSG & signature analysis Patterns: Writing/Reading 0s, s, Walking 0s, s Galloping 0s, s Topic 4-39 Topic 4-40
11 Low Cost Testing TestosterICs!! If you don t have a multimillion dollar tester:! Build a breadboard with LED s and switches! Hook up a logic analyzer and pattern generator! Or use a low-cost functional chip tester!! Ex: TestosterICs functional chip tester! Designed by clinic teams and David Diaz at HMC! Reads your IRSIM test vectors, applies them to your chip, and reports assertion failures Topic 4-4 Topic 4-42 Summary!! Think about testing from the beginning! Simulate as you go! Plan for test after fabrication!! If you don t test it, it won t work! (Guaranteed) Topic 4-43
Based on slides/material by. Topic Testing. Logic Verification. Testing
Based on slides/material by Topic 4 K. Masselos http://cas.ee.ic.ac.uk/~kostas J. Rabaey http://bwrc.eecs.berkeley.edu/classes/icbook/instructors.html igital Integrated Circuits: A esign Perspective, Prentice
Unit V Design for Testability
Unit V Design for Testability Outline Testing Logic Verification Silicon Debug Manufacturing Test Fault Models Observability and Controllability Design for Test Scan BIST Boundary Scan Slide 2 Testing
Digital Integrated Circuits Lecture 19: Design for Testability
Digital Integrated Circuits Lecture 19: Design for Testability Chih-Wei Liu VLSI Signal Processing LAB National Chiao Tung University cwliu@twins.ee.nctu.edu.tw DIC-Lec19 cwliu@twins.ee.nctu.edu.tw 1 Outline
UNIT IV CMOS TESTING. EC2354_Unit IV 1
UNIT IV CMOS TESTING EC2354_Unit IV 1 Outline Testing Logic Verification Silicon Debug Manufacturing Test Fault Models Observability and Controllability Design for Test Scan BIST Boundary Scan EC2354_Unit
Lecture 17: Introduction to Design For Testability (DFT) & Manufacturing Test
Lecture 17: Introduction to Design For Testability (DFT) & Manufacturing Test Mark McDermott Electrical and Computer Engineering The University of Texas at Austin Agenda Introduction to testing Logical
EE241 - Spring 2001 Advanced Digital Integrated Circuits. References
EE241 - Spring 2001 Advanced Digital Integrated Circuits Lecture 28 References Rabaey, Digital Integrated Circuits and EE241 (1998) notes Chapter 25, ing of High-Performance Processors by D.K. Bhavsar
CMOS Testing-2. Design for testability (DFT) Design and Test Flow: Old View Test was merely an afterthought. Specification. Design errors.
Design and test CMOS Testing- Design for testability (DFT) Scan design Built-in self-test IDDQ testing ECE 261 Krish Chakrabarty 1 Design and Test Flow: Old View Test was merely an afterthought Specification
Jin-Fu Li Advanced Reliable Systems (ARES) Laboratory. National Central University
Chapter 3 Basics of VLSI Testing (2) Jin-Fu Li Advanced Reliable Systems (ARES) Laboratory Department of Electrical Engineering National Central University Jhongli, Taiwan Outline Testing Process Fault
Scan. This is a sample of the first 15 pages of the Scan chapter.
Scan This is a sample of the first 15 pages of the Scan chapter. Note: The book is NOT Pinted in color. Objectives: This section provides: An overview of Scan An introduction to Test Sequences and Test
Unit 8: Testability. Prof. Roopa Kulkarni, GIT, Belgaum. 29
Unit 8: Testability Objective: At the end of this unit we will be able to understand Design for testability (DFT) DFT methods for digital circuits: Ad-hoc methods Structured methods: Scan Level Sensitive
for Digital IC's Design-for-Test and Embedded Core Systems Alfred L. Crouch Prentice Hall PTR Upper Saddle River, NJ
Design-for-Test for Digital IC's and Embedded Core Systems Alfred L. Crouch Prentice Hall PTR Upper Saddle River, NJ 07458 www.phptr.com ISBN D-13-DflMfla7-l : Ml H Contents Preface Acknowledgments Introduction
Lecture 18 Design For Test (DFT)
Lecture 18 Design For Test (DFT) Xuan Silvia Zhang Washington University in St. Louis http://classes.engineering.wustl.edu/ese461/ ASIC Test Two Stages Wafer test, one die at a time, using probe card production
Slide Set 14. Design for Testability
Slide Set 14 Design for Testability Steve Wilton Dept. of ECE University of British Columbia stevew@ece.ubc.ca Slide Set 14, Page 1 Overview Wolf 4.8, 5.6, 5.7, 8.7 Up to this point in the class, we have
Testing Digital Systems II
Testing Digital Systems II Lecture 2: Design for Testability (I) structor: M. Tahoori Copyright 2010, M. Tahoori TDS II: Lecture 2 1 History During early years, design and test were separate The final
Instructions. Final Exam CPSC/ELEN 680 December 12, Name: UIN:
Final Exam CPSC/ELEN 680 December 12, 2005 Name: UIN: Instructions This exam is closed book. Provide brief but complete answers to the following questions in the space provided, using figures as necessary.
VLSI Test Technology and Reliability (ET4076)
VLSI Test Technology and Reliability (ET476) Lecture 9 (2) Built-In-Self Test (Chapter 5) Said Hamdioui Computer Engineering Lab Delft University of Technology 29-2 Learning aims Describe the concept and
Testing Sequential Logic. CPE/EE 428/528 VLSI Design II Intro to Testing (Part 2) Testing Sequential Logic (cont d) Testing Sequential Logic (cont d)
Testing Sequential Logic CPE/EE 428/528 VLSI Design II Intro to Testing (Part 2) Electrical and Computer Engineering University of Alabama in Huntsville In general, much more difficult than testing combinational
Design for Testability
TDTS 01 Lecture 9 Design for Testability Zebo Peng Embedded Systems Laboratory IDA, Linköping University Lecture 9 The test problems Fault modeling Design for testability techniques Zebo Peng, IDA, LiTH
Using on-chip Test Pattern Compression for Full Scan SoC Designs
Using on-chip Test Pattern Compression for Full Scan SoC Designs Helmut Lang Senior Staff Engineer Jens Pfeiffer CAD Engineer Jeff Maguire Principal Staff Engineer Motorola SPS, System-on-a-Chip Design
Overview: Logic BIST
VLSI Design Verification and Testing Built-In Self-Test (BIST) - 2 Mohammad Tehranipoor Electrical and Computer Engineering University of Connecticut 23 April 2007 1 Overview: Logic BIST Motivation Built-in
DESIGN OF RANDOM TESTING CIRCUIT BASED ON LFSR FOR THE EXTERNAL MEMORY INTERFACE
DESIGN OF RANDOM TESTING CIRCUIT BASED ON LFSR FOR THE EXTERNAL MEMORY INTERFACE Mohammed Gazi.J 1, Abdul Mubeen Mohammed 2 1 M.Tech. 2 BE, MS(IT), AMISTE ABSTRACT In the design of a SOC system, random
VLSI System Testing. BIST Motivation
ECE 538 VLSI System Testing Krish Chakrabarty Built-In Self-Test (BIST): ECE 538 Krish Chakrabarty BIST Motivation Useful for field test and diagnosis (less expensive than a local automatic test equipment)
Lecture 23 Design for Testability (DFT): Full-Scan (chapter14)
Lecture 23 Design for Testability (DFT): Full-Scan (chapter14) Definition Ad-hoc methods Scan design Design rules Scan register Scan flip-flops Scan test sequences Overheads Scan design system Summary
Testing Sequential Circuits
Testing Sequential Circuits 9/25/ Testing Sequential Circuits Test for Functionality Timing (components too slow, too fast, not synchronized) Parts: Combinational logic: faults: stuck /, delay Flip-flops:
ECE 407 Computer Aided Design for Electronic Systems. Testing and Design for Testability. Instructor: Maria K. Michael. Overview
407 Computer Aided Design for Electronic Systems Testing and Design for Testability Instructor: Maria K. Michael MKM - 1 Overview VLSI realization process Role of testing, related cost Basic Digital VLSI
Design for Test. Design for test (DFT) refers to those design techniques that make test generation and test application cost-effective.
Design for Test Definition: Design for test (DFT) refers to those design techniques that make test generation and test application cost-effective. Types: Design for Testability Enhanced access Built-In
Design of Fault Coverage Test Pattern Generator Using LFSR
Design of Fault Coverage Test Pattern Generator Using LFSR B.Saritha M.Tech Student, Department of ECE, Dhruva Institue of Engineering & Technology. Abstract: A new fault coverage test pattern generator
Department of Electrical and Computer Engineering University of Wisconsin Madison. Fall Final Examination CLOSED BOOK
Department of Electrical and Computer Engineering University of Wisconsin Madison Fall 2014-2015 Final Examination CLOSED BOOK Kewal K. Saluja Date: December 14, 2014 Place: Room 3418 Engineering Hall
VLSI Technology used in Auto-Scan Delay Testing Design For Bench Mark Circuits
VLSI Technology used in Auto-Scan Delay Testing Design For Bench Mark Circuits N.Brindha, A.Kaleel Rahuman ABSTRACT: Auto scan, a design for testability (DFT) technique for synchronous sequential circuits.
This Chapter describes the concepts of scan based testing, issues in testing, need
Chapter 2 AT-SPEED TESTING AND LOGIC BUILT IN SELF TEST 2.1 Introduction This Chapter describes the concepts of scan based testing, issues in testing, need for logic BIST and trends in VLSI testing. Scan
Simulation Mismatches Can Foul Up Test-Pattern Verification
1 of 5 12/17/2009 2:59 PM Technologies Design Hotspots Resources Shows Magazine ebooks & Whitepapers Jobs More... Click to view this week's ad screen [ D e s i g n V i e w / D e s i g n S o lu ti o n ]
Lecture 23 Design for Testability (DFT): Full-Scan
Lecture 23 Design for Testability (DFT): Full-Scan (Lecture 19alt in the Alternative Sequence) Definition Ad-hoc methods Scan design Design rules Scan register Scan flip-flops Scan test sequences Overheads
Testability: Lecture 23 Design for Testability (DFT) Slide 1 of 43
Testability: Lecture 23 Design for Testability (DFT) Shaahin hi Hessabi Department of Computer Engineering Sharif University of Technology Adapted, with modifications, from lecture notes prepared p by
Final Exam CPSC/ECEN 680 May 2, Name: UIN:
Final Exam CPSC/ECEN 680 May 2, 2008 Name: UIN: Instructions This exam is closed book. Provide brief but complete answers to the following questions in the space provided, using figures as necessary. Show
At-speed Testing of SOC ICs
At-speed Testing of SOC ICs Vlado Vorisek, Thomas Koch, Hermann Fischer Multimedia Design Center, Semiconductor Products Sector Motorola Munich, Germany Abstract This paper discusses the aspects and associated
TKK S ASIC-PIIRIEN SUUNNITTELU
Design TKK S-88.134 ASIC-PIIRIEN SUUNNITTELU Design Flow 3.2.2005 RTL Design 10.2.2005 Implementation 7.4.2005 Contents 1. Terminology 2. RTL to Parts flow 3. Logic synthesis 4. Static Timing Analysis
International Journal of Scientific & Engineering Research, Volume 5, Issue 9, September ISSN
International Journal of Scientific & Engineering Research, Volume 5, Issue 9, September-2014 917 The Power Optimization of Linear Feedback Shift Register Using Fault Coverage Circuits K.YARRAYYA1, K CHITAMBARA
Module 8. Testing of Embedded System. Version 2 EE IIT, Kharagpur 1
Module 8 Testing of Embedded System Version 2 EE IIT, Kharagpur 1 Lesson 39 Design for Testability Version 2 EE IIT, Kharagpur 2 Instructional Objectives After going through this lesson the student would
EEC 116 Fall 2011 Lab #5: Pipelined 32b Adder
EEC 116 Fall 2011 Lab #5: Pipelined 32b Adder Dept. of Electrical and Computer Engineering University of California, Davis Issued: November 2, 2011 Due: November 16, 2011, 4PM Reading: Rabaey Sections
7 Nov 2017 Testing and programming PCBA s
7 Nov 207 Testing and programming PCBA s Rob Staals JTAG Technologies Email: robstaals@jtag.com JTAG Technologies The importance of Testing Don t ship bad products to your customers, find problems before
the Boundary Scan perspective
the Boundary Scan perspective Rik Doorneweert, JTAG Technologies rik@jtag.com www.jtag.com Subjects Economics of testing Test methods and strategy Boundary scan at: Component level Board level System level
Testing Digital Systems II
Testing Digital Systems II Lecture 5: Built-in Self Test (I) Instructor: M. Tahoori Copyright 2010, M. Tahoori TDS II: Lecture 5 1 Outline Introduction (Lecture 5) Test Pattern Generation (Lecture 5) Pseudo-Random
K.T. Tim Cheng 07_dft, v Testability
K.T. Tim Cheng 07_dft, v1.0 1 Testability Is concept that deals with costs associated with testing. Increase testability of a circuit Some test cost is being reduced Test application time Test generation
Ilmenau, 9 Dec 2016 Testing and programming PCBA s. 1 JTAG Technologies
Ilmenau, 9 Dec 206 Testing and programming PCBA s JTAG Technologies The importance of Testing Don t ship bad products to your customers, find problems before they do. DOA s (Death On Arrival) lead to huge
New Directions in Manufacturing Test
New Directions in Manufacturing Test Jacob A. Abraham Computer Engineering Research Center The University of Texas at Austin Shanghai Jiao Tong University July 19, 2005 July 19, 2005 1 Research Areas Manufacturing
Full scan testing of handshake circuits. Frank J. te Beest
Full scan testing of handshake circuits Frank J. te Beest 2003 Ph.D. thesis University of Twente Twente University Press Also available in print: http://www.tup.utwente.nl/ Full scan testing of handshake
ECE 715 System on Chip Design and Test. Lecture 22
ECE 75 System on Chip Design and Test Lecture 22 Response Compaction Severe amounts of data in CUT response to LFSR patterns example: Generate 5 million random patterns CUT has 2 outputs Leads to: 5 million
At-speed testing made easy
At-speed testing made easy By Bruce Swanson and Michelle Lange, EEdesign.com Jun 03, 2004 (5:00 PM EDT) URL: http://www.eedesign.com/article/showarticle.jhtml?articleid=21401421 Today's chip designs are
Saving time & money with JTAG
Saving time & money with JTAG AltiumLive 2017: ANNUAL PCB DESIGN SUMMIT Simon Payne CEO, XJTAG Ltd. Saving time and money with JTAG JTAG / IEEE 1149.X Take-away points Get JTAG right from the start Use
16 Dec Testing and Programming PCBA s. 1 JTAG Technologies
6 Dec 24 Testing and Programming PCBA s JTAG Technologies The importance of Testing Don t ship bad products to your customers, find problems before they do. DOA s (Death On Arrival) lead to huge costs
Chapter 8 Design for Testability
電機系 Chapter 8 Design for Testability 測試導向設計技術 2 Outline Introduction Ad-Hoc Approaches Full Scan Partial Scan 3 Design For Testability Definition Design For Testability (DFT) refers to those design techniques
nmos transistor Basics of VLSI Design and Test Solution: CMOS pmos transistor CMOS Inverter First-Order DC Analysis CMOS Inverter: Transient Response
nmos transistor asics of VLSI Design and Test If the gate is high, the switch is on If the gate is low, the switch is off Mohammad Tehranipoor Drain ECE495/695: Introduction to Hardware Security & Trust
18 Nov 2015 Testing and Programming PCBA s. 1 JTAG Technologies
8 Nov 25 Testing and Programming PCBA s JTAG Technologies The importance of Testing Don t ship bad products to your customers, find problems before they do. DOA s (Death On Arrival) lead to huge costs
Page 1 of 6 Follow these guidelines to design testable ASICs, boards, and systems. (includes related article on automatic testpattern generation basics) (Tutorial) From: EDN Date: August 19, 1993 Author:
DESIGN FOR TESTABILITY
DESIGN FOR TESTABILITY Raimund Ubar raiub@pld.ttu.ee Design for Testability Lectures Testability of Digital Systems Design for Testability Methods BIST/BISD Practical Works Two laboratory works Course
Design of Test Circuits for Maximum Fault Coverage by Using Different Techniques
Design of Test Circuits for Maximum Fault Coverage by Using Different Techniques Akkala Suvarna Ratna M.Tech (VLSI & ES), Department of ECE, Sri Vani School of Engineering, Vijayawada. Abstract: A new
Advances in VLSI Testing at MultiGb per Second Rates
SERBIAN JOURNAL OF ELECTRICAL ENGINEERING Vol. 2, No. 1, May 2005, 43-55 Advances in VLSI Testing at MultiGb per Second Rates Dragan Topisiroviç 1 Abstract: Today's high performance manufacturing of digital
Bit Swapping LFSR and its Application to Fault Detection and Diagnosis Using FPGA
Bit Swapping LFSR and its Application to Fault Detection and Diagnosis Using FPGA M.V.M.Lahari 1, M.Mani Kumari 2 1,2 Department of ECE, GVPCEOW,Visakhapatnam. Abstract The increasing growth of sub-micron
Department of Information Technology and Electrical Engineering. VLSI III: Test and Fabrication of VLSI Circuits L.
Institut für Integrierte Systeme Integrated Systems Laboratory Department of Information Technology and Electrical Engineering VLSI III: Test and Fabrication of VLSI Circuits 227-0148-00L Exercise 7 Speed
A Novel Low Power pattern Generation Technique for Concurrent Bist Architecture
A Novel Low Power pattern Generation Technique for Concurrent Bist Architecture Y. Balasubrahamanyam, G. Leenendra Chowdary, T.J.V.S.Subrahmanyam Research Scholar, Dept. of ECE, Sasi institute of Technology
Avoiding False Pass or False Fail
Avoiding False Pass or False Fail By Michael Smith, Teradyne, October 2012 There is an expectation from consumers that today s electronic products will just work and that electronic manufacturers have
CSE 352 Laboratory Assignment 3
CSE 352 Laboratory Assignment 3 Introduction to Registers The objective of this lab is to introduce you to edge-trigged D-type flip-flops as well as linear feedback shift registers. Chapter 3 of the Harris&Harris
Cell-Aware Fault Analysis and Test Set Optimization in Digital Integrated Circuits
Southern Methodist University SMU Scholar Computer Science and Engineering Theses and Dissertations Computer Science and Engineering Spring 5-19-2018 Cell-Aware Fault Analysis and Test Set Optimization
Built-In Self-Test (BIST) Abdil Rashid Mohamed, Embedded Systems Laboratory (ESLAB) Linköping University, Sweden
Built-In Self-Test (BIST) Abdil Rashid Mohamed, abdmo@ida ida.liu.se Embedded Systems Laboratory (ESLAB) Linköping University, Sweden Introduction BIST --> Built-In Self Test BIST - part of the circuit
Sequential Design Basics
Sequential Design Basics Lecture 2 topics A review of devices that hold state A review of Latches A review of Flip-Flops Unit of text Set-Reset Latch/Flip-Flops/D latch/ Edge triggered D Flip-Flop 8/22/22
Y. Tsiatouhas. VLSI Systems and Computer Architecture Lab. Built-In Self Test 2
CMOS INTEGRATE CIRCUIT ESIGN TECHNIUES University of Ioannina Built In Self Test (BIST) ept. of Computer Science and Engineering Y. Tsiatouhas CMOS Integrated Circuit esign Techniques VLSI Systems and
[Krishna*, 4.(12): December, 2015] ISSN: (I2OR), Publication Impact Factor: 3.785
![[Krishna*, 4.(12): December, 2015] ISSN: (I2OR), Publication Impact Factor: 3.785](/thumbs/84/89645202.jpg "[Krishna*, 4.(12): December, 2015] ISSN: (I2OR), Publication Impact Factor: 3.785")
IJESRT INTERNATIONAL JOURNAL OF ENGINEERING SCIENCES & RESEARCH TECHNOLOGY DESIGN AND IMPLEMENTATION OF BIST TECHNIQUE IN UART SERIAL COMMUNICATION M.Hari Krishna*, P.Pavan Kumar * Electronics and Communication
ISSN (c) MIT Publications
MIT International Journal of Electronics and Communication Engineering, Vol. 2, No. 2, Aug. 2012, pp. (83-88) 83 BIST- Built in Self Test A Testing Technique Alpana Singh MIT, Moradabad, UP, INDIA Email:
Introduction to JTAG / boundary scan-based testing for 3D integrated systems. (C) GOEPEL Electronics -
Introduction to JTAG / boundary scan-based testing for 3D integrated systems (C) 2011 - GOEPEL Electronics - www.goepelusa.com Who is GOEPEL? World Headquarters: GÖPEL electronic GmbH Göschwitzer Straße
Tools to Debug Dead Boards
Tools to Debug Dead Boards Hardware Prototype Bring-up Ryan Jones Senior Application Engineer Corelis 1 Boundary-Scan Without Boundaries click to start the show Webinar Outline What is a Dead Board? Prototype
Design and Implementation OF Logic-BIST Architecture for I2C Slave VLSI ASIC Design Using Verilog
Design and Implementation OF Logic-BIST Architecture for I2C Slave VLSI ASIC Design Using Verilog 1 Manish J Patel, 2 Nehal Parmar, 3 Vishwas Chaudhari 1, 2, 3 PG Students (VLSI & ESD) Gujarat Technological
Diagnosis of Resistive open Fault using Scan Based Techniques
Diagnosis of Resistive open Fault using Scan Based Techniques 1 Mr. A. Muthu Krishnan. M.E., (Ph.D), 2. G. Chandra Theepa Assistant Professor 1, PG Scholar 2,Dept. of ECE, Regional Office, Anna University,
VLSI Design Verification and Test BIST II CMPE 646 Space Compaction Multiple Outputs We need to treat the general case of a k-output circuit.
Space Compaction Multiple Outputs We need to treat the general case of a k-output circuit. Test Set L m CUT k LFSR There are several possibilities: Multiplex the k outputs of the CUT. M 1 P(X)=X 4 +X+1
Failure Analysis Technology for Advanced Devices
ISHIYAMA Toshio, WADA Shinichi, KUZUMI Hajime, IDE Takashi Abstract The sophistication of functions, miniaturization and reduced weight of household appliances and various devices have been accelerating
Topic 8. Sequential Circuits 1
Topic 8 Sequential Circuits 1 Peter Cheung Department of Electrical & Electronic Engineering Imperial College London Rabaey Chapter 7 URL: www.ee.ic.ac.uk/pcheung/ E-mail: p.cheung@ic.ac.uk 1 Based on
A Briefing on IEEE Standard Test Access Port And Boundary-Scan Architecture ( AKA JTAG )
A Briefing on IEEE 1149.1 1990 Standard Test Access Port And Boundary-Scan Architecture ( AKA JTAG ) Summary With the advent of large Ball Grid Array (BGA) and fine pitch SMD semiconductor devices the
Laboratory 1 - Introduction to Digital Electronics and Lab Equipment (Logic Analyzers, Digital Oscilloscope, and FPGA-based Labkit)
Massachusetts Institute of Technology Department of Electrical Engineering and Computer Science 6. - Introductory Digital Systems Laboratory (Spring 006) Laboratory - Introduction to Digital Electronics
Project 6: Latches and flip-flops
Project 6: Latches and flip-flops Yuan Ze University epartment of Computer Engineering and Science Copyright by Rung-Bin Lin, 1999 All rights reserved ate out: 06/5/2003 ate due: 06/25/2003 Purpose: This
Design for test methods to reduce test set size
University of Iowa Iowa Research Online Theses and Dissertations Summer 2018 Design for test methods to reduce test set size Yingdi Liu University of Iowa Copyright 2018 Yingdi Liu This dissertation is
CPE 628 Chapter 5 Logic Built-In Self-Test. Dr. Rhonda Kay Gaede UAH. UAH Chapter Introduction
Chapter 5 Logic Built-In Self-Test Dr. Rhonda Kay Gaede UAH 1 5.1 Introduction Introduce the basic concepts of BIST BIST Rules Test pattern generation and output techniques Fault Coverage Various BIST
IMPLEMENTATION OF X-FACTOR CIRCUITRY IN DECOMPRESSOR ARCHITECTURE
IMPLEMENTATION OF X-FACTOR CIRCUITRY IN DECOMPRESSOR ARCHITECTURE SATHISHKUMAR.K #1, SARAVANAN.S #2, VIJAYSAI. R #3 School of Computing, M.Tech VLSI design, SASTRA University Thanjavur, Tamil Nadu, 613401,
Testing Digital Systems II
Testing Digital Systems II Lecture 7: Built-in Self Test (III) Instructor: M. Tahoori Copyright 206, M. Tahoori TDS II: Lecture 7 BIST Architectures Copyright 206, M. Tahoori TDS II: Lecture 7 2 Lecture
Using the XC9500/XL/XV JTAG Boundary Scan Interface
Application Note: XC95/XL/XV Family XAPP69 (v3.) December, 22 R Using the XC95/XL/XV JTAG Boundary Scan Interface Summary This application note explains the XC95 /XL/XV Boundary Scan interface and demonstrates
Section 24. Programming and Diagnostics
Section. and Diagnostics HIGHLIGHTS This section of the manual contains the following topics:.1 Introduction... -2.2 In-Circuit Serial... -2.3 Enhanced In-Circuit Serial... -5.4 JTAG Boundary Scan... -6.5
EEC 118 Lecture #9: Sequential Logic. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation
EEC 118 Lecture #9: Sequential Logic Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation Outline Review: Static CMOS Logic Finish Static CMOS transient analysis Sequential
data and is used in digital networks and storage devices. CRC s are easy to implement in binary
Introduction Cyclic redundancy check (CRC) is an error detecting code designed to detect changes in transmitted data and is used in digital networks and storage devices. CRC s are easy to implement in
New tests and test methodologies for scan cell internal faults
University of Iowa Iowa Research Online Theses and Dissertations Fall 2009 New tests and test methodologies for scan cell internal faults Fan Yang University of Iowa Copyright 2009 Fan Yang This dissertation
Chapter 5 Flip-Flops and Related Devices
Chapter 5 Flip-Flops and Related Devices Chapter 5 Objectives Selected areas covered in this chapter: Constructing/analyzing operation of latch flip-flops made from NAND or NOR gates. Differences of synchronous/asynchronous
VLSI Chip Design Project TSEK06
VLSI Chip Design Project TSEK06 Project Description and Requirement Specification Version 1.1 Project: High Speed Serial Link Transceiver Project number: 4 Project Group: Name Project members Telephone
Diagnosis, Modeling and Tolerance of Scan Chain Hold-Time Violations
Diagnosis, Modeling and Tolerance of Scan Chain Hold-Time Violations Ozgur Sinanoglu Math & Computer Science Department Kuwait University Safat, Kuwait 13060 ozgur@sci.kuniv.edu.kw Philip Schremmer Qualcomm
CMOS Latches and Flip-Flops
CMOS Latches and Flip-Flops João Canas Ferreira University of Porto Faculty of Engineering 2016-05-04 Topics 1 General Aspects 2 Circuits based on positive feedback 3 Circuits based on charge storage João
Strategies for Efficient and Effective Scan Delay Testing. Chao Han
Strategies for Efficient and Effective Scan Delay Testing by Chao Han A thesis submitted to the Graduate Faculty of Auburn University in partial fulfillment of the requirements for the Degree of Master
Implementation of Scan Insertion and Compression for 28nm design Technology
Implementation of Scan Insertion and Compression for 28nm design Technology 1 Mohan PVS, 2 Rajanna K.M 1 PG Student, Department of ECE, Dr. Ambedkar Institute of Technology, Bengaluru, India 2 Associate
ELF-Murphy Data on Defects and Test Sets
ELF-Murphy Data on Defects and Test Sets E. J. McCluskey, Ahmad Al-Yamani, James C.-M Li, Chao-Wen Tseng, Erik Volkerink, Francois-Fabien Ferhani, Edward Li, and Subhasish Mitra Stanford Center for Reliable
Product Update. JTAG Issues and the Use of RT54SX Devices
Product Update Revision Date: September 2, 999 JTAG Issues and the Use of RT54SX Devices BACKGROUND The attached paper authored by Richard B. Katz of NASA GSFC and J. J. Wang of Actel describes anomalies
3. Configuration and Testing
3. Configuration and Testing C51003-1.4 IEEE Std. 1149.1 (JTAG) Boundary Scan Support All Cyclone devices provide JTAG BST circuitry that complies with the IEEE Std. 1149.1a-1990 specification. JTAG boundary-scan
Introduction to CMOS VLSI Design (E158) Lab 3: Datapath and Zipper Assembly
Harris Introduction to CMOS VLSI Design (E158) Lab 3: Datapath and Zipper Assembly An n-bit datapath consists of n identical horizontal bitslices 1. Data signals travel horizontally along the bitslice.
BSDL Validation: A Case Study
ASSET InterTech, Inc. Validation: A Case Study Michael R. Johnson Sr. Applications Engineer ASSET InterTech, Inc. Agilent Boundary Scan User Group Meeting December 15, 2008 About The Presenter Michael
Comparing Functional and Structural Tests
Comparing Functional and Structural Tests Peter Maxwell, Ismed Hartanto and Lee Bentz Imaging Electronics Division Agilent Technologies ABSTRACT This paper describes an experimental study to understand
ME 515 Mechatronics. Introduction to Digital Electronics
ME 55 Mechatronics /5/26 ME 55 Mechatronics Digital Electronics Asanga Ratnaweera Department of Faculty of Engineering University of Peradeniya Tel: 8239 (3627) Email: asangar@pdn.ac.lk Introduction to