Digital Principles and Design

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1 Digital Principles and Design Donald D. Givone University at Buffalo The State University of New York Grauu Boston Burr Ridge, IL Dubuque, IA Madison, Wl New York San Francisco St. Louis Bangkok Bogota Caracas Kuala Lumpur Lisbon London Madrid Mexico City Milan Montreal New Delhi Santiago Seoul Singapore Sydney Taipei Toronto

2 CONTENTS Preface xiii P.haptfir 1 Introduction The Digital Age Analog and Digital Representations of Information The Digital Computer The Organization of a Digital Computer The Operation of a Digital Computer An Overview 5 Number Systems, Arithmetic, and Codes Positional Number Systems Counting in a Positional Number System Basic Arithmetic Operations Addition Subtraction Multiplication Division Polynomial Method of Number Conversion Iterative Method of Number Conversion Iterative Method for Converting Integers Verification of the Iterative Method for Integers Iterative Method for Converting Fractions Verification of the Iterative Method for Fractions A Final Example Special Conversion Procedures Signed Numbers and Complements Addition and Subtraction with r's- Complements Signed Addition and Subtraction Addition and Subtraction with (r - l)'s- Complements Signed Addition and Subtraction Codes Decimal Codes Unit-Distance Codes Alphanumeric Codes 2.11 Error Detection Error Correction Hamming Code Single-Error Correction plus Double-Error Detection Check Sum Digits for Error Correction 54 Problems Boolean Algebra and Combinational Networks 3.1 Definition of a Boolean Algebra Principle of Duality Boolean Algebra Theorems A Two-Valued Boolean Algebra 3.4 Boolean Formulas and Functions Normal Formulas vii

3 viii DIGITAL PRINCIPLES AND DESIGN 3.5 Canonical Formulas Minterm Canonical Formulas m-notation Maxterm Canonical Formulas M-Notation Manipulations of Boolean Formulas Equation Complementation Expansion about a Variable Equation Simplification The Reduction Theorems Minterm Canonical Formulas Maxterm Canonical Formulas Complements of Canonical Formulas Gates and Combinational Networks Gates Combinational Networks Analysis Procedure Synthesis Procedure A Logic Design Example Incomplete Boolean Functions and Don't- Care Conditions Describing Incomplete Boolean Functions Don't-Care Conditions in Logic Design Additional Boolean Operations and Gates The Nand-Function The Nor-Function Universal Gates Nand-Gate Realizations Nor-Gate Realizations The Exclusive-Or-Function The Exclusive-Nor-Function Gate Properties Noise Margins Fan-Out Propagation Delays Power Dissipation 118 Problems 118 Chapter A Simplification of Boolean Expressions Formulation of the Simplification Problem Criteria of Minimality The Simplification Problem Prime Implicants and Irredundant Disjunctive Expressions Implies Subsumes Implicants and Prime Implicants Irredundant Disjunctive Normal Formulas Prime Implicates and Irredundant Conjunctive Expressions Karnaugh Maps One-Variable and Two-Variable Maps Three-Variable and Four-Variable Maps Karnaugh Maps and Canonical Formulas Product and Sum Term Representations on Karnaugh Maps Using Karnaugh Maps to Obtain Minimal Expressions for Complete Boolean Functions Prime Implicants and Karnaugh Maps Essential Prime Implicants "Minimal Sums Minimal Products Minimal Expressions of Incomplete Boolean Functions Minimal Sums Minimal Products Five-Variable and Six-Variable Karnaugh Maps Five-Variable Maps Six-Variable Maps 163

4 CONTENTS 4.8 The Quine-McCluskey Method of Generating Prime Implicants and Prime Implicates Prime Implicants and the Quine-McCluskey Method Algorithm for Generating Prime Implicants Prime Implicates and the Quine-McCluskey Method Prime-Implicant/Prime-Impricate Tables and Irredundant Expressions Petrick' s Method of Determining Irredundant Expressions Prime-Implicate Tables and Irredundant Conjunctive Normal Formulas Prime-Implicant/Prime-Implicate Table Reductions Essential Prime Implicants Column and Row Reductions A Prime-Implicant Selection Procedure Decimal Method for Obtaining Prime Implicants The Multiple-Output Simplification Problem Multiple-Output Prime Implicants Obtaining Multiple-Output Minimal Sums and Products Tagged Product Terms Generating the Multiple-Output Prime Implicants Multiple-Output Prime-Implicant Tables Minimal Sums Using Petrick's Method Minimal Sums Using Table Reduction Techniques Multiple-Output Minimal Products Variable-Entered Karnaugh Maps Constructing Variable-Entered Maps Reading Variable-Entered Maps for Minimal Sums Minimal Products Incompletely Specified Functions Maps Whose Entries Are Not Single- Variable Functions 218 Problems 222 Chapter 5 Logic Design with MSI Components and Programmable Logic Devices Binary Adders and Subtracters Binary Subtracters Carry Lookahead Adder Large High-Speed Adders Using the Carry Lookahead Principle Decimal Adders Comparators Decoders Logic Design Using Decoders Decoders with an Enable Input Encoders Multiplexers Logic Design with Multiplexers Programmable Logic Devices (PLDs) PLD Notation Programmable Read-Only Memories (PROMs) Programmable Logic Arrays (PLAs) Programmable Array Logic (PAL) Devices 292 Problems 294 ChaptPir 6 Flip-Flops and Simple Flip-Flop Applications The Basic Bistable Element Latches The SR Latch An Application of the SR Latch: A Switch Debouncer The SR Latch 307

5 DIGITAL PRINCIPLES AND DESIGN The Gated SR Latch The Gated D Latch Timing Considerations Propagation Delays Minimum Pulse Width Setup and Hold Times Master-Slave Flip-Flops (Pulse-Triggered Hip-Flops) The Master-Slave SR Flip-Flop The Master-Slave JK Flip-Flop ' s and 1' s Catching Additional Types of Master-Slave Flip-Flops Edge-Triggered Flip-Flops The Positive-Edge-Triggered D Flip-Flop Negative-Edge-Triggered D Flip-Flops Asynchronous Inputs Additional Types of Edge-Triggered Flip-Flops Master-Slave Flip-Flops with Data Lockout Characteristic Equations Registers Counters Binary Ripple Counters Synchronous Binary Counters Counters Based on Shift Registers Design of Synchronous Counters Design of a Synchronous Mod-6 Counter Using Clocked JK Flip-Flops Design of a Synchronous Mod-6 Counter Using Clocked D, T, or SR Flip-Flops Self-Correcting Counters 356 Problems 358 Chapter 7 Synchronous Sequential Networks Structure and Operation of Clocked Synchronous Sequential Networks Analysis of Clocked Synchronous Sequential Networks Excitation and Output Expressions Transition Equations Transition Tables Excitation Tables State Tables State Diagrams Network Terminal Behavior Modeling Clocked Synchronous Sequential Network Behavior The Serial Binary Adder as a Mealy Network The Serial Binary Adder as a Moore Network A Sequence Recognizer A 0110/1001 Sequence Recognizer A Final Example State Table Reduction Determining Equivalent Pairs of States Obtaining the Equivalence Classes of States Constructing the Minimal State Table The 0110/1001 Sequence Recognizer The State Assignment Some Simple Guidelines for Obtaining State Assignments Unused States Completing the Design of Clocked Synchronous Sequential Networks Realizations Using Programmable Logic Devices 432 Problems 436 Chaptfir 8 Algorithmic State Machines The Algorithmic State Machine ASM Charts The State Box The Decision Box The Conditional Output Box 450

6 CONTENTS Xi ASM Blocks ASM Charts Relationship between State Diagrams and ASM Charts Two Examples of Synchronous Sequential Network Design Using ASM Charts A Sequence Recognizer A Parallel (Unsigned) Binary Multiplier State Assignments ASM Tables ASM Transition Tables Assigned ASM Transition Tables Algebraic Representation of Assigned Transition Tables ASM Excitation Tables ASM Realizations Realizations Using Discrete Gates Realizations Using Multiplexers Realizations Using PLAs Realizations Using PROMs Asynchronous Inputs 491 Problems 493 Chapter 9 Asynchronous Sequential Networks Structure and Operation of Asynchronous Sequential Networks Analysis of Asynchronous Sequential Networks The Excitation Table The Transition Table The State Table The Flow Table The Flow Diagram Races in Asynchronous Sequential Networks The Primitive Flow Table The Primitive Flow Table for Example The Primitive Flow Table for Example Reduction of Input-Restricted Flow Tables Determination of Compatible Pairs of States Determination of Maximal Compatibles Determination of Minimal Collections of Maximal Compatible Sets Constructing the Minimal-Row Flow Table A General Procedure to Flow Table Reduction Reducing the Number of Stable States Merging the Rows of a Primitive Flow Table The General Procedure Applied to Input- Restricted Primitive Flow Tables The State-Assignment Problem and the Transition Table The Transition Table for Example The Transition Table for Example The Need for Additional State Variables A Systematic State-Assignment Procedure Completing the Asynchronous Sequential Network Design Static and Dynamic Hazards in Combinational Networks Static Hazards Detecting Static Hazards Eliminating Static Hazards Dynamic Hazards Hazard-Free Combinational Logic Networks Hazards in Asynchronous Networks Involving Latches Essential Hazards Example of an Essential Hazard Detection of Essential Hazards 575 Problems 578

7 xii DIGITAL PRINCIPLES AND DESIGN Appendix A Digital Circuits 589 A.I The pn Junction Semiconductor Diode 590 A.I.I Semiconductor Diode Behavior 590 A.1.2 Semiconductor Diode Models 592 A.2 Diode Logic 593 A.2.1 The Diode And-Gate 594 A.2.2 The Diode Or-Gate 595 A.2.3 Negative Logic 596 A.3 The Bipolar Junction Transistor 597 A.3.1 Simplified dc Transistor Operation 598 A.3.2 Normal Active Mode 600 A.3.3 Inverted Active Mode 602 A.3.4 Cutoff Mode 603 A.3.5 Saturation Mode 605 A.3.6 Silicon npn Transistor Characteristics 606 A.3.7 Summary 608 A.4 The Transistor Inverter 608 A.4.1 Loading Effects 611 A.5 Gate Performance Considerations 614 A.5.1 Noise Margins 614 A.5.2 Fan-Out 616 A.5.3 Speed of Operation and Propagation Delay Times 616 A.5.4 Power Dissipation 618 A.6 Diode-Transistor Logic (DTL) 618 A.6.1 Loading Effects 620 A.6.2 Modified DTL 621 A.7 Transistor-Transistor Logic (TTL) 622 A.7.1 Wired Logic 625 A.7.2 TTL with Totem-Pole Output 626 A.7.3 Three-State Output TTL 630 A.7.4 SchottkyTTL 632 A.7.5 Concluding Remarks 634 A.8 Emitter-Coupled Logic (ECL) 634 A.8.1 The Current Switch 635 A.8.2 The Emitter-Follower Level Restorers 638 A.8.3 The Reference Supply 639 A.8.4 Wired Logic 639 A.9 The MOS Field-Effect Transistor 641 A.9.1 A.9.2 Operation of the n-channel, Enhancement- Type MOSFET 641 The w-channel, Depletion-Type MOSFET 645 A.9.3 Thep-ChannelMOSFETs 646 A.9.4 Circuit Symbols 646 A.9.5 The MOSFET as a Resistor 647 A.9.6 Concluding Remarks 648 A.10 NMOS and PMOS Logic 649 A.10.1 The NMOS Inverter (Not-Gate) 649 A.10.2 NMOS Nor-Gate 650 A.10.3 NMOS Nand-Gate 651 A.10.4 PMOS Logic 652 A.10.5 Performance 652 A.ll CMOS Logic 654 A.11.1 The CMOS Inverter (Not-Gate) 654 A.11.2 CMOS Nor-Gate 655 A.11.3 CMOS Nand-Gate 656 A.11.4 Performance 657 Problems 657 Appendix B Tutorials 665 B.I A Gentle Introduction to Altera MAX+plus II10.1 Student Edition 665 B.2 A Gentle Introduction to LogicWorks Bibliography 684 Index 687 Additional Resources 1. CD-ROM with Altera MAX+plus II and Multisim 2001 (included with book) 2. Website at that includes labs for both Altera MAX+plus II and LogicWorks 4

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