Texas Instruments TNETE2201 Ethernet Transceiver Circuit Analysis

Transcription

1 October 31, 2003 Texas Instruments TNETE2201 Ethernet Transceiver Circuit Analysis Table of Contents List of Figures...Page 1 Introduction...Page 4 Device Summary Sheet...Page 6 Top Level Diagram...Tab 1 Parallel / Serial Converter...Tab 2 Serial / Parallel Converter...Tab 3 Synchronous Detect...Tab 4 Receiver PLL...Tab 5 Transmitter PLL (Clock Multiplier)...Tab 6 PLL Lock Detector...Tab 7 Received Data Output Multiplexer...Tab 8 Input Buffers...Tab 9 Output Buffers...Tab 10 Power Up...Tab 11 Symbol and Signal Naming Conventions...Tab 12 Signal Cross-Reference...Tab 13 For questions, comments, or more information about this report, or for any additional technical needs concerning semiconductor technology, please call Sales at Chipworks. F1.2

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3 Texas Instruments TNETE2201 Ethernet Transceiver Page 1 List of Figures Package Markings Package X-Ray Pin Configuration Die Markings Die Photograph Annotated Die Photograph Die Architecture Power Busing Architecture (top metal layer) Power Busing Architecture (bottom metal layer) Power Busing Architecture (polysilicon layer) Detailed Power Busing Architecture Layout of Power Busing (top metal layer) Close-up of Guard Rings (metal layers removed) FESEM Cross-Section of Guard Rings (silicon stain) FESEM Cross-Sectional Guard Rings at Y-Y [1] (oxide stain) FESEM Cross-Section of Decoupling Capacitance at Y-Y [2] (oxide stain) Bipolar Transistor Definitions ECL Flip-Flop 1 Definition ECL Flip-Flop 2 Definition ECL Flip-Flop 3 Definition ECL Flip-Flop 4 Definition ECL Latch Definition ECL Inverter/Buffer Definition ECL Complementary Level Shifter 1 Definition ECL Complementary Level Shifter 2 Definition ECL Single Level Shifter Definition ECL 2:1 Multiplexer Definition ECL NAND Definition ECL XOR Definition CMOS-ECL Level Shifter Definition CMOS D Flip-Flop 1 Definition CMOS D Flip-Flop 2 Definition CMOS D Flip-Flop 3 Definition CMOS D Flip-Flop 4 Definition CMOS 2:1 Multiplexer Definition CMOS XOR Definition Top Level Diagram Parallel/Serial Converter Bit Transmitter Register

4 Texas Instruments TNETE2201 Ethernet Transceiver Page :1 Transmitter MUX TX Output Buffer Transmitter Bias Serial/Parallel Converter Bit Receiver Shift Register Receiver Shift Register Received Data Sense Amplifier Comma Detector Comma Detector Bias Synchronous Detect K28.5 Misalignment Detector K28.5 Character Decoder Data Realignment Decoder Clock Stretch Register RBC Divider RBC/Test Multiplexer SYNC Pulse Output Synchronous Enable Receiver PLL RX Input Buffer Data-in/Loop-back MUX Phase Detector I and Data Retiming Charge Pump I Receiver PLL Filter Voltage Controlled Oscillator I VCO I Cell Test Multiplexer Phase Detector II Charge Pump II Recovered Clock Divider Recovered Clock Divider (part I) Recovered Clock Divider (part II) Receiver Output Clocks Receiver PLL BIAS Receiver PLL Bias I Receiver PLL Bias II Receiver PLL Bias III Transmitter PLL (Clock Multiplier) Phase Detector III Charge Pump III

5 Texas Instruments TNETE2201 Ethernet Transceiver Page Transmitter PLL Filter Voltage Controlled Oscillator II VCO II Cell Transmitter Clock Divider Transmitter PLL BIAS Transmitter BIAS I Transmitter PLL Bias II Transmitter BIAS III PLL Lock Detector Reference Clock LFSR Reset Pulse Generator Recovered Clock LFSR Lock Counter Received Data Output Multiplexer Input Buffers Input Buffer {REFCLK} Input Buffer {RESERVED} Input Buffer TD Register Clocks Generator Bias Generator Output Buffers Output Buffer Power Up Start-Up Timer Power-Up Bias Generator Receiver Bias A.1.0 Symbol Conventions A.2.0 Symbol Definitions - 1 A.2.1 Symbol Definitions - 2 A.3.0 Logic Gate Size Notation A.4.0 Transistor Size Notation A.5.0 Capacitor Size Notation