ECE337 Lab 4 Introduction to State Machines in VHDL

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1 ECE337 Lab Introduction to State Machines in VHDL In this lab you will: Design, code, and test the functionality of the source version of a Moore model state machine of a sliding window average filter. Synthesize, test, and verify the functionality of the mapped version of a Moore model state machine of sliding window average filter. Prelab Exercises For this lab it is required that the following things be completed before the start of lab: Create a Moore model state machine for a 1101 sequence detector (moore.vhd). Create a Mealy model state machine for a 1101 sequence detector (mealy.vhd). Print off and hand in waveforms that clearly verify that moore.vhd and mealy.vhd each work properly (source version is all that is required, one copy per team). Draw a state diagram for a two-point averaging filter and a four-point averaging filter. Also write pseudo-code for the four-point averaging filter. Electronically turn in your VHDL code and pseudo-code using the command autoturnin p. (Everyone) Lab Rules and Teamwork Report For this lab you will be working with a partner. Please see the Teamwork Guidelines document posted with this handout for details on what is and is not acceptable collaboration. You will also need to fill out a teamwork report after the lab as outlined by the Teamwork Guidelines document. Overall Design For this lab you will be designing an ASIC that reads in data samples and outputs the average of the last four samples, as well as keeping track of the number of samples processed. This sort of design is called a sliding-window average, and is a simple example of a digital filter. Such a design would be useful for smoothing an A/D conversion to reduce noise, for example. The RTL diagram of the system is given to you in Figure 1. Although the hardware described in this lab is not the most efficient way to solve this simple problem, it is very extensible, and the function of the system could be easily changed to do a much more complicated task with very little change to the RTL diagram. 1

2 The inputs and outputs of the top level are given here. (A more detailed description will be given with the description of the top level file itself.) SIGNAL DIRECTION DESCRIPTION clk Input 200MHz System clock nreset Input Active low reset data <15:0> Input -bit unsigned data input. data_ready Input Indicates that data is valid and may be read. count_out <15:0> Output How many samples have been read. modwait Output Indicates that the state machine is busy avg_out <15:0> Output This is the output of the average of the last for samples err Output Indicates that an overflow occurred during averaging. The asynchronous input data_ready must first be synchronized in order to be used by the system. When the synchronized signal, dr, goes high, it signals to the control unit that valid data is on the data signal and that the system should process a new sample. The control unit is responsible for telling the datapath block which operations to perform, in order, and where to store the values. It also pulses the cnt_up signal to increment the counter block and keep track of the number of samples processed. Additionally, the control unit must manage two top-level outputs: modwait, which tells the user that a sample is being processed; and err, which indicates an error in processing the samples. The datapath itself outputs the result of the operation, stored in a special output register. Before being presented to the user, the result (the summation of the last four samples) is divided by four. 2

3 data_ready nreset clk Synchronizer nreset clk Control Unit cnt_up modwait dr err op A B C V 2 nreset clk op A B C V cnt_up Datapath (Provided) counter outreg count_out division code count_out modwait err avg_out General Diagram of Datapath out data data clk nreset A B C data RegFile V Figure 1 Hardare Overview 3

4 Block Description Control Unit (controller.vhd) The control unit is the brain of your system. It has to regulate and control the operation sequence and input signals to the other components in the system so your system could operate as specified. The state transitions of the control unit can be described by the following pseudocode: idle: if (dr=0) goto idle ; Loop until dr asserted. sort1: err = 0 ; Reset error reg[] = reg[3] ; Reorder registers sort2: reg[3] = reg[2] sort3: reg[2] = reg[1] store: reg[1] = data ; Store data in register add1: reg[0] = reg[1] + reg[2] if (V=1) goto eidle ; stop adding on overflow add2: reg[0] = reg[0] + reg[3] if (V=1) goto eidle add3: reg[0] = reg[0] + reg[] if (V=1) goto eidle goto idle eidle: err = 1 ; Set error if (dr=0) goto eidle if (dr=1) goto sort1 A more in-depth description of the unit s operation is as follows: After receiving the dr signal, the data is reorganized and the oldest data thrown out in preparation of the newest data point. The new data should be stored in the register file, the data counter should be incremented, and any error signals should be de-asserted. The modwait signal should also be raised. Then the system will add the last four sampled data together (of course since you have only 1 adder, you have to do this in multiple cycles, therefore requiring you to use the register file as accumulator). If at any point during the summation an overflow occurs, stop adding, assert the error signal, err, and continue on to the next step. (Cutting the addition short like this provides a small power savings.) Once everything is done, modwait signal should be de-asserted to notify the external device that your system is done processing the data. Keep in mind that you need to store the final addition result in the register file and need to display it to the output when the modwait signal is deasserted. You may assume that the external device will know that unless the modwait signal is low, the data in the output line might be invalid. This is why having a stable (i.e. no glitches) modwait signal is crucial. Hint: The easiest way to ensure that modwait is stable is to use a flip-flop. Entity controller is port( clk: in std_logic;

5 ); nreset: in std_logic; dr :in std_logic; V:in std_logic; cnt_up: out std_logic; modwait: out std_logic; op:out std_logic_vector (1 downto 0); A:out std_logic_vector (3 downto 0); B:out std_logic_vector (3 downto 0); C: out std_logic_vector (3 downto 0); err: out std_logic end controller; SIGNAL DIRECTION DESCRIPTION clk Input This is the SYSTEM CLOCK signal that is used by the design. This clock will control when the state of the design is updated. This should occur on the rising edge of the clock. This signal is periodic at 200MHz. nreset Input This is the RESET signal. When this signal is asserted (active-low), all the Flip-Flop outputs in the design are set immediately to logic-0. Thus, this is an asynchronous reset signal. dr Input This is the synchronized signal for the analog to digital converter to signify that the next converted data is ready. V Input Indicates that an overflow occurred in the Datapath. cnt_up Output This signal acts as an enable to the counter so that the count will increment. This signal should only act as a pulse (i.e. high for only 1 clock cycle and then back to low). modwait Output This signal is to tell the external device connected to your design that the system is still processing the new data and the external device should wait. This signal should be stable (i.e. no glitches or edges unless during transition). To achieve stability, think about the state machine style or logic devices that you could use. op <1:0> Output Op-code for the Datapath. See description of Datapath. A <3:0> Output Operand for Datapath. See description of Datapath. B <3:0> Output Operand for Datapath. See description of Datapath. C <3:0> Output Operand for Datapath. See description of Datapath. err Output Error flag. Asserted when an overflow from an addition is detected, and de-asserted when the next data sample is read in. 5

6 Counter Unit (counter.vhd) The counter unit simply counts how many samples have been processed. The counter should increment whenever the signal cnt_up is asserted. This signal is supplied to the counter by the controller. This signal is only a pulse (i.e. only high for 1 clock cycle and then back to low). Hint: If you use the following libraries (in addition to other libraries you have been using) : IEEE.STD_LOGIC_ARITH.ALL; IEEE.STD_LOGIC_UNSIGNED.ALL; Then to implement the counter you could do: signal mycount, nextcount : std_logic_vector (3 downto 0); nextcount <= mycount + 1; In this example both mycount and nextcount can range from 0 to 15. Here nextcount equals one plus mycount. Entity counter is port( clk: in std_logic; nreset: in std_logic; cnt_up:in std_logic; count_out: out std_logic_vector (15 downto 0) ); end counter; SIGNAL DIRECTION DESCRIPTION clk Input This is the SYSTEM CLOCK signal that is used by the design. This clock will control when the state of the design is updated. This should occur on the rising edge of the clock. This signal is periodic at 200MHz. nreset Input This is the RESET signal. When this signal is asserted (active-low), all the Flip-Flop outputs in the design are set immediately to logic-0. Thus, this is an asynchronous reset signal. cnt_up Input This signal acts as an enable to the counter so that the 6

7 count will increment. This signal should only act as a pulse (i.e. high for only 1 clock cycle and then back to low). count_out <15:0> Output This signal is the stored value of how many ADC samples have been processed. Synchronizer (sync.vhd) The top-level input, data_ready needs to be synchronized before it can be used. See the end of this handout for a discussion of how to accomplish this. Entity sync is port( ); clk: in std_logic; nreset: in std_logic; A:in std_logic; A_sync : out std_logic end sync; SIGNAL DIRECTION DESCRIPTION clk Input This is the SYSTEM CLOCK signal that is used by the design. This clock will control when the state of the design is updated. This should occur on the rising edge of the clock. This signal is periodic at 200MHz. nreset Input This is the RESET signal. When this signal is asserted (active-low), all the Flip-Flop outputs in the design are set immediately to logic-0. Thus, this is an asynchronous reset signal. A Input The unsynchronized input. A_sync Output The synchronized output. Datapath (provided in ECE337_IP Library) This block has been provided to you in a library (ECE337_IP). You can use objects from this library for both simulation and synthesis, but you do not have access to the source code. (RTL-level block diagrams have been provided for reference, however.) A datapath is a term for the computational logic in a microprocessor. This datapath 7

8 contains an ALU for arithmetic operations and a register file for storing data. There are registers available for you to use, though you will not need them all for this design. Register 0 is the output register, so any values assigned to this register will appear immediately on the output. You will use this block to implement the arithmetic functions of your averaging filter. entity Datapath is port( clk: in std_logic; nreset: in std_logic; op :in std_logic_vector(1 downto 0); A : in std_logic_vector (3 downto 0); B : in std_logic_vector(3 downto 0); C : in std_logic_vector(3 downto 0); data : in std_logic_vector(15 downto 0); out : out std_logic_vector(15 downto 0); V : out std_logic ); end Datapath; SIGNAL DIRECTION DESCRIPTION clk Input System clock. nreset Input Active low, asynchronous reset. op<1:0> Input The operation to perform: 00 NOP 01 COPY: Copy register A to register C 10 LOAD: Store data in register C. 11 ADD: register C = register A + register B A<3:0> Input Operand #1 (see description of op) B<3:0> Input Operand #2 (see description of op) C<3:0> Input Operand #3 (see description of op) data<15:0> Input Literal data to be loaded into a register (see op). outreg<15:0> Output Value currently stored in the output register (register 0). V Output Set if the current operation produces an overflow. (This signal is actually generated asynchronously and can be assumed to be valid whenever the input to op is ADD.) 8

9 RegFile C wsel reg0 outreg V B rsel2 rdata2 A ALU res A rsel1 rdata1 B data MUX wdata wen Datapath Ctrl op 2 op sel wen clk nreset alu_op 2 Figure 3 Block diagram of Datapath 9

10 ECE337 Lab Spring 2008 rsel1 wdata Reg00 Reg01 reg0 wsel wen Decoder EN00 EN01 EN02... EN Reg Mux 1 Mux rdata1 rdata2 Reg15 rsel2 nreset clk Figure Detail of Register File 10

11 Top Level (avg_four.vhd) This is the top level module which will connect all the individual components. The division by four will be performed in the top level. An external source puts an unsigned-bit word on the data input, and asserts data_ready to indicate to the design that the data is valid. (Note that data and data_ready are asynchronous signals.) At this point the design will store the contents of data in a register file. Then it will add the last four samples together and store the result in the accumulator. The samples will need to be moved to make way for the next cycle, discarding the last data point, e.g., sample is discarded, sample3 becomes sample, and so on. While the processing occurs, the modwait signal is asserted to indicate that the system is not yet ready to process a new sample. If an overflow occurs during the averaging process, err is asserted to indicate an error and remains asserted until the beginning of the next averaging operation. The data on avg_out is not valid during this time. Below is a timing diagram showing this operation. Figure 5 Example Waveform Structural VHDL model for the sliding window average. As mentioned before, after you have created the internal blocks, now you have to connect them together to make the top level design avg_four.vhd. There are three methods to do this. You can use any method you think is the most appropriate, as they are all documented below. The first option is to use HDLDP. Essentially, this method will be creating a schematic like you did in Lab 2. The second method is to create it by hand using port-mapping in VHDL. In case you have not realized, HDLDP will create a VHDL file with port-maps when you generate the code from your schematic. This is why our 3 rd option is a combination of both. You could create your initial top level code using HDLDP and then modify the generated code manually if you need to change the top level design. 1. Using HDLDP to create a top level block First, you have to invoke HDLDP and get to the block diagram drawing space for your new block diagram. You should be familiar with these procedures from Lab 2. The next 11

12 step is for you to set up HDLDP to use the datapath IP and import your newly created control unit and counter to HDLDP. To set up HDLDP to use an IP library: 1. At the design browser menu bar: File New Library 2. A dialog box will pop up. Pick Downstream Only and click next. 3. Set the library name to ECE337_IP and under DOWNSTREAM Data Directories, select ModelSim Compiler. Just below that, enter /home/ecegrid/a/ece337/ece337_ip/vsim and click Add.. Click OK. To import your VHDL designs into HDL Designer: 1. At the design browser menu bar: HDL HDL Import 2. A dialog box will pop up. Pick Specify HDL files. Make sure VHDL is the default for unrecognized extension. Click next. 3. In the next step, Directory should point to your Lab source directory. Add all the files you want to be imported from your source directory. For the purpose of creating avg_four.vhd, you will need to import all of the previous design units, except, obviously the datapath source, which you do not have access to. Click next.. Make sure My_Lib is the default target library. Click next. 5. In the next step, verify that everything is correct and make sure the Convert imported files to Graphics option is checked, then click finish. 6. A pop up then will ask you for Convert to Graphics options. Choose appropriate properties on how you want your design to be viewed. For our purpose, choose Graphical view to be block diagram. Click finish. Now, in your library browser you should be able to see the three newly imported designs. To create the structural code, open a blank block diagram drawing space (see lab 2) and in your drawing space, add the newly imported components. To do this, in your drawing space select: Add Component or F3 You should see a new dialog box as in figure 6. Make sure the library you want to add the components from is My_Lib because that is where you import your components into. Add the control unit, the counter, and the synchronizer to your drawing board. Now you need to add the datapath module. In your drawing space select: Add IP 12

13 In the dialog that comes up, set the language to VHDL and set the entity source file to /home/ecegrid/a/ece337/class0.5u/ece337_ip/ece337_ip.vhd. Set the entity name to datapath. You can leave the architecture file and name blank, as the VHDL file specified as the entity source contains only an entity declaration. Set the Downstream Library to ECE337_IP. Select OK and place the datapath unit on the drawing board. (If it asks you about adding package dependencies, select yes to automatically include the correct VHDL library.) Figure 6: Add components to the drawing board After you have added all components to your drawing board, connect them and add the input/output pins per the design specification. You will need to add an embedded component for the division code. You should be familiar with these procedures from Lab 2. One thing you have to pay attention to is that when you save the diagram you have the correct design unit name. To do this in the Block Diagram Editor, click: File Save Library: My_Lib Design Unit: avg_four View: struct.bd Once you have done drawing the block diagram, you will have something similar to figure 7. Now you want to generate some VHDL code to describe the circuit. To do this, in the Block Diagram Editor select: a Tasks Generate Run through Components This command will generate a VHDL file of the schematic, which will be stored in the ~/ece337/my_lib/hdl directory. Refer to Lab 2 for more information. 13

14 Figure 7: Completed block diagram After you generated the VHDL code for your top level avg_four, you have to move the design to your source directory. In your ~/ece337 directory, you will see a directory called My_Lib. Go to ~/ece337/my_lib/hdl/ directory. Then you can see.vhd files and you will see your generated.vhd file from your schematic (probably named avg_four_struct.vhd). Copy that file to your source directory and rename it with the appropriate name. Try to compile it in vsim. Vsim might give you errors saying no component found or no lib found etc, go back to the moved code and comment out the portion that declares these components and links them to My_Lib. If you are still having problems, inform the course staff. You should have avg_four.vhd in your directory now, so start testing and debugging your design. 2. Using port maps to create a top level block Creating a top level block using port maps is just like writing VHDL code. (It is, in fact.) You will need to declare the entity for the top level block. In this case, your entity declaration should look like this: entity avg_four is port( clk : in std_logic; data : in std_logic_vector (15 DOWNTO 0); data_ready : in std_logic; nreset : in std_logic; count_out : out std_logic_vector (15 DOWNTO 0); modwait : out std_logic; avg_out : out std_logic_vector (15 DOWNTO 0) 1

15 ); end avg_four ; Next, you need to declare all the components you want to port map. In order to access the provided components, you need to specify the library where they are located. Do this by including a library/use statement at the beginning of the file: library ECE337_IP; use ECE337_IP.all; Remember, you should declare the components inside the architecture body of the code and it should look like this: architecture structural of avg_four is... component controller is port( clk : in std_logic; nreset : in std_logic; dr : in std_logic; V : in std_logic; cnt_up : out std_logic; modwait : out std_logic; op : out std_logic_vector (1 downto 0); A : out std_logic_vector (3 downto 0); B : out std_logic_vector (3 downto 0); C : out std_logic_vector (3 downto 0); Err : out std_logic); end component;... Now after you declare the components you want to port map, you must declare any intermediate signals you want to use. An intermediate signal is any signal that does not connect directly to a top-level input or output. Most of the inputs of the datapath, for example, are intermediate signals. Declare these signals and give them appropriate names. After you declare the intermediate signals you will need, you can start connecting the components. The syntax of a port map is: Block_name: component_entity_name port map ( componentio => destination/sourceio{, componentio => destination/sourceio} ); ENTITY avg_four IS PORT( clk : IN std_logic; data : IN std_logic_vector (15 DOWNTO 0); data_ready : IN std_logic; nreset : IN std_logic; 15

16 count_out : OUT std_logic_vector (15 DOWNTO 0); modwait : OUT std_logic; avg_out : OUT STD_LOGIC_VECTOR (15 DOWNTO 0) ); END avg_four ; SIGNAL DIRECTION DESCRIPTION clk Input This is the SYSTEM CLOCK signal that is used by the design. This clock will control when the state of the design is updated. This should occur on the rising edge of the clock. This signal is periodic at 200MHz. nreset Input This is the RESET signal. When this signal is asserted (active-low), all the Flip-Flop outputs in the design are set immediately to logic-0. Thus, this is an asynchronous reset signal. data <15:0> Input This is the converted analog to digital data. This data only valid when the data ready signal is high. This data is assumed to be valid for a short amount of time after data_ready is asserted. data_ready Input This is the signal for the analog to digital converter to signify that the next converted data is ready. This signal has to be synchronized count_out <15:0> Output This signal is the stored value of how many ADC samples have been processed. modwait Output This signal is to tell the external device connected to your design that the system is still processing the new data and the external device should wait. This signal should be stable (i.e. no glitches or edges unless during transition). To achieve stability, think about the state machine style or logic devices that you could use. avg_out <15:0> Output This is the output of the average of the last for samples err Output Error flag. Asserted when an overflow from an addition is detected, and de-asserted when the next data sample is read in.

17 Simulating the design When simulating the design, you may notice that you can see the hierarchy of the datapath in you ModelSim design window even though you do not have access to the source. Can you identify the sub-blocks within the datapath? Can you identify any internal signals? For this lab you have been provided with a gold model of the top-level design, called GOLD_avg_four. If your design matches the gold model, then you know it is working correctly. You should be familiar with the process of including a gold model from Lab 3. Post-lab questions: Answer these questions in a text file called Lab3.txt in your source directory and turn them in along with the rest of your lab using the autoturnin command. Question: What is the minimum amount of time that data_ready must remain asserted to ensure correct operation? What is the minimum amount of time, in clock cycles, that data must remain valid after data_ready is asserted in order to ensure correct operation? (You may assume that all setup and hold times, as well as any propagation delays, are negligible.) Question: Assume that the datapath was extended to support a multiplication instruction defined by C = A * B. Write the pseudocode for a state machine that would calculate the dot product of the last four samples. (Remember the dot product is (sample1*sample3) + (sample2*sample). Also assume that the division code has been removed from the top level. Grading Procedure Important: Your file name and entity name must be the same as specified in this handout or you will fail the automated grading script (i.e. your top level file name should be avg_four.vhd and the entity name should be avg_four. Your control unit must be named controller.vhd and the entity name should be controller, etc.). The grading of Lab will be different from the previous three labs. For this lab an automatic grading script will be used. The command for this is: autoturnin 17

18 The automatic grading script itself is a FIFO queue and will be running every 5 minutes or so. As you can imagine the queue will be large closer to the deadline, so it is suggested not to procrastinate on this lab. Your results will be ed to your mg account - you can check your mg account mail with such programs as pine or mailx, to name a few. If an error ever happens, do not worry, there is a back up copy of your design, so just contact your TA. You can check the status of your submission using: askqueue This will tell your position in the queue and how long you will have to wait to get your results back. The automatic grading script will do two things. First it will test the SOURCE version of your design. Second it will test the MAPPED version of your design. For this lab, 30/5 of your grade will be determined 100% from your MAPPED version grade (the last 15/5 comes from the prelab and teamwork report). This is to reinforce the importance of getting your mapped version working. The source version score is included just as a reference. In order to have completed this lab, you have to score 90% (27/30) or better on your mapped version test. COMMENTS: You will need to use the g option with scriptgen to create the synthesis script for avg_four. This will give you a warning that it can t find datapath.vhd. This is expected and is not a problem. Your design is required to run at at least 200 MHz or it will fail the autoturnin script. You may need to optimize the circuit as in Lab 3. (You can use the s option with scriptgen to help you set constraints.) The code for the grading testbench used by the grading script will not be disclosed to the student nor will the test cases be told to the student. The majority of the points come from successfully passing the synthesized design portion of the grading testbench, therefore it is highly recommended to make sure you have an error-free run through Synopsys. You will be allowed a maximum of 10 passes through the Lab grading testbench (i.e. 10 autoturnin submissions) note: this number will decrease in future labs. Only the last submission will count! So use RCS! If a previous submission is better than your most recent submission, restore it from RCS and submit again. RCS is your friend. For the blocks of code required for this lab you must name the source files with the name provided. Failure to do so will cause you to fail the grading script. 18

19 For the blocks of code required for this lab you must use the entity names provided along with the signal names. Failure to do so will cause you to fail the grading script. Make sure that your avg_four.scr file is located in your scripts directory. Failure to do so will cause you to fail a large majority of the grading script. 19

20 Appendix: Synchronizing Asynchronous Signals Whenever a design has input signals which are asynchronous to the system clock, these input signals need to be synchronized. Assuming the inputs are read on the rising edge of the system clock, synchronization will prevent reading a transition in the input signal. In order to synchronize a signal, the input must go through TWO flip-flops clocked on the system clock. Figure 8 shows how a synchronizer circuit would look for passing data between two different clock domains (same concept, the data in one clock domain is asynchronous to the other clock domain). Figure 8: Synchronizer Circuit for two clock domains In general the synchronizer circuit has two purposes: (1) to synchronize the input signal to the system clock domain and (2) to reduce the metastability of the signal. Metastability (the unknown value of a signal) is an issue when synchronizing an asynchronous signal into a flip-flop device. If the incoming asynchronous signal happens to change its state (logic value) at the same time the flip-flop device is capturing the data, an indeterminate value on the output of the flip-flop may be seen. Now we ask, How does this affect the functionality of the circuit? It can adversely affect the circuit if the captured data is fanned out to multiple places within the circuit. The indeterminate value of the captured signal can be interpreted differently (either a logic 1 or 0 ) by different logic gates within the receiving circuit. Thus leading to a possible malfunction of the circuit. To try to reduce the possibly of this occurring, a second flip-flop is attached in series to the data capturing flip-flop. It will be the output of this second flip-flop that is used inside the receiving circuit (see Figure 8). Please note that adding the second flipflop does not guarantee the output of the second flip flop to be stable but the chances of the output being metastable are greatly reduced (note: In some modern designs, three flipflops in series are used to synchronize asynchronous signals to a clock domain). 20

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