TAU 2013 Variation Aware Timing Analysis Contest

Transcription

1 TAU 2013 Vrition Awre Timing Anlysis Contest Debjit Sinh 1, Luís Guerr e Silv 2, Ji Wng 3, Shesh Rghunthn 4, Dileep Netrbile 5, nd Ahmed Shebit 6 1;5 IBM Systems nd Technology Group, 1 Hopewell Junction/ 5 Essex Junction, USA 2 INESC-ID / IST - TU Lisbon, Portugl 3 Illinois Institute of Technology, Chicgo, USA 4 IBM Systems nd Technology Group, Bnglore, Indi 6 Synopsys, Sunnyvle, USA TAU/ISPD joint session, Stteline, NV Mrch 26, 2013 TAU Sponsors: 1

2 Vrition wre timing Timing nlysis key component of chip design closure flow Pre/post route optimiztion, timing sign-off Incresing significnce of vribility Performnce BC WC Too smll performnce improvement Mrgin for vribility Gurnteed performnce Technology genertion Vribility wre timing nlysis essentil Growing chip sizes, complexity: Impcts timing nlysis run-time Trde-offs between modeling ccurcy/complexity nd run-time 2

3 TAU 2013 vrition wre timing nlysis contest Gol: Seek novel ides for fst, vrition wre timing nlysis by mens of the following Increse wreness of vrition wre timing nlysis, provide insight into some chllenging spects Encourge novel prlleliztion techniques (including multi-threding) Fcilitte cretion of publicly vilble vrition wre timing nlysis frmework nd benchmrks for reserch/future contests Trde-offs for timing model complexity Wnted focus on vrition wre timing, understnding chllenges for vrition wre timing, tool performnce Feedbck from prior contest committee: Tems spend too much time on infrstructure (e.g., prsers, fixing librry/benchmrk file bugs) Chose to expnd on single corner timing nlysis contest from

4 Timing nlysis contest rchitecture Pre-processing Provided to contestnts Contest objective Multiple benchmrks Benchmrk file(s) (internl formt ++ ) Design Multiple.lib (different PVT * conditions) Plce nd Route (Cdence tool) Design Assertions Prsitics Librry file (internl formt ++ ) Vrition wre timing nlysis tool development Timing report Output file (internl formt ++ ).lib Mnully sserted prmeter sensitivity (rndom, metl) Prmeterized gte librry Dely, Slew, Test mrgin (gurd time) Monte Crlo bsed vrition wre timer Finl Evlution Golden timing report * PVT Process, Voltge, Temperture ++ Formt identicl/extension to/of PATMOS 11 contest 4

5 Sources of vribility (Prmeters) Six globl (inter-chip) sources of vribility Environmentl: Voltge (V), Temperture (T) Front end of line process: Chnnel length (L), Device width (W), Voltge threshold (H) Bck end of line process: Metl (M) All metl lyers ssumed perfectly correlted Rndom vribility (R) Intr-chip (cross chip) systemtic vribility ignored M Hne et l., SISPAD

6 Vribility modeling Prmetric liner model * µ + v V + t T + L + W H Ech prmeter ( V, T,, R) ssumed s unit norml Gussin Ech sensitivity ( v, t,, r ) denotes first-order per-sigm sensitivity Prmeter my vry between [-3, 3] sigms l w + h + m M + r R Encourged novel vribility wre timing nlysis techniques Sttisticl timing [Fewer runs, pessimism relief for rndom vribility, modeling inccurcies/simplifictions] Multi-corner timing [Less complexity, fster nlysis nd potentilly more ccurte t ech corner, lrge number of corners, pessimistic for rndom vribility] Monte Crlo bsed timing [Less complexity, most ccurte, very long run-times] Golden timer s pproch: Used for ccurcy evlutions only Hybrid/novel pproch for vribility wre timing [?] * non-liner with prmetric slews 6

7 Interconnect (wire) modeling Interconnects modeled s resistnce cpcitnce (RC) network Single source (port), one or more sinks (tps) No coupling cpcitnces, no grounded resistnces Single corner timing model Elmore dely model First moment vlue of impulse response Single corner dely from port to tp 5: Multi step output slew computtion Combintion of input (port) slew, dely, nd second moment vlue of impulse response Introduces non-linerity [Kshyp et l., TCAD 04] s o 2 i = s + (2β o d 2 o ) Output slew Input slew Elmore dely Second moment vlue of impulse response 7

8 Interconnect (wire) modeling considering vribility Wire prsitics (RC vlues) function of metl prmeter ( M) Provided sigm (corner) specific scle fctors for prsitics Tp cpcitnce contribution from gte input pin unffected Prmetric input slew Prmetric wire dely nd output-slew First order sensitivity to metl nd other prmeters my be computed vi model-fitting (e.g. finite-differencing) for sttisticl timer Complex prmetric output slew computtion Corner dely t nominl metl corner (0 sigm): First order metl sensitivity: Corner dely t thick metl corner (σ sigm): Tp gte pin cp Prmetric wire dely: Corner specific scle fctors 8

9 Combintionl gte (cell) modeling Extended liner gte dely/slew model from PATMOS 11 contest to vrition wre model Sensitivities (to prmeters, input slew, lod) provided in gte librry Lumped lod model (no effective Cpcitnce/current source models) Note: Input slew (S i ) nd lod (C L ) re prmetric models 9

10 Sequentil gte (flip-flop) modeling Test (Setup/hold) mrgin or gurd-times liner function of slews t clock nd dt points Sensitivities (to input slews) provided in gte librry Prmetric slews Prmetric gurd-time 10

11 Prmetric timing nlysis Trditionl timing nlysis/propgtion Forwrd propgtion of signl rrivl times (t), nd slews Bckwrd propgtion of signl required rrivl times (rt) Slck computtion Nunces Worst slew propgtion (when 2+ signls meet t point) Seprte propgtion for erly, lte modes, nd rise, fll trnsitions Needs mximum, minimum opertions on prmetric quntities Could be expensive for sttisticl timing, inccurcy concerns Single clock domin No coupling, common pth pessimism reduction, loops 11

12 Projection techniques nd tool output Projection of prmetric vlues: 3 modes required for contest µ + v V + t T + l L + w W + h H + m M + r R MEAN: Nominl vlue (µ) SIGMA_ONLY: Stndrd devition ( ) WORST_CASE: Worst 3 sigm projection of metl prmeter, rndom prmeter, nd ll other prmeters combined together (vi root sum squre) Required tool output Must report projected vlues (bsed on shell vrible $TAU_PROJECTION) Set of lines specifying for ech primry output in design Arrivl times nd slews (for erly/lte/rise/fll combintions) Set of lines specifying for subset of pins in design Slcks 12

13 Contest timeline Dte Oct 12, 2012 Feb 8, 2013 Feb 20, 2013 Feb 28, 2013 (~4+ months) Mr 27, 2013 Activity Contest nnounced, webpge online ( Detiled 22 pge.pdf contest rules document provided Benchmrk suite ver1.0 provided (24 testcses) Vrition wre gte librry provided Interconnect network prser nd viewer utility provided (debug id) Informed tht source code of winning tool from PATMOS 11 contest (thnks to Prof. Chng s tem from NTU, Tiwn) vilble upon request to void infrstructure development (optionlly re-use prsers, etc.) Detiled clcultions for toy benchmrk provided Monte Crlo results for benchmrks ver1.0 provided New vrition wre gte librry provided Updted contest rules document Contestnts requested to provide erly binries of tool for comptibility testing 5 new lrge benchmrks provided (lrgest benchmrk ~88K gtes) Finl tool binries due for evlution Results nnounced 13

14 Tems 8 tems Chin (1) Greece (1) Indi (2) Singpore (1) Tiwn (2) USA (1) Registered tem Contest committee member 14

15 Interesting tool chrcteristics Sttisticl, Monte Crlo bsed No multi-corner timers Sttisticl mximum/minimum (mx/min) opertion nunces Used Clrk s [Opertions Reserch 61] moment clcultion pproch, nd Visweswrih et l. pproch [DAC 04] Smrt Compre mens nd do sttisticl mx/min in select cses Consider neglected correltion between signl inputs Better ccurcy of output distribution. Bsed on Nderjh et l. [IEEE TVLSI 08] Prlleliztion Two tems employed pthreds Multi-threded netlist prsing Multi-threded wire pre-processing Circuit leveliztion Multi-threded forwrd propgtion Multi-threded bckwrd propgtion 15

16 Benchmrks Benchmrks ver of 36 benchmrks used for finl evlutions ( > 250 gtes) Lrgest test-cse ~88.4K gtes Benchmrks ver lrge benchmrks not relesed to contestnts erlier All benchmrks now vilble on webpge 16

17 Evlution metrics Score model for ech benchmrk: A * { /T + 0.2/M } Accurcy score (A): Eqully weighted sum of verge-rrivl time ccurcy, verge-slew ccurcy, verge-slck ccurcy, worst ccurcy, ccurcy of worst design slck Bsed on WORST-CASE projected mode results only Scoring different for pessimistic versus optimistic result Score for pessimistic nswer Score for optimistic nswer 80 Score Score for pessimistic nswer Score for optimistic nswer % ccurcy (reltive to cycle time) 17

18 Evlution metrics (contd.) Score model for ech benchmrk: A * { /T + 0.2/M } Run-time score (T): Tool run-time (seconds) per 1K gtes Averge run-time for single threded sttisticl timer found ~ 1sec/1K gte benchmrk Memory score (M): Tool pek memory (in 100Mbs) per 1K gtes Averge memory for single threded sttisticl timer found ~ 100Mb/1K gte benchmrk Finl evlution nunces Evlution on 2.33Ghz Qud core mchine, 24Gb Rm, up to 8 threds Accurcy prmount Monte Crlo bsed timer to generte golden Bised towrds tools with better run-time/memory for similr ccurcy Finl score is sum of ll (20) benchmrk scores 18

19 Tool comprison for top 3 tems Tem Id Tem T13_11 IIT Mdrs, Indi Tem T13_13 Ntionl Tsing Hu University, Tiwn Tem T13_14 Ntionl Chio Tung University, Tiwn Timer Sttisticl multi threded Sttisticl single threded Sttisticl single threded Num. benchmrks tht crsh tool Missing pin slcks Few None Few ~Averge ccurcy ~Averge run-time [~ 1sec/1K gtes] 17.0 (vried between ) ~Averge memory [~ 100Mb/1K gtes] 0.3 Accurcy scores indicted within 3% ccurcy of sttisticl timing (for given benchmrks, librry) for rrivl times nd slews Slck ccurcy nd worst timing ccurcy using sttisticl timer usully within 10% of Monte Crlo results 19

20 Summry Vrition wre timing nlysis contest Increse wreness of vrition wre timing nlysis, provide insight into some chllenging spects Prmetric timing propgtion Model fitting/finite-difference concept, inccurcies Prmetric mximum/minimum opertions Projection techniques Pessimism relief Encourge novel prlleliztion techniques Multi-threded timers Fcilitte cretion of publicly vilble vrition wre timing nlysis frmework nd benchmrks for reserch/future contests Frmework for potentil concepts on prmetric pth trcing Vribility wre timing mcro-modeling, coupling, etc. Reference: Sinh et l., TAU 2013 Vrition wre timing nlysis contest, pp , ISPD 2013, Stteline, NV 20

21 Finl results Plques nd csh wrds for the top three tems Tem Id Tem T13_11 IIT Mdrs, Indi Tem T13_13 Ntionl Tsing Hu University, Tiwn Tem T13_14 Ntionl Chio Tung University, Tiwn Timer Sttisticl multi threded Sttisticl single threded Sttisticl single threded Num. benchmrks tht crsh tool Missing pin slcks Few None Few ~Averge ccurcy ~Averge run-time [~ 1sec/1K gtes] 17.0 (vried between ) ~Averge memory [~ 100Mb/1K gtes] 0.3 Finl score verged over ll benchmrks POSITION

22 TAU 2013 Vrition Awre Timing Contest Third Plce Awrd Presented to Yu-Ming Yng, Yu-Wei Chng, Shih-Heng Hung nd Iris Hui-Ru Jing Ntionl Chio Tung University, Tiwn For itimer Jinjun Xiong Chiryu Amin Debjit Sinh Generl Chir Technicl Chir Contest Chir 22

23 TAU 2013 Vrition Awre Timing Contest Second Plce Awrd Presented to Po-Yi Hsu, Sheng-Ki Wu, Yung-Shun Lin nd Wi-Kei Mk Ntionl Tsing Hu University, Tiwn For HWL Timer Jinjun Xiong Chiryu Amin Debjit Sinh Generl Chir Technicl Chir Contest Chir 23

24 TAU 2013 Vrition Awre Timing Contest First Plce Awrd Presented to Jobin Jcob Kvlm, Sudhrshn V, Nitin Chndrchoodn nd Shnkr Blchndrn IIT Mdrs, Indi For IITimer Jinjun Xiong Chiryu Amin Debjit Sinh Generl Chir Technicl Chir Contest Chir 24

25 Bckup: Detiled scores Finl results: Accurcy score: 25