CacheCompress A Novel Approach for Test Data Compression with cache for IP cores

Size: px

Start display at page:

Download "CacheCompress A Novel Approach for Test Data Compression with cache for IP cores"

Nora Fletcher
6 years ago
Views:

1 CacheCompress A Novel Approach for Test Data Compression with cache for IP cores Hao Fang ( 方昊 ) fanghao@mprc.pku.edu.cn Rizhao, ICDFN 07 20/08/2007 To be appeared in ICCAD 07

2 Sections Introduction Our proposed methods Experimentation Conclusion

3 Test Challenges Large test data size CUT (Circuit-Under-Test) Present circuit 100~1000M bits Next decade 10G~100G bits ATE (Automatic Test Equipment) Limited memory Cannot store all the data in ATE Long test time Directly proportional to $$ 1~2 $ for 1 minute Relative small number of pins stimulus ATE CUT response

4 Test Data Compression Automatic Test Equipment (ATE) Output channel Clock generator Input channel memory Pre-computed stimulus Pre-computed Test data Compacted response chip On-chip decoder Original stimulus Circuit-under-test (CUT) Original response Research Hot spot On-chip compactor Well researched Stimulus ( hot research spot ) Software compress Hardware decompress (on-chip decoder) Response Hardware on-chip compactor (well researched)

5 Test Data Compression Architecture Based on Scan slices circuit-under-test Codewords (from ATE) Codewords for Slice i Codeword for Slice i On-chip decoder chain1 chain2 chainc On-chip compactor slicei-1 slicei-2 slicei-3 slicek slicek-1 Narrow input (codeword) Data after compressed Broad output (slice) Original test data to be compressed

6 Hardware On-chip Decoder Features Vs. conventional software compression (gzip, rar) Small Area Overhead Cannot use too complex methods Cannot save all the former data Codeword Continuous-flow Input data (codeword) Receives one codeword every cycle Difficult to stop ATE clock Usually every slice needs at least one codeword Original stimulus content slice Few 0 or 1 Many don t-cares bits (X) Information Lossless (narrow input) Some image algorithms with very high compression ratio Pre-computed stimulus On-chip decoder Slice (broad output) Original stimulus

7 Compression methods LFSR based linear expansion Dictionary based on-chip memory Selective Encoding encode specified bits Others Hybrid...

Dictionary Methods Basic method Contain all the slices in the static memory Load test data in the on-chip memory at the beginning ROM Shorter memory address instead of larger slice Need

8 Dictionary Methods Basic method Contain all the slices in the static memory Load test data in the on-chip memory at the beginning ROM Shorter memory address instead of larger slice Need a very large memory Advanced method Dictionary with Correction (ITC 04) Need a smaller memory, but still very large Correction index Memory address RAM correction Chain 1 Chain 2 Chain n

9 Selective Encoding (ITC 05) For every slice Count # of 0s & # of 1s in the slice Determine default bit & value (majority) slice # 0 # 1 type specified bit & value (minority) Fill Xs with the default value Only encode the specified bits 0000xxxx 00xx001x N-type S-type Classified by # of specified bits 0: N-type (Non-specified) M-type 1: S-type (Single-specified) >1: M-type (Multiple-specified)

10 Encode Slices with Two Code Types Group 0 Group 1 Group 2 Group 3 control-code Data-code Single-mode code Slice: C=15, G=4 Codeword W=6 Only one codeword for N-type, S-type Composition The default value Index of the specified bit (index=n means no specified bit) Group-mode code M-type First codeword: group index Subsequent codewords: group content

11 Selective Encoding Decoder Structure decoder codeword w control Controller control Single Sub-decoder Group Sub-decoder Default value G index Select Group Content index G G Scan Slice Selector C Scan slice shift

Selective Coding -- Example Slice xx00 01xx

index=5, set bit 5 to 1 Start new slice,

slice, default=0, index=7, set bit 7 to 1

Decompressed Slice 0000 0100 1111 1111 0000

12 Selective Coding -- Example Slice xx00 01xx xxxx 1xx Control code Data code Interpretation Start new slice, default=0, index=5, set bit 5 to 1 Start new slice, default=1, index=8 (no bit set) Start new slice, default=0, index=7, set bit 7 to 1 Enter group-mode, Group index=0 Decompressed Slice Group data is Group pointer Overwrite

13 Sections Introduction Our proposed methods Experimentation Conclusion

14 Disadvantages of Dictionary Code Store entire slice Memory width Store slices as many as possible Great many words Memory height Contents are constant (static) Need additional initialization step Store large initialization data on ATE

15 Improvement in CacheCompress Store only part of slice Memory width A default compress method Single-mode code of selective encoding Many simple slices can be compressed Use memory to compress remain slices Memory height Cache-like Updating during testing Dynamic, MRU (Most frequently used) Memory height Eliminates memory initialization

16 Disadvantages of Selective Encoding Many specified bits in one slice Eg: Codeword: x Cause many group codes No specified bits in the slice (N-type) Eg: Codeword: The whole codeword for one slice In fact only a bit is enough, waste bandwidth

17 Improving Selective Coding Key idea Use the wasted bandwidth to write the dictionary in advance for future reading Many specified bits in the slice Much wider segment instead of group Read segment from dictionary Only one codeword for several groups No specified bits in the slice (N-type) One bit is for default value Wasted bits for writing dictionary

18 Compression Parameters & Slice Division Given parameters C: # of bits per slice W: word width Segment (read and write word) [C/W] groups Segment 0 Segment 1

19 Cachecompress Decoder Structure decoder Default value control Single Sub-Decoder index G Scan slice codeword W Controller D Select Read Sub-decoder control we S*G address dictionary Segment content S*G G index Scan Slice Selector C S*G Default value control Write Sub-decoder shift

An Example (C=15, W=8) Original scan slice

00xxx0xx xxxxxxxx 110 0010 000000000000000

xxxxxxxx 011 0101 111110111111111 Single

Mem[2]=01010011 01010011 1111111 011 1111

specified index 100 0010 010101011111111

20 An Example (C=15, W=8) Original scan slice Code Decompressed slice Shift Type Details 00xxx0xx xxxxxxxx Write default=0, writeaddress=2 xxxxxx00 0xxxxxxx Write default=0, write content= xxx011 xxxxxxxx Single default=1, specified bit index= xxx xxxxxxxx Write default=1, write content=0011 Do write: Mem[2]= Single default=1, no specified index Read segindex=0, readaddress=2, content= Write: Mem[2]=

21 Encoding Algorithm S-type One single-mode codeword N-type One single-mode codeword Record for possible future writes M-type One single-mode codeword for default value Encoding specified segment (specified bits > 1) Search suitable words in the dictionary If not found Use LRU replacement policy to overwrite one entry Convert single-mode for N-type to write-mode An read-after-write race should be avoided Encode as read-mode codeword For other uncovered bits Encode as single-mode codeword for correction

22 Sections Introduction Our proposed methods Experimentation Conclusion

23 Hardware Implementation Gate Count or Reg Count C=255 W=64 C=1023 W=64 C=1023 W=128 reuse memory gates regs not reuse memory gates regs Hardware Implement Verilog HDL (Parameterized C, W) Pass Simulation by VCS Hardware overhead Design compiler under TSMC13 process About 3-4 gates per scan chain (memory reuse) 1% area overhead

Benchmark Circuits Circuits Cells Scan cells Vectors TD X ratio CCT1 94757 11675 634 7,401,950 96.11 CCT2 183743 20652 2396 49,482,192 96.45 CCT3 248518 29057 2355 68,429,235 98.

24 Benchmark Circuits Circuits Cells Scan cells Vectors TD X ratio CCT ,401, CCT ,482, CCT ,429, CCT ,191, CCT ,414, CCT ,428, Industrial SoCs from MPRC All silicon proved Test patterns Generated by Synopsys Tetramax After dynamic compaction

25 Compression Result Circuits C SE [ITC 05] TE Cycle DC [ITC 04] TE Cycle Size W CacheCompress TE Cycle Size Hit rate (%) CCT ,053, , ,776 29, , ,393 71, CCT ,035, ,342 3,963,168 52,712 2,856, ,345, , CCT ,024, ,733 3,935,184 70,650 2,432, ,305, , CCT ,338, ,273 4,613,730 78,048 2,950, ,917, , CCT ,123, ,648 5,074, ,372 2,418, ,165, , CCT ,096,432 1,014,421 14,786, ,180 4,947, ,931, , Test data size: 30% reduced in all cases Testing time: 27% faster than SE Memory size: times smaller than DC Average hit rate: 84%

26 Ratio Improvement Analysis Codeword for N-type -> Write-mode Sufficiently use codeword bandwidth Words reuse 84% hit rate means every word will be read 7 times in average Only provide data the first time Subsequent 7 complex segments are benefited by reading

27 Sections Introduction Our proposed methods Experimentation Conclusion

28 Conclusion Contribution Combine other technique with dictionary coding Dynamic, cache-like Eliminates memory initialization Result Much smaller dictionary Higher compression ratio

A Combined Compatible Block Coding and Run Length Coding Techniques for Test Data Compression

World Applied Sciences Journal 32 (11): 2229-2233, 2014 ISSN 1818-4952 IDOSI Publications, 2014 DOI: 10.5829/idosi.wasj.2014.32.11.1325 A Combined Compatible Block Coding and Run Length Coding Techniques