1 Watt, MHz, SMT Tunable Band Pass Filter (MINI-ERF ) 1.75 x 2.40 x 0.387

Transcription

1 MN-3-52-X-S4 1 Watt, 3 52 MHz, SMT Tunable Band Pass Filter (MINI-ERF ) 1.75 x 2.4 x.387 Typical Applications Military Radios Military Radar SATCOM Test and Measurement Equipment Industrial and Medical Equipment Features 1 Watt CW continuous power handling +4 dbm IIP3 (typ.) Low IL (5.5 db typ., 4% filter) 22 db +/-1%, (4.7% filter) Fast Tune Time (15 µs, typ.) Functional Diagram RF MHz RF MHz MHz Digital Control VCC +3.3VDC N/C N/C A7 (SPIMOSI) A6 A5 (SPICLK) A4 (SPI CS) A3 A2 A1 A TUNE_READY SER/PAR /TUNE_STB CUSTOMER MODE VBB +1VDC 2 19 General Description The MINI ERF is a low-cost, miniature, highperformance tunable band pass filter. The MINI ERF uses PIN diodes to deliver high filter performance while fitting in a 1.75 x 2.4 x.387 package. Serial or parallel tuning interfaces are selectable. All MINI-ERF filters are fully tuned and tested by POLE/ZERO for convenience and ease of use. Table 1. Filter Configurations Models available (all parameters T a= +25C, V CC = 3.3V, V BB = 1V, 5 Ω system) Part Number Frequency Range (MHz) MN S MN S %BW3dB (%) 4.7 typ. (5.4 max.) 7.2 typ. (8.2 max.) Insertion Loss (db) 5.2 typ. (7 max.) 3.5 typ. (5 max.) Selectivity +/- 1% (db) 22 typ. (19 min.) 16 typ. (14 min.) Tune Time (+1dBm) (µs) 1 15 typ. (21 max.) 15 typ. (21 max.) Max 3.3V Current (ma) 2 Max +1V Current (ma) For more information see section 9. Tune Time. 2 Max 3.3V current consumption occurs at the low end of each of the three internal bands (3MHz, 9.54MHz, and MHz). Max current does not include the dynamic current of the filter during tuning. 3 Max +1V current consumption occurs at the low end of each of the three internal bands (3MHz, 9.54MHz, and MHz). Product Data Sheet Rev of 13

2 1. PIN INFORMATION MN-3-52-X-S4 Figure 1. Pin configuration S4 package Table 2. Pin Function Descriptions Pin No. Label Description, Conditions 1 V CC Supply Voltage Input: V V CC 3.6 V. 2, 17, 19, 2, 21, 23, 24, Digital and Analog Ground. 26, 27, 28 3, 4 NC No Connect Factory use only pins. Shorting or connecting these pins may affect the performance and functionality of the filter. Leave these pins floating. 22, 25 RF IN/OUT RF Signal Input or Output. A7 Parallel Data A7 (MSB) In Parallel interface mode, data is latched on the rising edge of STB and indicates which frequency the filter should tune to (A7 = MSb, A = LSb). 5 Serial Tune Interface Master Output Slave Input Data is applied to MOSI for transferring a tune command to the device. Each bit of data is latched on the rising edge of SCLK. The MOSI filter accepts tune command lengths of 16-bits. 6 A6 Parallel Data A6. Product Data Sheet Rev of 13

3 MN-3-52-X-S4 Pin No. Label Description, Conditions A5 Parallel Data A5. 7 SCLK Serial Tune Interface Clock SCLK is used to clock in the tune word. Data is latched on the rising edge of SCLK. A4 Parallel Data A4. Serial Tune Interface Chip Select The master transmits logic for the desired filter using 8 the chip select line. When CS is taken low, the control circuitry wakes up and the filter is CS ready for a new tune command. When the entire tune word has been loaded into the filter CS is taken high to indicate the tune command is complete. For proper operation in Serial mode, tie this pin directly to STB (pin 15). 9 A3 Parallel Data A3. 1 A2 Parallel Data A2. 11 A1 Parallel Data A1. 12 A Parallel Data A (LSB). 13 TUNE READY Tune Ready Indicator This pin normally remains low. When CS and/or STB is taken low to initiate a tune in either SPI or Parallel tune modes, the TUNE READY pin transitions high to indicate the filter is ready to receive the SPI or Parallel data. After data has been shifted in via the tune interface, the TUNE READY pin will transition back low indicating that the tune process is finished. Serial/Parallel Command Interface Selection Leaving SER/PAR floating or pulled to V CC will enable the SPI (serial) tune command interface. Keeping SER/PAR pulled to will 14 SER/PAR enable the parallel tune command interface. Modes can be switched at any time but require a power cycle to take effect. In Serial interface mode STB wakes the controller circuitry on a low transition. For proper operation in SPI mode, tie this pin directly to CS (pin 8). In Parallel interface mode, when STB is taken low, the control circuitry wakes up and data 15 STB is ready to be sent on A7-A. When STB is transitioned high, the MSB of parallel data is latched. STB should be taken low again while the LSB is loaded on the data port. When STB is transitioned high for the second time, the LSB of parallel data is latched and the filter is commanded to the frequency specified by the parallel data interface. (This pin is internally pulled to VCC with a 27 kω resistor only when used in parallel mode.) 16 TUNE MODE Leave this pin floating or pull to V CC to enable legacy tune mode 4 Pulling this pin low is not supported at this time and is reserved for future use. The MINI-ERF will not operate correctly if this pin is pulled low. 18 V BB High Bias Supply Voltage Input: +1 VDC for optimum performance. 4 Contact Pole/Zero for more information on future/custom interface requirements. Product Data Sheet Rev of 13

4 2. ABSOLUTE MAXIMUM RATINGS MN-3-52-X-S4 Table 3. Absolute Maximum Ratings Voltages are referenced to (ground = V) Symbol Parameter Conditions Min. Max. Unit V CC Supply voltage V 5 V BB High bias supply voltage V V PIN Pin voltage with respect to and V CC V CC +.5 V I OH /I OL Digital interface pin sink/source current ma P IN In-band RF input power level Signal is in passband f = 3 52 MHz - 32 dbm P IN Out-of-band RF input power level dbm 5 T RATE Maximum tune rate (Frequency Hopping) khz T A Storage temperature C 3. SPECIFICATIONS Table 4. General Operating Ratings Voltages are referenced to (ground = V) Symbol Parameter Conditions Min. Typ. Max. Unit V CC Supply voltage V I CC V CC current consumption at 3.3 V ma V BB High bias supply voltage V V IH Digital high level input voltage V CC = V.7 * V cc - V cc +.5 V V IL Digital low level input voltage V CC = V * V cc V I OH /I OL Digital Interface pin source sink current ma P IN Maximum RF input power for linear operation Signal is in passband f = 3 52 MHz dbm F RANGE Tunable frequency range MHz Z O Input/output impedance Ω VSWR Voltage Standing Wave Ratio :1 2.2:1 - IL Insertion loss See Table BW Bandwidth See Table Selectivity at f C ± 1% See Table Tuning time μs 7 F DRIFT Center frequency drift over temperature -4 to +85 C ppm/ C T A Ambient temperature C 5 Refer to 1. Application Information. 6 For an input signal of dbm. Refer to section 9. Tune Time for more information. 7 Center Frequency, Fc, moves inversely with temperature. For example if Fc = 52 MHz at +25ºC, then at 85ºC, Fc will move slightly lower to around MHz. (Δ Fc = -.5 x 52 x 6 = -1.56MHz). Product Data Sheet Rev of 13

5 S21 (db) S11 (db) S21 (db) S11 (db) S21 (db) S11 (db) S21 (db) S11 (db) MN-3-52-X-S4 4. TYPICAL FILTER RESPONSE Frequency (MHz) Frequency (MHz) 4% 7% 4% 7% Figure 2. Filter response at 3 MHz Figure 3. Filter Response at 9 MHz Frequency (MHz) Frequency (MHz) 4% 7% 4% 7% Figure 4. Filter Response at 25 MHz Figure 5. Filter Response at 5 MHz Product Data Sheet Rev of 13

6 MN-3-52-X-S4 5. TUNE COMMAND FORMAT 5.1 Legacy Tune Mode Legacy tune mode is used the same way that the tune interface of a legacy ERF product is used. The tune word is a two-byte load with the first byte (MSB) being the band the filter should tune to, and the second byte (LSB) being the frequency offset in the chosen band. Legacy tune mode can be selected by leaving the TUNE MODE pin floating or pulled up to +3.3 V. The Legacy tune mode can be used in both serial and parallel modes. Table 5. Legacy Tune Word Properties Symbol Band Value Description VHFL 3 MHz Minimum Tunable Frequency. f MIN is the absolute minimum f MIN VHFH 9.54 MHz frequency that the filter is capable of tuning to for the respective UHF MHz band. VHFL 9 MHz Maximum Tunable Frequency. f MAX is the absolute maximum f MAX VHFH 225 MHz frequency that the filter is capable of tuning to. Sending tune commands greater than the maximum tunable frequency will result in an invalid tune condition. The frequency response of an UHF 52 MHz on the next valid tune command. Varies depending on the band. invalid tune is unknown. Normal frequency response will return f STEP VHFL.24 MHz Tune step size. f STEP is the minimum spacing between adjacent VHFH.54 MHz tune commands. UHF 1.18 MHz Commanded Frequency. f COM is the commanded frequency that is sent over the SPI or Parallel tune command interface. The command can be calculated by subtracting f MIN from the desired f COM - round ( (f DESIRED F MIN ) frequency for the particular band and dividing the result by the ) f f STEP STEP of that particular band and then rounding down to the nearest integer command. This formula is used to select the closest possible frequency to the desired tune word. If the next lowest tune word is desired replace round with floor and if the next highest tune word is desired replace round with ceil. Table 6. Legacy Tune Word Format (MSb) (LSb) 8 Band Bits Commanded Frequency 8 Bits represented as zero must be set to zero for all tune positions. Product Data Sheet Rev of 13

7 MN-3-52-X-S4 Table 7. Band Bit Selection Band Bits Bit 9 Bit 8 Selected Band Band Range (MHz) VHFL VHFH UHF Unsupported, Do not Select - Table 8. Example Legacy Tune Words f DESIRED (MHz) Required Band Band (Hex) f MIN of Band (MHz) f STEP of Band (MHz) f COM Calculation (Decimal) f COM (Decimal) f COM (Hex) Tune Command (Hex) (3 3) 3. VHFL x x x VHFL x 3.24 ( ) x48 x48 9. VHFL x 3.24 (9 3) xfa xfa 9.54 VHFH x ( ).54 x x VHFH x ( ) x43 x VHFH x ( ) xf9 x1f UHF x ( ) 1.18 x x UHF x ( ) x8b x28b 52. UHF x ( ) xf9 x2f9 Product Data Sheet Rev of 13

8 MN-3-52-X-S4 6. SPI (SERIAL PERIPHERAL INTERFACE) TIMING The SPI tune command interface is a standard SPI interface with Mode = (CPOL =, CPHA = ). There are always 16 data bits regardless of the tune mode used. Any bits that do not affect the frequency offset of the filter should always be set to. The interface receives the data most significant byte and most significant bit first. The SPI interface can be used in legacy and bit weighted tune modes. The SPI interface is selected by leaving SER/PAR floating or pulled to V CC. Pin J8 and J15 (CS & STB ) must be tied together externally for SPI mode to function properly. Filter Center Frequency Previous Tune Frequency New Freq TTUNE TUNE READY TNEW CS & STB TWAKE MOSI D15 D14 D TIS TIH SCLK TCSH TCSS TSCK TSCKW TSCKW TSCKF TSCKR Figure 6. Serial Timing Diagram Table 9. SPI Timing Characteristics Symbol Parameter Min. Max. Unit T WAKE Wakeup Time The amount of time from CS & STB transitioning low until TUNE READY transitions high µs T CSS CS & STB Setup Time The amount of time needed from when CS & STB transitions low until the first rising edge of SCLK µs T IS MOSI Setup The amount of time data needs to be present on MOSI before the rising edge of SCK. 1 - ns T IH MOSI Hold The amount of time data needs to be held on MOSI after the rising edge of SCLK. 4 - ns T SCK SCLK Period ns T SCW SCLK Duty Cycle. T SCK 2 - ns T SCKF SCLK Fall Time µs T SCKR SCLK Rise Time µs T CSH CS & STB Hold Time The amount of time CS & STB needs to remain low after the last falling edge of SCLK. 5 - ns T NEW New Command Delay The amount of between subsequent falling edges of CS. This is the time between the start of new tune commands. 5 - µs T TUNE Time from the last rising edge of clock until the RF response reaches 9% µs V CC = 3.3 V +/-5%, = V 9 Refer to section 9. Tune Time. Product Data Sheet Rev of 13

9 7. PARALLEL INTERFACE MN-3-52-X-S4 The Parallel tune command interface is an 8-bit wide synchronous parallel interface with a two-byte load. There are always 16 data bits per parallel tune regardless of the tune mode used. Any bits that do not affect the frequency offset of the filter should always be set to. A7 is the most significant bit and A is the least significant bit. The Parallel interface can be used in legacy and bit weighted tune modes. Keeping SER/PAR pulled to will enable the parallel tune command interface. Filter Center Frequency Previous Tune Frequency New Freq TTUNE TUNE READY TNEW TWAKE TSTBW STB TSTBS TSTBH TSTBS TSTBH PARALLEL DATA A7-A MSByte LSByte Figure 7. Parallel Timing Diagram Table 1. Parallel Timing Characteristics Symbol Parameter Min. Max. Unit T WAKE Wakeup Time The amount of time from STB transitioning low until TUNE READY transitions high. 6.5 µs Strobe Wait Time The amount of time needed to wait after STB transitions low T STBW before STB can transition back high to latch the most significant byte of the parallel 7.1 µs tune command. T STBS Parallel Data Setup Time The amount of time parallel data needs to be present and valid before STB transitions high. 3 ns T STBH Parallel Command Hold Time The amount of time the command data needs to be present and valid after STB transitions high. 3 ns T NEW New Command Delay The amount of between the first falling edge of. STB This is the time between the start of new tune commands. 5 µs T TUNE Time from the last rising edge of STB until the RF response reaches 9% µs V CC = 3.3 V +/-5%, = V 1 Refer to section 9. Tune Time. Product Data Sheet Rev of 13

10 8. ADDITIONAL PIN DETAIL MN-3-52-X-S4 Pin Name TUNE READY SER/PAR CS & STB TUNE MODE Detail Tune Ready Indicator The TUNE READY pin is a driven digital output, do not connect any other push-pull output directly to this pin. The function of the TUNE READY pin is to indicate the status of the digital interface during/after tune events. The normal logic state of TUNE READY is low/deasserted at power up. In this condition, the filter is ready to receive a new tune command. When a new tune command is initiated by pulling CS & STB low in serial mode or pulling STB low in parallel mode, the TUNE READY pin will transition high/assert after the filter is ready to start receiving digital data. The external control circuit must monitor the TUNE READY pin to determine when it transitions high or alternatively, delay for the minimum Control Circuit Setup Time before loading the digital data. Once the filter has received the valid tune command and has finished processing all tune functions, the TUNE READY pin will return to a logic low/de-asserted state. Note: In Parallel interface mode, if the TUNE READY pin is stuck high after completing a parallel tune, there is a chance that the control circuitry missed the second rising edge of STB. If this happens transition STB low for > 3 ns and then back high. If the TUNE READY pin transitions low, the filter can be re-tuned. Serial/Parallel Command Interface Selection The SER/PAR is sampled at power-up to determine which tune interface should be used to tune the filter. Leaving SER/PAR floating or pulled to V CC will enable the SPI (serial) tune command interface. Keeping SER/PAR pulled to will enable the parallel tune command interface. Changes to interface modes will only take effect at power-up and cannot be changed on the fly. SPI Chip Select and Tune Strobe In Serial interface mode, STB wakes the control circuitry on a low transition. For proper operation in SPI mode, tie the CS (pin 8) and STB (pin 15) directly together externally or SPI mode will not function. In Parallel interface mode, CS is multiplexed with Parallel data A4. STB wakes the control circuitry on a low transition. The two subsequent rising edges of STB will load the most significant byte and least significant byte respectively. Tune mode pin The TUNE MODE pin is sampled at power-up to determine which tune mode should be used to tune the filter. Leave the TUNE MODE pin floating or pull to V CC to enable legacy tune mode. Pull the TUNE MODE pin to ground to enable frequency weighted tune mode. Changes to the tune mode will only take effect at power-up and cannot be changed on the fly. Product Data Sheet Rev of 13

11 MN-3-52-X-S4 9. TUNE TIME Tune times include internal processing of the tune command data and the 9% settled RF response time of the filter. This time excludes the time required to load the tune command into the filter. Low level signal measurements were utilized to show the Rx tune time that can be expected. In addition, RF power in excess of +25 dbm is considered to be hot switching of the filter. While the data in Table 11. Typical RF Tune Times was taken via hot switching, this does not imply that tuning operation of the filter into these levels can be done reliably. It is recommended that RF is less than +2dBm during a tune event. Table 11. Typical RF Tune Times 11 Freq (MHz) Input Power (dbm) Band From To dbm 3 9 VHFL () us 9 3 VHFL () us VHFH (1) us VHFH (1) us UHF (2) us UHF (2) us 3 52 VHFL () to UHF (2) us 52 3 UHF (2) to VHFL () us 1. APPLICATION INFORMATION Table 12. Application Information Symbol V BB T RATE Description High bias supply voltage It is recommended that an external high voltage capacitor be placed from V BB (pin 18) to in order to prevent V BB from sagging during a tune event (There can be large instantaneous/surge currents on V BB while the filter is switching to a new tune frequency. An external capacitor of 1 µf minimum is recommended in order to keep the sagging to a minimum. Additional capacitance above 1 µf may be required, depending on the V BB supply being utilized.). Maximum tune rate The maximum rate at which the filter can be continuously tuned (to different frequencies) is 2 khz. As this rate is increased from static to the maximum rate of 2 khz, V BB (the high voltage supply) current will increase. With V BB set to +1 VDC, and re-tuning at the maximum rate of 2 khz, V BB current can increase to a maximum of around 15 ma (the actual current will likely be less than this since it depends on the actual tune frequencies used. 15 ma should be considered the worst case V BB current.) 11 Data taken in Parallel, Legacy interface mode. Tune time is measured from 2 nd rising edge of strobe to 9% RF output. ( Serial interface mode performance is similar). Product Data Sheet Rev of 13

12 MN-3-52-X-S4 11. DIMENSIONS All dimensions specified in inches [mm]. 12. RECOMMENDED PAD LAYOUT All dimensions specified in inches [mm]. Product Data Sheet Rev of 13

13 13. APPLICATION CIRCUITS MN-3-52-X-S4 Figure 8. Serial Application Circuit Figure 9. Parallel Application Circuit Product Data Sheet Rev of 13