Achieving Timing Closure in ALTERA FPGAs

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Maurice Chandler
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Achieving Timing Closure in ALTERA FPGAs Course Description This course provides all necessary theoretical and practical know-how to write system timing constraints for variety designs in ALTERA

1 Achieving Timing Closure in ALTERA FPGAs Course Description This course provides all necessary theoretical and practical know-how to write system timing constraints for variety designs in ALTERA FPGAs. The course goes into great depth and touches upon every aspect of timing constraints for high frequency, I/Os, area, power, timing analysis, timing problems, as well as timing exceptions. The course begins with static timing analysis flow, continues with methods to write timing constraints into an SDC file, write test-benches and run them in the simulator post place & route. The course also covers timing analysis methodology, and how to achieve timing closure. In addition, the course embeds complex timing constraints examples such as DDR memory, Analog to digital converter, SERDES, source synchronous, multiple clock domains, IPs. The course ends with teaching of how to generate advanced reports, analyze variety problems and solve them via RTL code and Quartus II software. The course combines 50% theory with 50% practical work in every meeting. The practical labs cover most of the theory and also include practical digital design. Course Duration 4 days

2 Goals 1. Become familiar with the design process using TimeQuest 2. Generate SDC file and reports 3. Become familiar with TimeQuest terms and terminology 4. Write clock constraints 5. Write I/Os constraints 6. Write asynchronous signals constraints 7. Write multi-cycle and false path constraints 8. Write DDR and high-speed interfaces constraints 9. Optimize frequency, area and power with Quartus II tools 10. Analyze timing problems and solve them in a teamwork Intended Users Hardware engineers who develop FPGAs and would like to enhance their skills, in order to acquire better expertise with TimeQuest, and be able to write constraints for advanced interfaces Previous Knowledge FPGA design, VHDL/Verilog, ModelSim Course Material 1. Synthesizer and Place & Route: Quartus II (ALTERA) 2. Course book (including labs)

3 Table of Contents Day #1 Introduction to Timing Analysis o TimeQuest tool overview o Basic steps to using TimeQuest (generate timing netlist, enter SDC constraints, update timing netlist, generate timing reports) o Using TimeQuest in Quartus II flow o Timing analysis basics (Launch Vs Latch edges, setup and hold times, data and clock arrival time, data required time, setup and hold slack analysis, I/O analysis, recovery and removal, timing models) Timing Reports o Reporting in Quartus II Vs reporting in TimeQuest o Custom, summary and diagnostic reports o Clock transfer, datasheet, Fmax reports o Slack histogram report o Detailed slack/path report, further path analysis Introduction to Timing Constraints o Importance of constraining o Enter constraints o SDC netlist terminology o Collections SDC Timing Constraints o Internal and virtual clocks o Generated clocks (inverted clocks, phase shifted clocks o PLL clocks and derive_pll_clocks Altera SDC extension o Automatic clock detection and creation o Non ideal clock constraints (Jitter, latency on PCB) o Common clock path pessimism removal o Checking clock constraints o Report clocks

4 Day #2 SDC Timing Constraints for I/O o Combinational I/O interface constraints (max & min delay constraints) o Synchronous inputs constraints (setup and hold time calculations, set_input_delay max & min, set_output_delay min& max, when to use each constraint, output pin load, signal integrity metrices) o Source synchronous interface constraints (SDR Source synchronous input center aligned, using SDC with source synchronous input, SDR source synchronous output center aligned, source synchronous edge aligned) o Checking I/O constraints (report SDC, report unconstrained path, report ignored constraint) Asynchronous Path Constraints o Asynchronous path definition o TimeQuest and asynchronous ports o Recovery and removal constraints o Externally registered asynchronous paths constraints o Internally registered asynchronous paths constraints o Checking and reporting asynchronous control constraints o Truly asynchronous control inputs o The problem with latches Timing exception o False path constraints (logic based, timing based, set_clock_groups and set_false_path commands, clock mux constraints, synchronizers constraints, FIFO constraints) o Verifying false paths and groups o Multicycle path constraints (multicycle types, multicycle setup and hold, multicycle with and without enable signal, positive clock phase shift or offset, source clock at higher frequency) o Reporting multicycles o Absolute and annotated delays constraints

5 Day #3 Application Constraints o Reset synchronizer constraints & reporting o Externally switched clocks constraints o PLL clock switchover constraints o Multiple virtual clocks in I/O constraints o I/O timing requirements Tsetup, Tco, Th o JTAG signals constraints o Tri-state outputs constraints o Input and output delays with multiple clocks o High performance FPGA PLL analysis with TimeQuest o LVDS SERDES constraints (TCCS and RSKM) o Analyzing timing of external memory (DDR,DDR2,DDR3) o ADC constraints Day #4 Achieving Timing Closure o Frequency problems & solutions (long combinational path, fanout, place & route issues, global signals, synchronous vs asynchronous generated signals, pipeline) o Clock domain problems (where to place and constrain the synchronizers) o I/O problems (I/O registers, lock the delay chain settings for I/O cells, PLL shifting to meet I/O timing, slew rate) Achieving Timing Closure in Team Based Designs o Design partitioning with incremental compilation & LogicLock o Hierarchical design rules o Design space explorer o Floorplanning assignments o ECO (Engineering Change Order) o Missing timing constraints o Conflicting timing constraints o Overly restrictive location constraints

קורס Achieving Timing Closure in ALTERA FPGAs

קורס Achieving Timing Closure in ALTERA FPGAs תיאור הקורס קורסזהמספקאתכלהידע התיאורטיוהמעשילכתיבתאילוצימערכת לתכנוניםמגווניםברכיבי ALTERA עלמנתלעמודבדרישותהפרויקט. הקורס מעמיק מאוד ונוגע בכל אספקט של תדר,