Dr. Shahram Shirani COE2DI4 Midterm Test #2 Nov 19, 2008
|
|
- Elmer Wells
- 6 years ago
- Views:
Transcription
1 Page 1 Dr. Shahram Shirani COE2DI4 Midterm Test #2 Nov 19, 2008 Instructions: This examination paper includes 13 pages and 20 multiple-choice questions starting on page 3. You are responsible for ensuring that your copy of the paper is complete. Bring any discrepancy to the attention of your invigilator. The answers for all the questions must be indicated by filling the corresponding circle on the optical scanning (OMR) examination sheet. This OMR examination sheet is the only page to be handed in. The instructions for completing the OMR examination sheet are provided on page 2. Read and follow these instructions with care! There is one mark for each question. Answer all questions. There is no penalty for guessing. This is a closed book exam. No reference material of any kind is permitted. No calculators of any kind are permitted. Time allowed is 50 minutes. Note: A' and A are used interchangeably. Continued on page 2
2 Page 2 OMR examination instructions Continued on page 3
3 Page 3 Multiple choice questions (numbered 1 to 20) indicate your answer by filling the corresponding circle on the OMR answer sheet 1. Consider function G(A,B,C)=AB+BC. Let F(A,B,C) be the dual of G(A,B,C). Then F(A,B,C) can be implemented using A as the select (control) input to a 2-to-1 multiplexer. The correct implementation of F(A,B,C) is shown in: 1. Figure 1(a) 2. Figure 1(b) 3. Figure 1(c) 4. Figure 1(d) Figure 1 - Implementations for function F(A,B,C) for question Function F(A,B,C)= Σ m(1,3,4,5) can be implemented using B and C as the select (control) inputs to a 4-to-1 multiplexer. The correct implementation is shown in: 1. Figure 2(a) 2. Figure 2(b) 3. Figure 2(c) 4. Figure 2(d) Continued on page 4
4 Page 4 Figure 2 - Implementations for function F(A,B,C) for question 2. Figure 3 - Block diagrams and truth tables for decoders without an enable signal for questions 3 and 4 3. The circuit shown in Figure 4 is: 1. F(A,B,C,D) = Σ m(0,1,2,3) 2. F(A,B,C,D) = Σ m(0,3,12,15) 3. F(A,B,C,D) = Σ m(0,4,8,12) 4. F(A,B,C,D) = Σ m(0,5,10,15) Figure 4 Circuit for question 3. Use the truth table of the decoder with un-inverted outputs shown in Figure 3(a). Continued on page 5
5 Page 5 4. The circuit shown in Figure 5 is: 1. F(A,B,C,D) = M(0,2,13,15) 2. F(A,B,C,D) = M(0,4,11,15) 3. F(A,B,C,D) = M (0,5,10,15) 4. F(A,B,C,D) = M (0,7,8,15) Figure 5 Circuit for question 4. Use the truth table of the decoder with inverted outputs shown in Figure 3(b). 5. The circuit from Figure 6 is equivalent to the circuit from: 1. Figure 7(a) 2. Figure 7(b) 3. Figure 7(c) 4. Figure 7(d) Figure 6 - Circuit for question 5. Continued on page 6
6 COE2DI4 Midterm Test #2 Fall 2008 Page 6 Figure 7 - Circuits for question A Moore machine has one input and one output. The output should be 1 if the total number of 0s received at the input is odd and the total number of 1s received is an even number greater than 0. This machine can be implemented in how many states? A flip-flop has a 3-ns delay from the time the clock edge occurs to the time the output is complemented. What is the maximum frequency that a 10-bit binary ripple counter that uses this flipflop can operate with reliability? MHz MHz MHz MHz MHz Continued on page 7
7 COE2DI4 Midterm Test #2 Fall 2008 Page 7 Figure 8 - Sequential (or storage) elements and signal waveforms for questions 8, 9 and 10. Note, the initial value of all the storage elements is zero and they are assumed to be ideal, i.e., the propagation delays and setup/hold times are considered to be zero. 8. Given the clock and d in waveforms in Figure 8(b) the waveform for Q A from Figure 8(a) is: 1. wave 1 from Figure 8(b) 2. wave 2 from Figure 8(b) 3. wave 3 from Figure 8(b) 4. wave 4 from Figure 8(b) 5. wave 5 from Figure 8(b) 9. Given the clock and d in waveforms in Figure 8(b) the waveform for Q B from Figure 8(a) is: 1. wave 4 from Figure 8(b) 2. wave 5 from Figure 8(b) 3. wave 6 from Figure 8(b) 4. wave 7 from Figure 8(b) 5. wave 8 from Figure 8(b) 10. Given the clock and d in waveforms in Figure 8(b) the waveform for Q C from Figure 8(a) is: 1. wave 4 from Figure 8(b) 2. wave 5 from Figure 8(b) 3. wave 6 from Figure 8(b) 4. wave 7 from Figure 8(b) 5. wave 8 from Figure 8(b) Continued on page 8
8 COE2DI4 Midterm Test #2 Fall 2008 Page In Figure 9, if the current state is Q 3 Q 2 Q 1 Q 0 =1101, then after the next positive edge of the clock signal the new state will be: Figure 9 - Circuit for question 11 (note, the flip-flops are positive edge triggered). Note for question 11: Because NOT all the flip-flops clock inputs share the same clock signal, it is considered that the new state value will be observed only when all the flip-flops outputs have become stable, i.e., after all the events triggered by the positive edge of the clock signal have been completed. 12. The periodic sequence Q 2 Q 1 Q 0 generated by the circuit shown in Figure 10 is: , 111, 011, 010, , 111, 011, , 111, , 111 Figure 10 - Circuit for question 12 (it is assumed that after power up the state is 000). Continued on page 9
9 COE2DI4 Midterm Test #2 Fall 2008 Page Using a synchronous 3-bit up counter with parallel load capability (Q 2 and D 2 are the most significant bits) the circuit shown in Figure 11 generates the following periodic sequence: 1. 0, 2, 3, 4, 6, , 2, 3, 4, , 2, 3, , 2, , 4 Figure 11 Circuit for question 13 (it is assumed that after power up the state is 000). 14. Figure 12 shows a frequency division circuit implemented using a synchronous 4-bit up-counter with parallel load capability capability (Q 3 and D 3 are the most significant bits). If the frequency of the clock signal is 60 MHz, then signal z, which is a periodic signal, has its frequency equal to: MHz MHz MHz MHz 5. 6 MHz Tip for question 14: To compute the frequency of signal z, you must derive the periodic sequence generated by the circuit from Figure The single precision IEEE binary floating point representation of a number is What is the decimal value of this number? none of the above Figure 12 Circuit for question 14 (it is assumed that after power up the state is 1010). Continued on page 10
10 COE2DI4 Midterm Test #2 Fall 2008 Page 10 Figure 13 - State table and circuit for questions 16, 17 and 18. Note, Q A is the most significant bit. Tip: fill in the truth tables and use K-maps for logic minimization. Continued on page 11
11 COE2DI4 Midterm Test #2 Fall 2008 Page 11 Figure 14 - Circuit implementations for questions 16, 17 and Consider the state transition table of a sequential circuit shown in Figure 13(a) (see previous page). If in our technology library we have only one JK flip-flop, one T flip-flop and one D flip-flop, then a generic implementation is shown Figure 13(b) (see previous page). Based on the state transition table and circuit topology shown in Figure 13, the logic function, which drives the input J A of the leftmost flipflop from Figure 13(b) is shown in: 1. Figure 14(a) 2. Figure 14(b) 3. Figure 14(c) 4. Figure 14(d) 5. Figure 14(e) 17. Consider the state transition table of a sequential circuit shown in Figure 13(a) (see previous page). If in our technology library we have only one JK flip-flop, one T flip-flop and one D flip-flop, then a generic implementation is shown Figure 13(b) (see previous page). Based on the state transition table and circuit topology shown in Figure 13, the logic function, which drives the input T B of the center flipflop from Figure 13(b) is shown in: 1. Figure 14(a) 2. Figure 14(b) 3. Figure 14(c) 4. Figure 14(d) 5. Figure 14(e) 18. Consider the state transition table of a sequential circuit shown in Figure 13(a) (see previous page). If in our technology library we have only one JK flip-flop, one T flip-flop and one D flip-flop, then a generic implementation is shown Figure 13(b) (see previous page). Based on the state transition table and circuit topology shown in Figure 13, the logic function, which drives the input D C of the rightmost flip-flop from Figure 13(b) is shown in: 1. Figure 14(a) 2. Figure 14(b) 3. Figure 14(c) 4. Figure 14(d) 5. Figure 14(e) Continued on page 12
12 COE2DI4 Midterm Test #2 Fall 2008 Page 12 Figure 15 - Circuit for question Consider the sequential circuit shown in Figure 15. Consider the following state assignment: A stands for Q=0, B stands for Q=1. The state transition diagram for the circuit from Figure 15 is shown in: 1. Figure 16(a) 2. Figure 16(b) 3. Figure 16(c) 4. Figure 16(d) Figure 16 - State transition diagrams for question 19. Continued on page 13
13 COE2DI4 Midterm Test #2 Fall 2008 Page 13 Figure 17 - Circuit for question Consider the sequential circuit shown in Figure 17. Consider the following state assignment: A stands for Q=0, B stands for Q=1. The state transition diagram for the circuit from Figure 16 is shown in: 1. Figure 18(a) 2. Figure 18(b) 3. Figure 18(c) 4. Figure 18(d) Figure 18 - State transition diagrams for question THE END - Continued on page 14
1. Convert the decimal number to binary, octal, and hexadecimal.
1. Convert the decimal number 435.64 to binary, octal, and hexadecimal. 2. Part A. Convert the circuit below into NAND gates. Insert or remove inverters as necessary. Part B. What is the propagation delay
More informationFinal Exam review: chapter 4 and 5. Supplement 3 and 4
Final Exam review: chapter 4 and 5. Supplement 3 and 4 1. A new type of synchronous flip-flop has the following characteristic table. Find the corresponding excitation table with don t cares used as much
More informationYEDITEPE UNIVERSITY DEPARTMENT OF COMPUTER ENGINEERING. EXPERIMENT VIII: FLIP-FLOPS, COUNTERS 2014 Fall
YEDITEPE UNIVERSITY DEPARTMENT OF COMPUTER ENGINEERING EXPERIMENT VIII: FLIP-FLOPS, COUNTERS 2014 Fall Objective: - Dealing with the operation of simple sequential devices. Learning invalid condition in
More information1. True/False Questions (10 x 1p each = 10p) (a) I forgot to write down my name and student ID number.
CprE 281: Digital Logic Midterm 2: Friday Oct 30, 2015 Student Name: Student ID Number: Lab Section: Mon 9-12(N) Mon 12-3(P) Mon 5-8(R) Tue 11-2(U) (circle one) Tue 2-5(M) Wed 8-11(J) Wed 6-9(Y) Thur 11-2(Q)
More informationChapter 6. Flip-Flops and Simple Flip-Flop Applications
Chapter 6 Flip-Flops and Simple Flip-Flop Applications Basic bistable element It is a circuit having two stable conditions (states). It can be used to store binary symbols. J. C. Huang, 2004 Digital Logic
More informationAsynchronous (Ripple) Counters
Circuits for counting events are frequently used in computers and other digital systems. Since a counter circuit must remember its past states, it has to possess memory. The chapter about flip-flops introduced
More informationASYNCHRONOUS COUNTER CIRCUITS
ASYNCHRONOUS COUNTER CIRCUITS Asynchronous counters do not have a common clock that controls all the Hipflop stages. The control clock is input into the first stage, or the LSB stage of the counter. The
More informationLecture 8: Sequential Logic
Lecture 8: Sequential Logic Last lecture discussed how we can use digital electronics to do combinatorial logic we designed circuits that gave an immediate output when presented with a given set of inputs
More informationCounter dan Register
Counter dan Register Introduction Circuits for counting events are frequently used in computers and other digital systems. Since a counter circuit must remember its past states, it has to possess memory.
More informationLogic and Computer Design Fundamentals. Chapter 7. Registers and Counters
Logic and Computer Design Fundamentals Chapter 7 Registers and Counters Registers Register a collection of binary storage elements In theory, a register is sequential logic which can be defined by a state
More informationLATCHES & FLIP-FLOP. Chapter 7
LATCHES & FLIP-FLOP Chapter 7 INTRODUCTION Latch and flip flops are categorized as bistable devices which have two stable states,called SET and RESET. They can retain either of this states indefinitely
More informationRS flip-flop using NOR gate
RS flip-flop using NOR gate Triggering and triggering methods Triggering : Applying train of pulses, to set or reset the memory cell is known as Triggering. Triggering methods:- There are basically two
More informationObjectives. Combinational logics Sequential logics Finite state machine Arithmetic circuits Datapath
Objectives Combinational logics Sequential logics Finite state machine Arithmetic circuits Datapath In the previous chapters we have studied how to develop a specification from a given application, and
More information1 Hour Sample Test Papers: Sample Test Paper 1. Roll No.
6.1.2 Sample Test Papers: Sample Test Paper 1 Roll No. Institute Name: Course Code: EJ/EN/ET/EX/EV/IC/IE/IS/MU/DE/ED/ET/IU Subject: Principles of Digital Techniques Marks: 25 1 Hour 1. All questions are
More informationDepartment of Electrical and Computer Engineering Mid-Term Examination Winter 2012
1 McGill University Faculty of Engineering ECSE-221B Introduction to Computer Engineering Department of Electrical and Computer Engineering Mid-Term Examination Winter 2012 Examiner: Rola Harmouche Date:
More informationLecture 12. Amirali Baniasadi
CENG 24 Digital Design Lecture 2 Amirali Baniasadi amirali@ece.uvic.ca This Lecture Chapter 6: Registers and Counters 2 Registers Sequential circuits are classified based in their function, e.g., registers.
More informationUniversal Asynchronous Receiver- Transmitter (UART)
Universal Asynchronous Receiver- Transmitter (UART) (UART) Block Diagram Four-Bit Bidirectional Shift Register Shift Register Counters Shift registers can form useful counters by recirculating a pattern
More information1.b. Realize a 5-input NOR function using 2-input NOR gates only.
. [3 points] Short Questions.a. Prove or disprove that the operators (,XOR) form a complete set. Remember that the operator ( ) is implication such that: A B A B.b. Realize a 5-input NOR function using
More informationproblem maximum score 1 28pts 2 10pts 3 10pts 4 15pts 5 14pts 6 12pts 7 11pts total 100pts
University of California at Berkeley College of Engineering Department of Electrical Engineering and Computer Sciences EECS150 J. Wawrzynek Spring 2002 4/5/02 Midterm Exam II Name: Solutions ID number:
More informationDigital Fundamentals: A Systems Approach
Digital Fundamentals: A Systems Approach Counters Chapter 8 A System: Digital Clock Digital Clock: Counter Logic Diagram Digital Clock: Hours Counter & Decoders Finite State Machines Moore machine: One
More informationThe word digital implies information in computers is represented by variables that take a limited number of discrete values.
Class Overview Cover hardware operation of digital computers. First, consider the various digital components used in the organization and design. Second, go through the necessary steps to design a basic
More informationSri Vidya College of Engineering And Technology. Virudhunagar Department of Electrical and Electronics Engineering
Sri Vidya College of Engineering And Technology Virudhunagar 626 005 Department of Electrical and Electronics Engineering Year/ Semester/ Class : II/ III/ EEE Academic Year: 2017-2018 Subject Code/ Name:
More informationRegisters and Counters
Registers and Counters Clocked sequential circuit = F/Fs and combinational gates Register Group of flip-flops (share a common clock and capable of storing one bit of information) Consist of a group of
More informationRegisters and Counters
Registers and Counters Clocked sequential circuit = F/Fs and combinational gates Register Group of flip-flops (share a common clock and capable of storing one bit of information) Consist of a group of
More informationR13. II B. Tech I Semester Regular Examinations, Jan DIGITAL LOGIC DESIGN (Com. to CSE, IT) PART-A
SET - 1 Note: Question Paper consists of two parts (Part-A and Part-B) Answer ALL the question in Part-A Answer any THREE Questions from Part-B a) What are the characteristics of 2 s complement numbers?
More informationExperiment 8 Introduction to Latches and Flip-Flops and registers
Experiment 8 Introduction to Latches and Flip-Flops and registers Introduction: The logic circuits that have been used until now were combinational logic circuits since the output of the device depends
More informationQuiz #4 Thursday, April 25, 2002, 5:30-6:45 PM
Last (family) name: First (given) name: Student I.D. #: Circle section: Hu Saluja Department of Electrical and Computer Engineering University of Wisconsin - Madison ECE/CS 352 Digital System Fundamentals
More informationFind the equivalent decimal value for the given value Other number system to decimal ( Sample)
VELAMMAL COLLEGE OF ENGINEERING AND TECHNOLOGY, MADURAI 65 009 Department of Information Technology Model Exam-II-Question bank PART A (Answer for all Questions) (8 X = 6) K CO Marks Find the equivalent
More informationChapter 4. Logic Design
Chapter 4 Logic Design 4.1 Introduction. In previous Chapter we studied gates and combinational circuits, which made by gates (AND, OR, NOT etc.). That can be represented by circuit diagram, truth table
More informationIT T35 Digital system desigm y - ii /s - iii
UNIT - III Sequential Logic I Sequential circuits: latches flip flops analysis of clocked sequential circuits state reduction and assignments Registers and Counters: Registers shift registers ripple counters
More informationCHAPTER 6 COUNTERS & REGISTERS
CHAPTER 6 COUNTERS & REGISTERS 6.1 Asynchronous Counter 6.2 Synchronous Counter 6.3 State Machine 6.4 Basic Shift Register 6.5 Serial In/Serial Out Shift Register 6.6 Serial In/Parallel Out Shift Register
More informationCOE 202: Digital Logic Design Sequential Circuits Part 1. Dr. Ahmad Almulhem ahmadsm AT kfupm Phone: Office:
COE 202: Digital Logic Design Sequential Circuits Part 1 Dr. Ahmad Almulhem Email: ahmadsm AT kfupm Phone: 860-7554 Office: 22-324 Objectives Sequential Circuits Memory Elements Latches Flip-Flops Combinational
More informationR13 SET - 1 '' ''' '' ' '''' Code No: RT21053
SET - 1 1. a) What are the characteristics of 2 s complement numbers? b) State the purpose of reducing the switching functions to minimal form. c) Define half adder. d) What are the basic operations in
More informationNH 67, Karur Trichy Highways, Puliyur C.F, Karur District UNIT-III SEQUENTIAL CIRCUITS
NH 67, Karur Trichy Highways, Puliyur C.F, 639 114 Karur District DEPARTMENT OF ELETRONICS AND COMMUNICATION ENGINEERING COURSE NOTES SUBJECT: DIGITAL ELECTRONICS CLASS: II YEAR ECE SUBJECT CODE: EC2203
More informationModule -5 Sequential Logic Design
Module -5 Sequential Logic Design 5.1. Motivation: In digital circuit theory, sequential logic is a type of logic circuit whose output depends not only on the present value of its input signals but on
More informationIntroduction. NAND Gate Latch. Digital Logic Design 1 FLIP-FLOP. Digital Logic Design 1
2007 Introduction BK TP.HCM FLIP-FLOP So far we have seen Combinational Logic The output(s) depends only on the current values of the input variables Here we will look at Sequential Logic circuits The
More informationReview of digital electronics. Storage units Sequential circuits Counters Shifters
Review of digital electronics Storage units Sequential circuits ounters Shifters ounting in Binary A counter can form the same pattern of 0 s and 1 s with logic levels. The first stage in the counter represents
More informationComputer Organization & Architecture Lecture #5
Computer Organization & Architecture Lecture #5 Shift Register A shift register is a register in which binary data can be stored and then shifted left or right when a shift signal is applied. Bits shifted
More informationChapter 6 Registers and Counters
EEA051 - Digital Logic 數位邏輯 Chapter 6 Registers and Counters 吳俊興國立高雄大學資訊工程學系 January 2006 Chapter 6 Registers and Counters 6-1 Registers 6-2 Shift Registers 6-3 Ripple Counters 6-4 Synchronous Counters
More informationLogic Design. Flip Flops, Registers and Counters
Logic Design Flip Flops, Registers and Counters Introduction Combinational circuits: value of each output depends only on the values of inputs Sequential Circuits: values of outputs depend on inputs and
More informationMidterm Examination II
Midterm Examination II EE 203 - Digital Systems DESIGN (Fall 2015) MEF University Instructions Assigned: 6:30pm on December 17, 2015. Due: 8:00pm on December 17, 2015. Instructor: Şuayb Ş. Arslan. Name:
More information(CSC-3501) Lecture 7 (07 Feb 2008) Seung-Jong Park (Jay) CSC S.J. Park. Announcement
Seung-Jong Park (Jay) http://www.csc.lsu.edu/~sjpark Computer Architecture (CSC-3501) Lecture 7 (07 Feb 2008) 1 Announcement 2 1 Combinational vs. Sequential Logic Combinational Logic Memoryless Outputs
More informationRS flip-flop using NOR gate
RS flip-flop using NOR gate Triggering and triggering methods Triggering : Applying train of pulses, to set or reset the memory cell is known as Triggering. Triggering methods:- There are basically two
More informationCprE 281: Digital Logic
CprE 28: Digital Logic Instructor: Alexander Stoytchev http://www.ece.iastate.edu/~alexs/classes/ Registers and Counters CprE 28: Digital Logic Iowa State University, Ames, IA Copyright Alexander Stoytchev
More informationMidterm Exam 15 points total. March 28, 2011
Midterm Exam 15 points total March 28, 2011 Part I Analytical Problems 1. (1.5 points) A. Convert to decimal, compare, and arrange in ascending order the following numbers encoded using various binary
More informationCHAPTER 4: Logic Circuits
CHAPTER 4: Logic Circuits II. Sequential Circuits Combinational circuits o The outputs depend only on the current input values o It uses only logic gates, decoders, multiplexers, ALUs Sequential circuits
More informationBCN1043. By Dr. Mritha Ramalingam. Faculty of Computer Systems & Software Engineering
BCN1043 By Dr. Mritha Ramalingam Faculty of Computer Systems & Software Engineering mritha@ump.edu.my http://ocw.ump.edu.my/ authors Dr. Mohd Nizam Mohmad Kahar (mnizam@ump.edu.my) Jamaludin Sallim (jamal@ump.edu.my)
More informationCombinational vs Sequential
Combinational vs Sequential inputs X Combinational Circuits outputs Z A combinational circuit: At any time, outputs depends only on inputs Changing inputs changes outputs No regard for previous inputs
More informationRangkaian Sekuensial. Flip-flop
Rangkaian Sekuensial Rangkaian Sekuensial Flip-flop Combinational versus Sequential Functions Logic functions are categorized as being either combinational (sometimes referred to as combinatorial) or sequential.
More informationEMT 125 Digital Electronic Principles I CHAPTER 6 : FLIP-FLOP
EMT 125 Digital Electronic Principles I CHAPTER 6 : FLIP-FLOP 1 Chapter Overview Latches Gated Latches Edge-triggered flip-flops Master-slave flip-flops Flip-flop operating characteristics Flip-flop applications
More informationName: Date: Suggested Reading Chapter 7, Digital Systems, Principals and Applications; Tocci
Richland College Engineering Technology Rev. 0 B. Donham Rev. 1 (7/2003) J. Horne Rev. 2 (1/2008) J. Bradbury Digital Fundamentals CETT 1425 Lab 7 Asynchronous Ripple Counters Name: Date: Objectives: To
More informationCSE Latches and Flip-flops Dr. Izadi. NOR gate property: A B Z Cross coupled NOR gates: S M S R Q M
CSE-4523 Latches and Flip-flops Dr. Izadi NOR gate property: A B Z A B Z Cross coupled NOR gates: S M S R M R S M R S R S R M S S M R R S ' Gate R Gate S R S G R S R (t+) S G R Flip_flops:. S-R flip-flop
More informationEET2411 DIGITAL ELECTRONICS
5-8 Clocked D Flip-FlopFlop One data input. The output changes to the value of the input at either the positive going or negative going clock trigger. May be implemented with a J-K FF by tying the J input
More informationUNIT-3: SEQUENTIAL LOGIC CIRCUITS
UNIT-3: SEQUENTIAL LOGIC CIRCUITS STRUCTURE 3. Objectives 3. Introduction 3.2 Sequential Logic Circuits 3.2. NAND Latch 3.2.2 RS Flip-Flop 3.2.3 D Flip-Flop 3.2.4 JK Flip-Flop 3.2.5 Edge Triggered RS Flip-Flop
More informationAsynchronous Counter
Asynchronous Counter Contents: Asynchronous/Ripple Counter Propagation Delay in Ripple Counter MOD Number Synchronous/Parallel Counter 10101010101010101010101010101010101010101010101010101010101010101010101010101010
More informationContents Circuits... 1
Contents Circuits... 1 Categories of Circuits... 1 Description of the operations of circuits... 2 Classification of Combinational Logic... 2 1. Adder... 3 2. Decoder:... 3 Memory Address Decoder... 5 Encoder...
More informationFlip Flop. S-R Flip Flop. Sequential Circuits. Block diagram. Prepared by:- Anwar Bari
Sequential Circuits The combinational circuit does not use any memory. Hence the previous state of input does not have any effect on the present state of the circuit. But sequential circuit has memory
More informationDecade Counters Mod-5 counter: Decade Counter:
Decade Counters We can design a decade counter using cascade of mod-5 and mod-2 counters. Mod-2 counter is just a single flip-flop with the two stable states as 0 and 1. Mod-5 counter: A typical mod-5
More informationCHAPTER 4: Logic Circuits
CHAPTER 4: Logic Circuits II. Sequential Circuits Combinational circuits o The outputs depend only on the current input values o It uses only logic gates, decoders, multiplexers, ALUs Sequential circuits
More informationChapter 5 Sequential Circuits
Logic and Computer Design Fundamentals Chapter 5 Sequential Circuits Part 2 Sequential Circuit Design Charles Kime & Thomas Kaminski 28 Pearson Education, Inc. (Hyperlinks are active in View Show mode)
More informationDigital Systems Based on Principles and Applications of Electrical Engineering/Rizzoni (McGraw Hill
Digital Systems Based on Principles and Applications of Electrical Engineering/Rizzoni (McGraw Hill Objectives: Analyze the operation of sequential logic circuits. Understand the operation of digital counters.
More informationSEMESTER ONE EXAMINATIONS 2002
SEMESTER ONE EXAMINATIONS 2002 EE101 Digital Electronics Solutions Question 1. An assembly line has 3 failsafe sensors and 1 emergency shutdown switch. The Line should keep moving unless any of the following
More informationReport on 4-bit Counter design Report- 1, 2. Report on D- Flipflop. Course project for ECE533
Report on 4-bit Counter design Report- 1, 2. Report on D- Flipflop Course project for ECE533 I. Objective: REPORT-I The objective of this project is to design a 4-bit counter and implement it into a chip
More informationDigital Logic Design ENEE x. Lecture 19
Digital Logic Design ENEE 244-010x Lecture 19 Announcements Homework 8 due on Monday, 11/23. Agenda Last time: Timing Considerations (6.3) Master-Slave Flip-Flops (6.4) This time: Edge-Triggered Flip-Flops
More informationMUHAMMAD NAEEM LATIF MCS 3 RD SEMESTER KHANEWAL
1. A stage in a shift register consists of (a) a latch (b) a flip-flop (c) a byte of storage (d) from bits of storage 2. To serially shift a byte of data into a shift register, there must be (a) one click
More informationDigital Logic Design Sequential Circuits. Dr. Basem ElHalawany
Digital Logic Design Sequential Circuits Dr. Basem ElHalawany Combinational vs Sequential inputs X Combinational Circuits outputs Z A combinational circuit: At any time, outputs depends only on inputs
More informationSolution to Digital Logic )What is the magnitude comparator? Design a logic circuit for 4 bit magnitude comparator and explain it,
Solution to Digital Logic -2067 Solution to digital logic 2067 1.)What is the magnitude comparator? Design a logic circuit for 4 bit magnitude comparator and explain it, A Magnitude comparator is a combinational
More informationAC103/AT103 ANALOG & DIGITAL ELECTRONICS JUN 2015
Q.2 a. Draw and explain the V-I characteristics (forward and reverse biasing) of a pn junction. (8) Please refer Page No 14-17 I.J.Nagrath Electronic Devices and Circuits 5th Edition. b. Draw and explain
More informationSEQUENTIAL LOGIC. Satish Chandra Assistant Professor Department of Physics P P N College, Kanpur
SEQUENTIAL LOGIC Satish Chandra Assistant Professor Department of Physics P P N College, Kanpur www.satish0402.weebly.com OSCILLATORS Oscillators is an amplifier which derives its input from output. Oscillators
More informationBachelor Level/ First Year/ Second Semester/ Science Full Marks: 60 Computer Science and Information Technology (CSc. 151) Pass Marks: 24
2065 Computer Science and Information Technology (CSc. 151) Pass Marks: 24 Time: 3 hours. Candidates are required to give their answers in their own words as for as practicable. Attempt any TWO questions:
More informationSequential Digital Design. Laboratory Manual. Experiment #7. Counters
The Islamic University of Gaza Engineering Faculty Department of Computer Engineering Spring 2018 ECOM 2022 Khaleel I. Shaheen Sequential Digital Design Laboratory Manual Experiment #7 Counters Objectives
More informationFlip-Flops and Sequential Circuit Design
Flip-Flops and Sequential Circuit Design ECE 52 Summer 29 Reading ssignment Brown and Vranesic 7 Flip-Flops, Registers, Counters and a Simple Processor 7.5 T Flip-Flop 7.5. Configurable Flip-Flops 7.6
More informationCprE 281: Digital Logic
CprE 28: Digital Logic Instructor: Alexander Stoytchev http://www.ece.iastate.edu/~alexs/classes/ Registers and Counters CprE 28: Digital Logic Iowa State University, Ames, IA Copyright Alexander Stoytchev
More informationLecture 11: Synchronous Sequential Logic
Lecture 11: Synchronous Sequential Logic Syed M. Mahmud, Ph.D ECE Department Wayne State University Aby K George, ECE Department, Wayne State University Contents Characteristic equations Analysis of clocked
More informationCounters
Counters A counter is the most versatile and useful subsystems in the digital system. A counter driven by a clock can be used to count the number of clock cycles. Since clock pulses occur at known intervals,
More information1. a) For the circuit shown in figure 1.1, draw a truth table showing the output Q for all combinations of inputs A, B and C. [4] Figure 1.
[Question 1 is compulsory] 1. a) For the circuit shown in figure 1.1, draw a truth table showing the output Q for all combinations of inputs A, B and C. Figure 1.1 b) Minimize the following Boolean functions:
More informationDIGITAL CIRCUIT COMBINATORIAL LOGIC
DIGITAL CIRCUIT COMBINATORIAL LOGIC Logic levels: one zero true false high low CMOS logic levels: 1 => 0.7 V DD 0.4 V DD = noise margin 0 =< 0.3 V DD Positive logic: high = 1 = true low = 0 = false Negative
More informationVignana Bharathi Institute of Technology UNIT 4 DLD
DLD UNIT IV Synchronous Sequential Circuits, Latches, Flip-flops, analysis of clocked sequential circuits, Registers, Shift registers, Ripple counters, Synchronous counters, other counters. Asynchronous
More informationMultiplexor (aka MUX) An example, yet VERY useful circuit!
Multiplexor (aka MUX) An example, yet VERY useful circuit! A B 0 1 Y S A B Y 0 0 x 0 0 1 x 1 1 x 0 0 1 x 1 1 S=1 S=0 Y = (S)? B:A; Y=S A+SB when S = 0: output A 1: output B 56 A 32-bit MUX Use 32 1-bit
More informationDEPARTMENT OF COMPUTER SCIENCE & ENGINEERING
DRONACHARYA GROUP OF INSTITUTIONS, GREATER NOIDA Affiliated to Mahamaya Technical University, Noida Approved by AICTE DEPARTMENT OF COMPUTER SCIENCE & ENGINEERING Lab Manual for Computer Organization Lab
More informationDigital Circuits I and II Nov. 17, 1999
Physics 623 Digital Circuits I and II Nov. 17, 1999 Digital Circuits I 1 Purpose To introduce the basic principles of digital circuitry. To understand the small signal response of various gates and circuits
More informationMODULE 3. Combinational & Sequential logic
MODULE 3 Combinational & Sequential logic Combinational Logic Introduction Logic circuit may be classified into two categories. Combinational logic circuits 2. Sequential logic circuits A combinational
More informationLogic Design Viva Question Bank Compiled By Channveer Patil
Logic Design Viva Question Bank Compiled By Channveer Patil Title of the Practical: Verify the truth table of logic gates AND, OR, NOT, NAND and NOR gates/ Design Basic Gates Using NAND/NOR gates. Q.1
More informationRegister Transfer Level in Verilog: Part II
Source: M. Morris Mano and Michael D. Ciletti, Digital Design, 4rd Edition, 2007, Prentice Hall. Register Transfer Level in Verilog: Part II Lan-Da Van ( 范倫達 ), Ph. D. Department of Computer Science National
More informationVTU NOTES QUESTION PAPERS NEWS RESULTS FORUMS Registers
Registers Registers are a very important digital building block. A data register is used to store binary information appearing at the output of an encoding matrix.shift registers are a type of sequential
More informationDIGITAL SYSTEM FUNDAMENTALS (ECE421) DIGITAL ELECTRONICS FUNDAMENTAL (ECE422) LATCHES and FLIP-FLOPS
COURSE / CODE DIGITAL SYSTEM FUNDAMENTALS (ECE421) DIGITAL ELECTRONICS FUNDAMENTAL (ECE422) LATCHES and FLIP-FLOPS In the same way that logic gates are the building blocks of combinatorial circuits, latches
More informationScanned by CamScanner
NAVEEN RAJA VELCHURI DSD & Digital IC Applications Example: 2-bit asynchronous up counter: The 2-bit Asynchronous counter requires two flip-flops. Both flip-flop inputs are connected to logic 1, and initially
More informationSequential Digital Design. Laboratory Manual. Experiment #3. Flip Flop Storage Elements
The Islamic University of Gaza Engineering Faculty Department of Computer Engineering Spring 2018 ECOM 2022 Khaleel I. Shaheen Sequential Digital Design Laboratory Manual Experiment #3 Flip Flop Storage
More informationDigital Systems Laboratory 3 Counters & Registers Time 4 hours
Digital Systems Laboratory 3 Counters & Registers Time 4 hours Aim: To investigate the counters and registers constructed from flip-flops. Introduction: In the previous module, you have learnt D, S-R,
More informationChapter 6 Digital Circuit 6-5 Department of Mechanical Engineering
MEMS1082 Chapter 6 Digital Circuit 6-5 General digital system D Flip-Flops, The D flip-flop is a modification of the clocked SR flip-flop. The D input goes directly into the S input and the complement
More informationMC9211 Computer Organization
MC9211 Computer Organization Unit 2 : Combinational and Sequential Circuits Lesson2 : Sequential Circuits (KSB) (MCA) (2009-12/ODD) (2009-10/1 A&B) Coverage Lesson2 Outlines the formal procedures for the
More informationQuestion Bank. Unit 1. Digital Principles, Digital Logic
Question Bank Unit 1 Digital Principles, Digital Logic 1. Using Karnaugh Map,simplify the following boolean expression and give the implementation of the same using i)nand gates only(sop) ii) NOR gates
More informationChapter 2. Digital Circuits
Chapter 2. Digital Circuits Logic gates Flip-flops FF registers IC registers Data bus Encoders/Decoders Multiplexers Troubleshooting digital circuits Most contents of this chapter were covered in 88-217
More informationIntroduction to Sequential Circuits
Introduction to Sequential Circuits COE 202 Digital Logic Design Dr. Muhamed Mudawar King Fahd University of Petroleum and Minerals Presentation Outline Introduction to Sequential Circuits Synchronous
More informationExperiment # 9. Clock generator circuits & Counters. Digital Design LAB
Digital Design LAB Islamic University Gaza Engineering Faculty Department of Computer Engineering Fall 2012 ECOM 2112: Digital Design LAB Eng: Ahmed M. Ayash Experiment # 9 Clock generator circuits & Counters
More informationMore on Flip-Flops Digital Design and Computer Architecture: ARM Edition 2015 Chapter 3 <98> 98
More on Flip-Flops Digital Design and Computer Architecture: ARM Edition 2015 Chapter 3 98 Review: Bit Storage SR latch S (set) Q R (reset) Level-sensitive SR latch S S1 C R R1 Q D C S R D latch Q
More informationEKT 121/4 ELEKTRONIK DIGIT 1
EKT 2/4 ELEKTRONIK DIGIT Kolej Universiti Kejuruteraan Utara Malaysia Sequential Logic Circuits - COUNTERS - LATCHES (review) S-R R Latch S-R R Latch Active-LOW input INPUTS OUTPUTS S R Q Q COMMENTS Q
More informationCHAPTER1: Digital Logic Circuits
CS224: Computer Organization S.KHABET CHAPTER1: Digital Logic Circuits 1 Sequential Circuits Introduction Composed of a combinational circuit to which the memory elements are connected to form a feedback
More informationUnit 11. Latches and Flip-Flops
Unit 11 Latches and Flip-Flops 1 Combinational Circuits A combinational circuit consists of logic gates whose outputs, at any time, are determined by combining the values of the inputs. For n input variables,
More informationEECS 270 Midterm Exam Spring 2011
EES 270 Midterm Exam Spring 2011 Name: unique name: Sign the honor code: I have neither given nor received aid on this exam nor observed anyone else doing so. Scores: Page # Points 2 /15 3 /10 4 /6 5 /12
More information