Engr354: Digital Logic Circuits

Transcription

1 Engr354: igital Circuits Chapter 7 Sequential Elements r. Curtis Nelson Sequential Elements In this chapter you will learn about: circuits that can store information; Basic cells, latches, and flip-flops; State diagrams; esign techniques for circuits that use flip-flops. Engr354 - Chapter 7, Brown 1

2 Circuit Types Combinational output depends only on the input. Sequential output depends on input and past behavior: Requires use of storage elements; Contents of the storage elements is called state; Circuit goes through a sequence of states as a result of changes in inputs. Synchronous controlled by a clock. Clock Signals Engr354 - Chapter 7, Brown 2

3 A Bistable Memory Element Bistable possessing two stable states. A B A / (SR) Memory Element Called a Basic Cell; NOR centered Basic Cell: Circuit (a), Function table (b). are active when they are high; Blocking side inputs. Engr354 - Chapter 7, Brown 3

4 Typical Operation of a Basic Cell, clear., preset. NOR-Centered ( ominant) Basic Cell r + s Action n+1 hold n 1 reset 1 set reset Operation Table Circuit n n+1 1 f f 1 1 f 1 f r sr 1 r State iagram Engr354 - Chapter 7, Brown 4

5 NAN-Centered ( ominant) Basic Cell are active low (when they are asserted); Operation table indicates assertion, not voltage, levels. s Action N+1 hold N 1 reset 1 set set 1 Operation Table Circuit n n+1 1 f 1 f 1 1 f f rs 1 s + r State iagram s Combined Form of the Basic Cell n n+1 1 f 1 f 1 1 f f NAN-centered n n+1 n n+1 1 f f 1 1 f 1 f NOR-centered 1 f 1 1 f Combined Form Basic Cell Engr354 - Chapter 7, Brown 5

6 esigning Latches - A Model Latch - a logic circuit that transfers the input state to the output state when the clock signal is high and latches and holds the input when the clock signal goes low. n n+1 1 f 1 1 f Combined Form Clock S R Basic Cell (H) (L) esign of a Clocked (ata) Latch Clock S R Basic Cell (H) (L) Engr354 - Chapter 7, Brown 6

7 esign of a Clocked Latch (H) Clk Clk Action N+1 x Block iagram hold N reset set 1 Operation Table n n+1 1 f 1 1 f Basic Cell Clk n n+1 f 1 1 f 1 f f 1 f f Truth Table = clk = clk Equations CLK +CLK 1 +CLK CLK State iagram Clocked Latch Engr354 - Chapter 7, Brown 7

8 esign of a Clocked Toggle (T) Latch (H) T Clk Clk T Action N+1 x Hold N 1 Hold N 1 1 Toggle N Function Table Block iagram n n+1 1 f 1 1 f Basic Cell Clk T n n+1 f 1 1 f 1 f f 1 f f Truth Table = clk T = clk T Equations T CLK T +CLK 1 T +CLK T CLK State iagram esign of a Clocked JK Latch (H) J K Clk Clk J K Action N+1 x x Hold N 1 Hold N Toggle N Function Table Block iagram n n+1 1 f 1 1 f Basic Cell = clk J = clk K Equations Clk J K n n+1 f 1 1 f 1 f f 1 f f 1 1 f f 1 f f 1 1 f f Truth Table Engr354 - Chapter 7, Brown 8

9 esign of a -ominant Clocked SR Latch S R Clock S R Basic Cell (H) (L) S, R, Clock, Outputs, esign of a -ominant Clocked SR Latch (H) S R Clk Action N hold N reset set 1 set 1 Operation Table Block iagram n n+1 1 f 1 1 f Basic Cell = clk S = clk R S Equations Clk n n+1 f 1 1 f 1 f f 1 f f 1 1 f f 1 f f 1 1 f f f Truth Table Engr354 - Chapter 7, Brown 9

10 SR Latch with Enable (Clock) esign of a Clocked JK Latch Version II Replace the basic cell with a -latch as the memory element. J K Clk -Latch (H) (L) J, K, Clk, Output Engr354 - Chapter 7, Brown 1

11 esign of a Clocked JK Latch Version II (H) J K Clk Clk J K Action N+1 x x Hold N 1 Hold N Toggle N Function Table Block iagram n n Truth Table = K + clk + clk J Equation Clk J K n n Terminology Latches are often called Transparent because the output will follow the input as long as the clock signal is high. Flip-flops are edge-triggered: Positive-edge triggered (PET) is when action occurs on the rising edge of the clock signal; Negative-edge triggered (NET) is when action occurs on the falling edge of the clock signal. Types of Flip-flops: SR (rarely used); (very, very common, 74HC74); JK (hardly ever used, 74HC19); Toggle (occasionally used by CA programs). Engr354 - Chapter 7, Brown 11

12 up and Hold Times up time (t SU ) is the time interval preceding the active transition point of the CLK during which all data inputs must remain stable. Hold time (t H ) is the time interval following the active transition point of the CLK during which all data inputs must remain stable. See data sheet for 74HC74 t su t h Clk PET Master-Slave Flip-Flop M follows the input whenever CLK is low. When CLK goes high, M is transferred to the output. Engr354 - Chapter 7, Brown 12

13 Positive-Edge-Triggered Flip-Flop PET Flip-Flop with Clear and Preset Synchronous transitions or actions occur in relation to the CLK signal; Asynchronous transitions or actions are not related to the CLK signal. Engr354 - Chapter 7, Brown 13

14 Level-Sensitive vs. Edge-Triggered Level-sensitive = latch Edge-triggered = flip-flop a Clock Clk a b Clock b a c b c c (a) Circuit (b) Timing diagram esign a T Flip-Flop from a Flip-Flop The memory element is now edge-triggered meaning the Clk signal is no longer part of the next-state logic. T flip-flop (H) (L) Clk T 1 ( n + 1 ) ( n ) ( n ) Function Table n n T n n Truth Table Engr354 - Chapter 7, Brown 14

15 esign a T Flip-Flop from a Flip-Flop T Clock (a) Circuit T (c) Graphical symbol esign a JK Flip-Flop from a Flip-Flop J K Clock J K ( n+ 1) 1 ( n) ( n) Function Table Circuit J K Graphical symbol Engr354 - Chapter 7, Brown 15

16 Summary of Terminology Basic cell cross-coupled NAN/NOR. Gated latch output changes only when Clk is asserted: Gated SR latch; Gated latch; Gated JK latch. Flip-flop output changes only on Clk edge: Master-slave; Edge-triggered; Three main types: (very, very common, 74HC74); JK (hardly ever used, 74HC19); Toggle (occasionally used by CA programs). Sequential Elements Summary In this chapter you learned about: circuits that can store information; Basic cells, latches, and flip-flops; State diagrams; esign techniques for circuits that use flip-flops. Engr354 - Chapter 7, Brown 16