CH 11 Latches and Flip-Flops

Transcription

1 CH Latches and Flip-Flops Flops Lecturer : 吳安宇 Date : Ver.. ACCESS IC LAB

2 v. Introduction v.2 Set-Reset Latch v.3 Gated D Latch Outline v.4 Edge-Triggered D Flip-Flop v.5 S-R Flip-Flop v.6 J-K Flip-Flop v.7 T Flip-Flop v.8 Flip-Flops with Additional Inputs v.9 Summary pp. 2

3 Introduction vcombinational Circuits (without memory) A B C F(A,B,C) F(A,B,C) vsequential Circuit (with memory) A B C D(n-) f MEM f(n) D(n) pp. 3

4 Latch: Basic memory unit (store bit) v Fundamentals : pp. 4

5 v. Introduction v.2 Set-Reset Latch v.3 Gated D Latch Outline v.4 Edge-Triggered D Flip-Flop v.5 S-R Flip-Flop v.6 J-K Flip-Flop v.7 T Flip-Flop v.8 Flip-Flops with Additional Inputs v.9 Summary pp. 5

6 Set-Reset Latch (SR-latch)(/2) (stable) ( ) (set) (stable) ( ) (Reset) pp. 6

7 Set-Reset Latch (SR-latch)(2/2) v Cross-Couple Form R : Reset S : Set v S-R-(Unstable Net allowed) S P R pp. 7

8 Representation Format (a) Timing diagram (b) Truth Table S(t) R(t) (t) (t-e) - - unchanged Reset to Set to Inputs not allowed (c) Next-state Equation or characteristic Equations R(t) (t) S(t) X (tε) S(t) R (t)(t) SR Under SR (S,R not allowed) x pp. 8

9 Applications- Debouncing scheme Note : work with a double throw switch that switch between two contacts. pp. 9

10 SR Latch (NAND gate based) S (t) R (t) (t) (t) - - unchanged Reset to Set to Inputs not allowed Active-low inputs for S & R pp.

11 v. Introduction v.2 Set-Reset Latch v.3 Gated D Latch Outline v.4 Edge-Triggered D Flip-Flop v.5 S-R Flip-Flop v.6 J-K Flip-Flop v.7 T Flip-Flop v.8 Flip-Flops with Additional Inputs v.9 Summary pp.

12 Gated D Latch Figure - Gated D Latch Figure -2 Symbol and Truth Table for Gated Latch G D unchanged D GD G GD pp. 2

13 v. Introduction v.2 Set-Reset Latch v.3 Gated D Latch Outline v.4 Edge-Triggered D Flip-Flop v.5 S-R Flip-Flop v.6 J-K Flip-Flop v.7 T Flip-Flop v.8 Flip-Flops with Additional Inputs v.9 Summary pp. 3

14 Edge-triggered D Flip-Flop Flop Positive (Rising edge) trigger Negative (Falling edge) trigger to align with clock edges D D Figure -4 Timing for D Flip-Flop (Falling-Edge Trigger) pp. 4

15 D F/F (Rising-edge trigger) pp. 5

16 v. Introduction v.2 Set-Reset Latch v.3 Gated D Latch Outline v.4 Edge-Triggered D Flip-Flop v.5 S-R Flip-Flop v.6 J-K Flip-Flop v.7 T Flip-Flop v.8 Flip-Flops with Additional Inputs v.9 Summary pp. 6

17 S-R R Flip-Flop Flop with clock input changes at clock edges S R change no state SR P Half clock cycle S, R set to (after active Ck edge) S, R reset to (after active Ck edge) S R not allowed pp. 7

18 v. Introduction v.2 Set-Reset Latch v.3 Gated D Latch Outline v.4 Edge-Triggered D Flip-Flop v.5 S-R Flip-Flop v.6 J-K Flip-Flop v.7 T Flip-Flop v.8 Flip-Flops with Additional Inputs v.9 Summary pp. 8

19 J-K K Flip-Flop Flop (extension of SR F/F) J S (Jump to ) K R (clear to ) J K, Toggle J K J K unchanged clear to Jump to Toggle pp. 9

20 v. Introduction v.2 Set-Reset Latch v.3 Gated D Latch Outline v.4 Edge-Triggered D Flip-Flop v.5 S-R Flip-Flop v.6 J-K Flip-Flop v.7 T Flip-Flop v.8 Flip-Flops with Additional Inputs v.9 Summary pp. 2

21 T Flip-Flop Flop T T T T,,, Toggle, unchange T Unchanged Toggle T' T' T pp. 2

22 Implementation (A) JK F/F Based: ( J K T ) (B) D F/F Based D input T J' K' T' T' ' T T' T' pp. 22

23 v. Introduction v.2 Set-Reset Latch v.3 Gated D Latch Outline v.4 Edge-Triggered D Flip-Flop v.5 S-R Flip-Flop v.6 J-K Flip-Flop v.7 T Flip-Flop v.8 Flip-Flops with Additional Inputs v.9 Summary pp. 23

24 F/F with additional inputs Ck D PreN ClrN x x x x x x, x (not allowed) (no change) Keep whole cycle pp. 24

25 D Flip-Flop Flop with Clock Enable (CE) CE for Fig.-27(c): D ( CE)' Din( CE) pp. 25

26 v. Introduction v.2 Set-Reset Latch v.3 Gated D Latch Outline v.4 Edge-Triggered D Flip-Flop v.5 S-R Flip-Flop v.6 J-K Flip-Flop v.7 T Flip-Flop v.8 Flip-Flops with Additional Inputs v.9 Summary pp. 26

27 Summary Characteristic Equations of flip-flops (Eq.): S R' ( SR ) (S-R latch or flip-flop) GD G' (gated D latch) D (D flip-flop) D CE CE' (D-CE flip-flop) J' K' (J-K flip-flop) T T' T ' (T flip-flop) pp. 27