Part 4: Introduction to Sequential Logic. Basic Sequential structure. Positive-edge-triggered D flip-flop. Flip-flops classified by inputs

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1 Part 4: Introduction to Sequential Logic Basic Sequential structure There are two kinds of components in a sequential circuit: () combinational blocks (2) storage elements Combinational blocks provide current inputs to the storage elements and output logic. Storage elements act as memory cells that keep bit information. The memory cells are implemented by Flip- Flops (FFs). There are many varieties of FFs. 3/3/26 3/3/26 2 Flip-flops classified by inputs Positive-edge-triggered flip-flop flip-flop is a memory element capable of storing one logical variable (one bit). Flip-flops come in many flavours, including (for elay or ata), RS (Reset/Set), T (Toggle) and JK (a weird combination of RS and T ). These letters are the names of the inputs; e.g. a flip-flop has one input called, while a JK type has two inputs called J and K. The most widely used flip-flops are the type (because it s simple) and the JK type (because it allows many don t-cares in the supporting combinational logic). It s high time we described a particular flip-flop in detail. flip-flop has (at least) a data input, a clock input, and an output. In addition, the complemented output is often available. The clock input is marked by the arrow or triangle on the circuit symbol [right]. The absence of an inversion bubble indicates positive clocking - positive edge triggering in this case. Let n denote the output up to and during the next clock edge, and n+ the output after the next clock edge. In this notation, the truth table of the flip-flop is n n+ Input Clock Output (Output) 3/3/26 3 3/3/26 4

2 flip-flop: setup and hold times Note the simplicity of the truth table: on the rising edge of the clock, the input is simply copied to the output. The new output n+ does not even depend on the current output n. So the use of this flip-flop is conceptually simple. Unfortunately the edgetriggering is not quite perfect. To guarantee that the correct value of is to be copied to, we must hold constant for a certain time before the clock edge (the setup time t su ) and for a certain time thereafter (the hold time t h ). must not change. Clock (voltage vs. time) 3/3/26 5 t su t h flip-flop: internal circuit * The logic diagram [right] shows one way to construct a positive-edgetriggered flip-flop out of gates - in this case, all NN gates. 3/3/ SR Flip FLop JK Flip FLop Symbol R S Symbol J K State table R S (n+) State table K J (n+) Timing diagram (n)? Timing diagram (n) (n) R K S J 3/3/26 7 3/3/26 8

3 T Flip FLop Symbol State table Timing diagram T T (n+) (n) (n) Common building blocks There are some sequential circuits that are widely used in many more complicated system such as in computer systems. They are largely regarded as the building blocks in the digital system design. We will study some of them. T 3/3/26 9 3/3/26 Simple n-bit memory register Register with load-enable () The simplest type of n-bit register is just an array of n -type flip-flops with a common clock input. The diagram shows the case n = 4. The 4-bit input I 3 I 2 I I is loaded (copied to the output 3 2 ) on the rising clock edge, and that output is held until the next clock edge. I 3 3 I 2 2 I I The diagram shows one bit of a register with a load-enable input. On the clock edge, the flip-flop loads the input I only if the loadenable input E is true; otherwise it holds (or, more precisely, reloads) its present output. The logic gates determine whether I or is presented to the flip-flop s input: From the diagram, = E + EI. So if E =, = ; but if E =, = I. I E 3/3/26 3/3/26 2

4 Register with load-enable (2) On the previous slide, the gates form a 2: MUX of which the select input is E, input is, input is I, and the output Z feeds the flip-flop input. So the register may be redrawn as shown here (two bits are shown this time). E and are common to all the bits of the register. Z I 3/3/26 3 E Z I 2 2 SIPO shift register () Serial-In Parallel-Out (SIPO) shift register is a cascade of flip-flops. On the clock edge, the output of each flipflop is passed to the next flip-flop in the chain. The input signal is fed serially (one bit at a time) into the first flipflop in the chain. The flip-flop outputs are available in parallel (all at once). Such a device may be used to receive multi-bit words transmitted over a serial line. Input 3/3/ SIPO shift register (2) The operation of the shift register may be described using a Pascal-like notation. On each clock edge, the following assignments take place: := Input ; := ; 2 := ; 3 := 2 ; etc. is a delayed version of ; 2 is a delayed version of, and so on; the delay in each case is one clock period. In general, k is the value that held k clock cycles ago. So the register may be used as a delay line for digital signal processing (e.g. the output filter of a C player). SIPO shift register (3) * If a flip-flop is to work correctly in a shift register, the propagation delay t p must be longer than the hold time t h, so that the input of the next flip-flop does not change until after the hold time has expired. properly designed flip-flop meets this condition. Otherwise the data might be shifted through two flip-flops at once ( might be copied straight to 2 ), or the shifting might be inconsistent. Input t p t h INPUTS STEY 3/3/26 5 3/3/26 6

5 PISO shift register Parallel-In Serial-Out (PISO) shift register is useful for transmitting multi-bit words over a serial line. Two bits are shown here. If Load = on the rising clock edge, the flip-flops read the inputs I, I 2, etc. in parallel. If Load = on the rising clock edge, each flip-flop reads the output of the one above. Thus the loaded value can be shifted downward one bit at a time. Load Z I Z I 2 3/3/ bit Moebius counter () 3-bit Moebius counter or twisted-tail counter comprises three flip-flops connected in a loop. One of the connections uses the inverted output; the others use the true outputs. On the rising edge of the clock, the old is copied to B, the old B is copied to C, and the old C is copied to. B C 3/3/26 8 Twisted-tail connection 3-bit Moebius counter (2) From the verbal description of the operation, we can draw up the following state sequences and timing diagram: B C B C Timing diagram (first sequence): (again) : : B: C: The longer sequence produces a three-phase signal at one third of the clock frequency. This is useful, e.g. in analog modulators. 3/3/26 9 Hang-up states So a 3-bit Moebius counter can give a 6-state cycle, which we want, or a 2-state cycle, which we don t want. Together, the two cycles contain all 8 possible states. If the counter somehow gets into one of the two unwanted states (e.g. because of power fluctuations or interference), it will stay in the unwanted cycle indefinitely. Unwanted states that form a closed cycle are called hang-up states. Let us modify the circuit to ensure that all unwanted states eventually lead back into the wanted cycle. circuit that behaves this way is described as self-clearing. 3/3/26 2

6 f-clearing 3-bit Moebius counter The only two states for which C is true are the wanted state, whose successor is, and the unwanted state, whose successor is. So if the transition C := B is modified so that it becomes C := B + C, the only change will be that leads to instead of. The modified circuit is B C 3/3/26 2 C B B+C State diagrams The state sequence of the self-clearing 3-bit Moebius counter is shown on the left. If we number the states by the binary number 2, represent each state by a numbered square, and show state transitions by arrows, we obtain the state diagram on the right. Note that the unwanted sequence (red lines) leads back to the wanted sequence (black lines) /3/26 22 esigning from a state diagram () Let us now design the same circuit more rigorously, using the state diagram as the specification. The state diagram [right] leads to the truth table [left], in which the three columns, B and C show the required inputs to the flip-flops; these values will appear at the outputs, B and C on the next clock edge. State B C /3/26 23 esigning from a state diagram (2) Now we find the inputs as functions of,b,c. From the truth table, = Σm(,2,4,6) ; B = Σm(4,5,6,7) ; C = Σm(2,3,5,6,7). s usual, we simplify these functions using K-maps: B : : C : Thus we obtain = C, B =, and C = B+C, as on slide 3. 3/3/26 24

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