Allegro PCB SI SigXplorer L Series Tutorial. Product Version 16.0 June 2007

Transcription

1 Product Version 16.0 June 2007

2 Cadence Design Systems, Inc. All rights reserved. Portions Apache Software Foundation, Sun Microsystems, Free Software Foundation, Inc., Regents of the University of California, Massachusetts Institute of Technology, University of Florida. Used by permission. Printed in the United States of America. Cadence Design Systems, Inc. (Cadence), 2655 Seely Ave., San Jose, CA 95134, USA. Allegro PCB SI SigXplorer contains technology licensed from, and copyrighted by: Apache Software Foundation, 1901 Munsey Drive Forest Hill, MD 21050, USA , Apache Software Foundation. Sun Microsystems, 4150 Network Circle, Santa Clara, CA USA , Sun Microsystems, Inc. Free Software Foundation, 59 Temple Place, Suite 330, Boston, MA USA 1989, 1991, Free Software Foundation, Inc. Regents of the University of California, Sun Microsystems, Inc., Scriptics Corporation, 2001, Regents of the University of California. Daniel Stenberg, , Daniel Stenberg. UMFPACK 2005, Timothy A. Davis, University of Florida, Ken Martin, Will Schroeder, Bill Lorensen , Ken Martin, Will Schroeder, Bill Lorensen. Massachusetts Institute of Technology, 77 Massachusetts Avenue, Cambridge, Massachusetts, USA 2003, the Board of Trustees of Massachusetts Institute of Technology. All rights reserved. Trademarks: Trademarks and service marks of Cadence Design Systems, Inc. contained in this document are attributed to Cadence with the appropriate symbol. For queries regarding Cadence s trademarks, contact the corporate legal department at the address shown above or call Open SystemC, Open SystemC Initiative, OSCI, SystemC, and SystemC Initiative are trademarks or registered trademarks of Open SystemC Initiative, Inc. in the United States and other countries and are used with permission. All other trademarks are the property of their respective holders. Restricted Permission: This publication is protected by copyright law and international treaties and contains trade secrets and proprietary information owned by Cadence. Unauthorized reproduction or distribution of this publication, or any portion of it, may result in civil and criminal penalties. Except as specified in this permission statement, this publication may not be copied, reproduced, modified, published, uploaded, posted, transmitted, or distributed in any way, without prior written permission from Cadence. Unless otherwise agreed to by Cadence in writing, this statement grants Cadence customers permission to print one (1) hard copy of this publication subject to the following conditions: 1. The publication may be used only in accordance with a written agreement between Cadence and its customer. 2. The publication may not be modified in any way. 3. Any authorized copy of the publication or portion thereof must include all original copyright, trademark, and other proprietary notices and this permission statement. 4. The information contained in this document cannot be used in the development of like products or software, whether for internal or external use, and shall not be used for the benefit of any other party, whether or not for consideration. Patents: Allegro PCB SI SigXplorer, described in this document, is protected by U.S. Patents 5,481,695; 5,510,998; 5,550,748; 5,590,049; 5,625,565; 5,715,408; 6,516,447; 6,594,799; 6,851,094; 7,017,137; 7,143,341; 7,168,041. Disclaimer: Information in this publication is subject to change without notice and does not represent a commitment on the part of Cadence. Except as may be explicitly set forth in such agreement, Cadence does not make, and expressly disclaims, any representations or warranties as to the completeness, accuracy or usefulness of the information contained in this document. Cadence does not warrant that use of such information will not infringe any third party rights, nor does Cadence assume any liability for damages or costs of any kind that may result from use of such information. Restricted Rights: Use, duplication, or disclosure by the Government is subject to restrictions as set forth in FAR and DFAR et seq. or its successor.

3 Contents Lesson Read This First! Objectives About Online Documentation Working with Database Files Board databases used in this tutorial Starting the Tutorial Controlling your View of the design Save the Design To Summarize What You Have Learned Lesson Objectives Working with a Single Net Extracting a Net Topology To Summarize What You Have Learned Lesson Objectives Extracting a Net Topology Exploring the Circuit Topology Examine the circuit parameters Examine the IOCell models Setting Up for Simulation Specifying Stimulus Specifying Reflection Measurements Simulation and Analysis Taking a closer look Finishing Up June Product Version 16.0

4 To Summarize What You Have Learned Lesson Revising the Board Layout Moving the clock driver Swapping Components Simulation and Analysis Making Signal-to-Signal Comparisons Finishing Up To Summarize What You Have Learned Lesson Routing the Clock Driver Net Exploring the Extracted Circuit Topology Simulation and Analysis Finishing Up To Summarize What You Have Learned June Product Version 16.0

5 Lesson 1 Read This First! This tutorial is designed to familiarize you with basic functions in SigXplorer PCB SI series L. It is intended for users licensed to run series L Allegro products. If you or your company hold licenses for product tiers L and higher, perform the following steps prior to doing the tutorial: 1. In Allegro PCB Design L, select Setup User Preferences. 2. In the User Preferences Editor, select Signal_analysis from the Categories list. 3. Enter SELECT in the Value field. 4. Click OK to save the envoronment variable setting and close the form. This will allow you to select SigXplorer PCB SI L from the list of product tiers that you have a license to run when you launch SigXplorer from Allegro PCB Design L. This tutorial describes a flow from Allegro PCB Design L to Allegro PCB SI SigXplorer L. The tutorial begins from Allegro PCB Design L. Objectives In this lesson, you learn: What comprises the SigXplorer information set The board database files that are used in this tutorial How to start the tutorial from the PCB Design How to change your view of the board in the PCB Design June Product Version 16.0

6 Lesson 1 About Online Documentation The SigXplorer documentation set consists of online help and an online books. All documentation is accessible from the SigXplorer help menu. Refer to... Getting Started with Allegro PCB SI SigXplorer L Series Allegro PCB SI SigXplorer L Series Tutorial (this book) Allegro PCB SI SigXplorer User Guide and Allegro PCB SI SigXplorer Command Reference for this level of information This book is for users who know how to use PCB Design but are new to the signal integrity field. A basic introduction to the major features of SigXplorer including net extraction, reflection simulation, and analysis. This book complements Getting Started by guiding you through a series of exercises that lead to optimized placement based on signal exploration and analysis. Online documentation provides a more in-depth look at SigXplorer and signal integrity concepts. June Product Version 16.0

7 Lesson 1 Working with Database Files The SigXplorer tutorial uses five board database files for use in each successive lesson. The prerequisite section of each lesson informs you which board file to use. To start the tutorial, you should first make a writable folder (a working directory) on your hard drive. You should copy the board (.brd) files, and the devices.dml file, from the product CD (or from your network) to this local, working directory on your hard drive. The board files for the tutorial are on the product CD at the following location in your installation heirarchy. <install_dir>\doc\assetut\goldenboards We suggest that you complete each lesson in sequence. In this way, the state of the board file at the end of one lesson can be used as the starting point for the next lesson. You can, though, take a lesson out of sequence by loading the appropriate board file for that lesson. See Board databases used in this tutorial on page 8. Important You can also complete this tutorial by copying and renaming tutboard1.brd to any file name that you like: perhaps myboard1.brd. As you progress through each lesson, you would then save the board in succession (myboard2.brd,...) and use it to start the next lesson. In this way, your results are based on the placement decisions that you make; therefore, they may differ slightly with those in the text. This approach also promotes a feeling of continuity in the tutorial. June Product Version 16.0

8 Lesson 1 Board databases used in this tutorial Lesson/ Board File Lesson 1 tutboard1.brd Design State Board database contains netlist Board shows full ratsnest display Lesson 2 tutboard2.brd Clock net (cclock) in the PCB Design is not extractable for topology exploration and analysis in SigXplorer. Board shows full ratsnest display Lesson 3 tutboard3.brd Board shows full ratsnest display off (blank); cclock visible Clock net (cclock) is now extractable for topology exploration and analysis Lesson 4 tutboard4.brd Lesson 5 tutboard5.brd Critical high-speed components are not optimally placed resulting in excessive length of the clock driver signal that feed these components Clock driver, U9, is relocated to a central location among the components that it drives The clock net, cclock, is reduced in length from swapping component U93 with U70 and U85 with U16 Note: Although the design databases tutboard1.brd and tutboard2.brd are identical, as are tutboard3.brd and tutboard4.brd,we ve supplied each to maintain continuity between the board number and the lesson number. Also, to end this tutorial, you can optionally save the clock net that you routed in Lesson 5, as myboard6.brd. In this way, you can archive the entire tutorial for later reference. June Product Version 16.0

9 Lesson 1 Starting the Tutorial Now that you have set up a working directory as described in Board databases used in this tutorial on page 8, you re ready to start the first lesson. The first lesson explains how to navigate within the PCB Design using zoom and pan commands. These principles hold true for moving around in SigXplorer and SigWave, which you are asked do in later lessons. To open the board database file in Allegro PCB Design L 1. From Allegro PCB Design L, choose File > Open. If a design is already open, you will be prompted to save it before continuing. The Open dialog box appears. 2. Click the change directory check box to ensure that your design is saved to the working directory that you set up. 3. Double-click tutboard1.brd. The board database is loaded into PCB Design with all ratsnest lines displayed. June Product Version 16.0

10 Lesson 1 Controlling your View of the design This section discusses zoom and pan commands. You use these commands to refocus your view of the board layout (in PCB Design), topology canvas or spreadsheet (in SigXplorer), or waveform display (in SigWave). These commands can be accessed from the View menu in PCB Design and SigXplorer, or from the Zoom menu in SigWave. You can also access each of these commands from icons in the tool bar This section is only for reference. You do not perform any exercises. There are many zoom commands; however, in this tutorial, we ll limit our discussion to In, Out, Points, Fit, and panning. This zoom command... Is used to... View Zoom In View Zoom Out View Zoom Points View Zoom Fit Display an enlarged view of the board, topology, or waveform. Display an reduced view of the board, topology, or waveform. Display an area of the board, topology, or waveform by selecting a starting and ending point. Click to anchor the starting point, drag across the area, and click to define the end point. The view now focuses around this area. Display the entire board, topology, or waveform. To roam the board or topology (panning) Hold down the middle mouse button and drag up, down, left, or right. June Product Version 16.0

11 Lesson 1 The following depicts zoom commands available from PCB Design. The equivalent menu commands from SigXplorer and SigWave are also shown. PCB Design SigXplorer SigWave Fit In Out To pan the drawing, hold down the middle mouse button and drag up, down, left, or right. Points June Product Version 16.0

12 Lesson 1 Save the Design You have not modified the board in this lesson, but to maintain continuity between the board number and the lesson number, if you are using your own board files choose File > Save As and specify myboard2.brd (or whatever naming convention you chose). Congratulations! You have completed Lesson 1. To Summarize What You Have Learned In this lesson, you learned: What is contained in the information set. About the board database files and their design state. How to use the zoom commands and the panning functionality. June Product Version 16.0

13 Lesson 2 Objectives In this lesson, you: Highlight a net in Allegro PCB Design L for extraction into SigXplorer. Become familiar with the Topology Template dialog box. Attempt to extract a net from Allegro PCB Design L for topology exploration in SigXplorer. Prepare a net for extraction by running the Database Setup Advisor. June Product Version 16.0

14 Lesson 2 Working with a Single Net High-speed considerations do not necessarily involve the entire design; rather, they may just involve the placement and routing, one-by-one, of only a few critical nets. In this tutorial, you will analyze the clock net cclock for optimum placement and routing. In this exercise, you will isolate the clock net so that it is easier to work with. You accomplish this in two steps. To begin this lesson, you should have tutboard2.brd open in Allegro PCB Design L. To hide all ratsnests From Allegro PCB Design L, choose Display Blank Rats All. Rats Visible Rats Hidden The drawing appears to be far less cluttered. To display a single ratsnest 1. From Allegro PCB Design L, choose Display Show Rats Net. June Product Version 16.0

15 Lesson 2 2. If it is not already open, position your cursor over the Find tab to display the Find Filter. (You can also open it from the View Windows Find menu selection.) Enter cclock here The Nets checkbox is active. 3. Enter cclock in the Find By Name field. 4. Press Return The ratsnest connections for cclock are now highlighted in your drawing. To obtain an unobstructed view of the cclock net: a. Hide all the ratnests in the design by selecting Display Blank Rats All. b. Display only the selected net in this case, cclock by selecting Display Show Rats Of Selection. For illustration, the ratsnest lines in the screens of this tutorial have been overdrawn by an illustration program, resulting in a thicker line than is displayed in Allegro PCB Design L. June Product Version 16.0

16 Lesson 2 Notice the net connects connector J7, the clock driver U9, and the processor chipset. Extracting a Net Topology In this exercise, you attempt to extract cclock into SigXplorer for exploration and analysis. The device definition for connector J7, which is connected to cclock, has an incorrect CLASS property, rendering cclock unextractable. You will run the Database Setup Advisor to identify and correct this problem. To extract a net topology 1. From Allegro Allegro PCB Design L, choose Tools Topology Extract. The Topology Template dialog box appears. 2. Select the clock driver net, cclock, using one of the following methods: Scroll through the list of nets, locate cclock, then click on it. June Product Version 16.0

17 Lesson 2 Replace the * in the the Xnet filter field with the net name cclock, then press Tab, then click on the net name. Click on the net in the design. The net extraction begins. The following message appears. 3. Click Yes. The Database Setup Advisor is invoked. The Database Setup Advisor guides you through the following five steps that prepare a net for extraction into SigXplorer. Cross-section DC Nets Devices SI Models SI Audit Important Consult Getting Started with Allegro PCB SI SigXplorer L Series for information on using the Database Setup Advisor. The Database Set Up Advisor is invoked automatically when a non-extractable net is encountered. You can also invoke the advisor with the Tools Setup Advisor command from Allegro PCB Design L. As mentioned earlier, the device definition for connector J7, which is connected to cclock, has an incorrect CLASS property, rendering cclock unextractable. Therefore, you need only work in the Devices section of the Database Setup Advisor. June Product Version 16.0

18 Lesson 2 To correct a device PINUSE with the Database Setup Advisor From the previous exercise, you should have the advisor displayed. 1. Click Next three times to advance to the Device Setup form in the advisor. 2. Click Device Setup. The Device Setup dialog box appears with a brief explanation of how to set up device parameters. 3. Click the Device Setup button. Click here June Product Version 16.0

19 Lesson 2 The following dialog box appears. 4. Accept J* in the Connectors field (the default). The device s PINUSE information derives from the device s CLASS definition. 5. Click OK. The Device Setup Changes report appears. Note that connector J7 was changed from class IC to IO. Because J9 shares the same device definition, it was changed as well. Other connectors in the design remain unchanged with class IO. Caution Had you explicitly specified J7 (instead of J*), J7 and J9 would change to class IO because they share the same part type; however, all other connectors would change to class IC because it is the default value. June Product Version 16.0

20 Lesson 2 6. Dismiss the report. 7. Click Finish to accept the database modifications and dismiss the advisor. With the correct CLASS properties (IO) on Connectors J7 and J9, the clock net is now prepared for extraction. You repeat the net extraction process in the next lesson. If you are using your own board files, in Allegro PCB Design L, choose File Save As and specify myboard3.brd (or whatever naming convention you chose). Congratulations! You have completed Lesson 2. June Product Version 16.0

21 Lesson 2 To Summarize What You Have Learned In this lesson, you have learned to Isolate a single net among a sea of nets Use the Topology Template dialog box Prepare a net for extraction by running the Database Setup Advisor June Product Version 16.0

22 Lesson 2 June Product Version 16.0

23 Lesson 3 Objectives In this lesson, you: Extract a net from Allegro PCB Design L for topology exploration in SigXplorer Explore the extracted circuit topology in SigXplorer Set up reflection measurements in SigXplorer Simulate a net topology in SigXplorer Analyze the resulting spreadsheet- and waveform-data in SigXplorer June Product Version 16.0

24 Lesson 3 Extracting a Net Topology In this exercise, you will extract a net topology for clock signal cclock. You begin with tutboard3.brd loaded in Allegro PCB Design L. To extract a net topology 1. From Allegro PCB Design L, choose Tools Topology Extract. The Topology Template dialog box appears. 2. Using the net selection techniques that you learned in the previous lesson, extract the clock driver net cclock. Note: The extraction checkboxes will be discussed in Lesson 4. The net extraction begins. 3. When the Extracting Net confirmer disappears, click View in the Topology Template dialog box. SigXplorer PCB SI L launches. June Product Version 16.0

25 Lesson 3 Important If a higher tier (XL or GXL) of SigXplorer opens, it indicates you are also licensed to run higher tiers of Cadence products. To launch the correct tier of SigXplorer (for the purposes of this tutorial), set the sigxp_tier environment variable, as described in Read This First! in Chapter One, then: a. Repeat step 3. b. Select Allegro PCB SI L from the Cadence Product Choices form. Exploring the Circuit Topology Upon initial invocation, the editor displays only the canvas. The spreadsheet is sized out of view. Resize the canvas so that it occupies about three-quarters of the SigXplorer window. To resize the canvas area and zoom level 1. Click the horizontal border separating the canvas and the spreadsheet, then drag the border vertically. 2. Click in the canvas and click the zoom fit icon. Zoom Fit icon Drag to vertically to resize The circuit topology expands to accommodate the resized canvas view. June Product Version 16.0

26 Lesson 3 With the topology extracted from your design in Allegro PCB Design L and visible in SigXplorer, you should make the following observations. You may have to zoom and pan as appropriate. Notice: The off-board connector (J7) along with a single driver (U9, Pin 9) and many receivers Transmission lines with delays based on length (derived from Manhattan distance estimates) The driver and all receivers default to Tristate on initial extraction. Default IOCell models were assigned to drivers and receivers based on PINUSE Important When you select a circuit component in the spreadsheet at the bottom of the editor, it will highlight in the topology canvas, at the top of the editor. Examine the circuit parameters Click Parameters and expand all circuit parameters by clicking the + signs until the spreadsheet shows all - signs, indicating the lowest level. Expand/ Collapse Tline Parameters Note the characteristic impedances for the transmission lines in the circuit. You can click in the attribute Value field and change any of these values. The topology element in the canvas will be updated with the new value. June Product Version 16.0

27 Lesson 3 Examine the IOCell models Examine the attribute and value (IOCell buffer model) field of receiver U69. Fully expand field to examine buffer model attribute Click here to invoke the Set Buffer Parameters window You can select a different IOCell buffer model based on your requirements. Dismiss the Set Buffer Parameter dialog box. Note: Consult the SigXplorer online help for a thorough discussion of signal integrity models. June Product Version 16.0

28 Lesson 3 Setting Up for Simulation Before you can simulate and analyze this circuit topology, you must set up for simulation. This involves specifying: Stimulus for the driver (U9, Pin 9) Reflection measurements Each is discussed in the sections that follow. Specifying Stimulus The receivers are preset to their default tri-state condition. You must set the driver to either a Pulse, Rise, or Fall state. You can simulate with only one active driver at a time, which is not an issue with the cclock net as it has only a single driver (U9, Pin 9). To set the driver stimulus state 1. Zoom in on the driver. Click Zoom Points Drag over U9 Your view now focuses on U9 Note the label on the symbol indicating it is tri-stated. 2. Click the TRISTATE label on U9. Click label to change stimulus state June Product Version 16.0

29 Lesson 3 The Stimulus Editor appears. 3. Click Pulse. 4. Click OK. Stimulus State has changed on symbol in canvas The stimulate state of the driver changes to Pulse. Specifying Reflection Measurements 1. Resize the spreadsheet view to occupy about two-thirds of the editor. 2. Click the Measurements tab. 3. Click the Reflection button to expand the measurements view. 4. Click the circle adjacent to the reflection label, and then right-click and choose All Off from the pop-up window. June Product Version 16.0

30 Lesson 3 5. Click on individual measurements as follows: Click here then rightclick and select All Off Click to expand view Click to select individual measurements You are ready to simulate. Simulation and Analysis Now that you have specified a stimulus for the driver, have verified that all receivers are tristated, and have set up measurements to sample, you are now ready to simulate. To simulate the topology Choose Analyze Simulate. Invoke simulator by menupick or by icon click June Product Version 16.0

31 Lesson 3 A pop-up window displays as the simulation progresses. The Command window also becomes active in the spreadsheet so you can monitor the simulation. Once simulation is complete, the Results View appears showing the spreadsheet data. Important You can click on a column header followed by a right-click to invoke a pop-up menu from which you can specify an ordering scheme for the spreadsheet data. The figure below shows an ascending ordering of data. Notice in the Overshoot Low column, many of the receivers approach negative 900 millivolts. June Product Version 16.0

32 Lesson 3 Next, SigWave appears showing the output waveforms from the simulation. Ringing Non-monotonic deviation Negative overshoot Observations include: (1) skew at the clock input to the receivers; (2), a fair amount of ringing; (3), a noticeable negative overshoot of 900 mv below ground; and (4), some non-monotonic activity. Taking a closer look In SigWave, you are going to take a closer look at the problem areas of the waveforms. To zoom in on the bottom of the waveform 1. Click in the SigWave window. 2. Choose Zoom In Region. 3. Drag over the bottom of the waveforms. Zoom over the lower-part of the waveform display Notice that there is approximately a mv overshoot below ground SigWave focuses on the selected area. June Product Version 16.0

33 Lesson 3 The input protection diodes in the receivers are designed to fire at -700 millivolts. You are going to measure the duration that the waveforms dip below this threshold. To mark off time measurements 1. Drag the horizontal marker vertically to this point (-700 mv) mv 2. Click the differential vertical marker icon in the toolbar and size each marker to correspond to the beginning and ending points where the waveforms extend below the -700 mv threshold. Differential Vertical Marker Drag each vertical marker to mark off the portion of the waveform below -700 mv. This should measure approximately 3 nanoseconds This should measure approximately 3.75 nanoseconds in duration. This much negative overshoot lasting for this duration will soon damage the receivers. You will need to take corrective actions to optimize the placement. June Product Version 16.0

34 Lesson 3 Finishing Up In SigWave, save the waveform as preplaced. A.sim file extension is automatically added to the base file name. In the next lesson, you will use this for making comparisons. If you are using your own board files, in Allegro PCB Design L, choose File SaveAs and specify myboard4.brd (or whatever naming convention you chose). Congratulations! You have completed Lesson 3. To Summarize What You Have Learned In this lesson, you learned to: Extract a circuit topology Explore the circuit topology Set up simulation parameters (stimulus and measurements) Simulate and analyze a circuit topology June Product Version 16.0

35 Lesson 4 Objectives In this lesson, you: Move the clock driver chip in PCB Design to a location that is central to other components on the clock circuit Swap components in PCB Design to reduce the length of the clock circuit Simulate this revised circuit topology in Allegro PCB SigXplorer Analyze the resulting spreadsheet- and waveform-data in Allegro PCB SigXplorer June Product Version 16.0

36 Lesson 4 Revising the Board Layout In Lesson 3, you extracted the clock circuit from Allegro PCB Design L based on its initial placement. You performed a reflection simulation in SigXplorer and analyzed results that were unacceptable. In this lesson, you modify the placement of the clock circuit and repeat the analysis process. To begin this lesson, you should have tutboard4.brd open in Allegro PCB Design L. Moving the clock driver The clock driver (U9) is located in the lower-left quadrant of the board, which is some distance from many of the chips (receivers) that it controls. To minimize delays at the receivers, it is best to centralize the placement of this driver. To move the clock chip 1. From PCB Design, choose Edit Move. 2. Drag the cursor (crosshair) across U9 and select it to move. 3. Move U9 by dragging to the location shown below. The ratsnest connections follow the movement of the chip. 4. Click to anchor the placement. 5. Right-click and choose Done from the pop-up menu. Before Move After Move June Product Version 16.0

37 Lesson 4 Swapping Components Although the clock driver is now closer to the receivers, you can shorten the length of the clock net even more by swapping some of the receivers, with chips of the same type, that are even closer to the driver. In this exercise, you will swap U93 with U70, and U85 with U16. Graphic depicts layout before swapping To swap components 1. From PCB Design, choose View Zoom by Points. 2. Drag across the lower-right quadrant of the board. The view now focuses on the chips that you will swap. 3. Choose Place Swap Components. Click U93 (the source component), then click U70 (the target component) The components exchange places on the board. Click U85 (the source component), then click U16 (the target component) The components exchange places on the board. Right-click and choose Done from the pop-up menu. This ends the swap component mode. June Product Version 16.0

38 Lesson 4 Simulation and Analysis Now that you modified the placement in your design by moving the clock chip and some of the receivers, resimulate the clock net to see if you have reduced the noise margin. In Lesson 3, you learned how to do the following. Extract a Net Topology Examine Circuit Parameters Specify Stimulus (Pulse) Specify Measurements Simulate Put these skills to work and simulate the revised circuit topology. The measurements that you previously specified are still in effect. You do not have to reselect them. If SigXplorer is still open, confirm that you want to overwrite the old topology. June Product Version 16.0

39 Lesson 4 Making Signal-to-Signal Comparisons To go a step further, you superimpose the pre-placed waveform (preplace.sim) that you saved in the previous lesson onto the placed waveform which currently displays in SigWave. You then examine pre- and post-placement waveforms with all signals displayed, followed by a signal-to-signal comparison. To superimpose simulation waveforms 1. From SigWave, choose File Import SigWave.sim file. The File Open dialog box appears. 2. Double click preplaced.sim. The pre-placed waveform (preplaced.sim) is superimposed over the placed waveform which remains in memory. Expand waveforms Resize window 3. Expand the signals (as shown) in the waveform libraries folder by clicking the + signs. 4. Size the SigWave window (as shown) so that you can view the signal names. You should observe that all signals from both waveforms display with minimal deviation. June Product Version 16.0

40 Lesson 4 To examine both waveforms (signal-by-signal) 1. Click on each waveform sub-folder in the waveform library folder, then right-click and choose hide all subitems from the pop-up menu. All Signals On All Signals Off Each signal in SigWave is now identified with a slashed-circle in the left pane; waveforms are suppressed in the right pane. Important When manipulating a signal in the left pane of SigWave, you may have to click in the right pane to refresh the waveform display. 2. One at a time, compare each pin of the pre-placed waveform with the corresponding pin of the placed waveform by selecting the net, and then right-click and choose Display from the pop-up menu. Comparing U9, Pin 9 of pre-placed waveform against U9, Pin 9 of placed waveform. Click on signal, then right-click and choose Display. June Product Version 16.0

41 Lesson 4 You should observe results similar to the following. Note: The composite drawing below captures the resulting waveform and spreadsheet data from pre-placed and placed simulations. Waveform analysis after initial placement. Waveform analysis after moving clock driver and swapping components to minimize length of clock signal. Spreadsheet comparison of results from the initial placement (left) to the revised placement (right). You should observe a marked improvement in the waveforms and in the numbers. The negative overshoot is well within the -700 mv margin where the input protection diodes turn on. There is also far less ringing and skew among the receivers. Finishing Up From SigWave, choose File Save and enter placed. In the next lesson, you compare this pre-route waveform (placed.sim) against the post-route waveform. If you are using your own board files, in PCB Design, choose File Save As and specify myboard5.brd (or whatever naming convention you chose). Congratulations! You have completed Lesson 4. June Product Version 16.0

42 Lesson 4 To Summarize What You Have Learned In this lesson, you have learned to: Modify placement by moving and swapping components Compare current simulation waveforms (based on revised placement) against previously saved waveforms (based on initial placement) June Product Version 16.0

43 Lesson 5 Objectives In this lesson, you: Route the clock net Simulate the clock net using actual trace models instead of Manhattan distance estimates Compare simulation waveforms (routed) against previously saved waveforms (unrouted) June Product Version 16.0

44 Lesson 5 Routing the Clock Driver Net In Lesson 4, you extracted the clock circuit from PCB Design based on the revised placement. You performed a reflection simulation in SigXplorer and analyzed the results that are now acceptable. In this lesson, you route the clock net and repeat the simulation and analysis process to verify that you still meet the noise budget. To begin this lesson, you should have tutboard5.brd open in Allegro PCB Design L. To route the clock net 1. From PCB Design, choose Route Route Net(s) By Pick. 2. Click on the visible ratsnest cclock. The PCB Router routes your board in the background. For illustration, the routed trace lines in the screens of this tutorial have been overdrawn by an illustration program, resulting in a thicker trace width than is displayed in PCB Design. June Product Version 16.0

45 Lesson 5 Exploring the Extracted Circuit Topology Using the skills that you learned in previous lessons, do the following. Resize the canvas and the spreadsheet equally. Zoom in on transmission line symbol TL1. Click the parameters tab in the spreadsheet and expand the parameter view to examine the attribute values of TL1. Transmission line symbol: canvas view Transmission line symbol: spreadsheet view The extracted interconnect model describes the connection relative to the reference planes. June Product Version 16.0

46 Lesson 5 Simulation and Analysis Now that you have routed the clock net in your design, you resimulate to verify that you have maintained the revised placement noise margin. In previous lessons, you learned how to do the following: Specify Stimulus Specify Measurements Simulate Compare resulting simulation waveforms Put these skills to work and simulate the routed circuit topology. Caution The pre-routed topology that you extracted in the previous lesson was based on a virtual representation. The routed topology that you are about to extract is based on a physical layout with layer and via information; therefore, before you simulate from SigXplorer, you must choose Analyze Reset Sim Data to reload the interconnect library that contains the electrical model for the extracted via. If SigXplorer is still open, confirm that you want to overwrite the old topology. You should observe results similar to the following. June Product Version 16.0

47 Lesson 5 Note: The composite drawing below captures the resulting waveform and spreadsheet data from pre-route and post-route simulations. Waveform analysis after moving clock driver and swapping components to minimize the length of the clock signal. Waveform analysis verified after extracting routed clock signal. Notice that the post-route waveforms are even more ideal than the waveforms from the modified placement. There is less skew among the receivers, the negative overshoot was reduced from mv to mv. Finishing Up If you are using your own board files, in PCB Design, choose File Save As and specify myboard6.brd (or whatever naming convention you chose). Congratulations! You have completed Lesson 5 and the tutorial. June Product Version 16.0

48 Lesson 5 To Summarize What You Have Learned In this lesson, you learned to: Extract a net topology from PCB Design into SigXplorer Compare current simulation waveforms against previously generated waveforms (based on revised placement) In this tutorial, you learned to: Prepare a net for extraction from PCB Design into SigXplorer. Extract a net based on the initial placement in PCB Design, simulate the net in SigXplorer, and examine the resulting data in the results view of the spreadsheet as well as the resulting waveforms in SigWave. Modify the placement in PCB Design, resimulate and analyze the waveforms, and observe more ideal (less ringing among the receivers, less skew, and less negative overshoot) waveforms. Route the net, resimulate and analyze to verify that the net remains within the noise budget. June Product Version 16.0