Chapter 9. Timing Design. (Based on Chapter 7 and Chapter 8 of Wakerly)

Transcription

1 Chapter 9 Timing esign (Based on Chapter 7 and Chapter 8 of Wakerly) 1 Metastability in bistables, latches, and flip-flops Bistable uestion: How long the set or reset control should be active before becoming passive? Until the friendly echo arrives. S R If this pulse is short, then, may go into a metastable state S = 1=>0=>1 =0=>1 =1=>0 R = 1 -Latch If clock goes inactive immediately after changes, the latch can go into metastable state. See figure 7-12 (page 531) and figure 7-14 (page 531) in Wakerly. 4/12/06 EE201L Class Notes - Chapter #9 Page 1 / 9

2 -FF (positive edge triggered) If clock goes high immediately after changes, the master latch portion of the -FF can go into metastable state. See figure 7-15 (page 532) and figure 7-17 (page 533) in Wakerly. 2 Why would change around the clock Improper timing design Asynchronous inputs (push-button operation by a human) ue to clock Skew (clock may not reach all parts of the chip at the same exact time) 3 Setup time, Hold time, and Propagation delay of a Flip-Flop Setup time t su : The input shall be valid and stable for t su time before the significant edge of the clock. Hold time t h : The input shall be valid and stable for t h time [7:0] after the significant edge of the clock. Note: There is only one value for t su and t h : the minimum. There is no typical or maximum for these. After the clock edge, the output may change after a little time called propagation delay. t su t h 4/12/06 EE201L Class Notes - Chapter #9 Page 2 / 9

3 SN5474, SN54LS74A, SN54S74 SN7474. SN74LS74A, SN74S74 UAL -TYPE POSITIVE-EGE-TRIGGERE FLIP-FLOPS WITH PRESET AN CLEAR SLS119 ECEMBER 1983 REVISE MARCH 1988 min. only 4 POST OFFICE BOX ALLAS, TEXAS /12/06 EE201L Class Notes - Chapter #9 Page 3 / 9

4 4 Timing Check, setup time margin and hold time margin X State machine Next State 0 1 State Memory 0 1 A B EN ata Path Comb. C C <= A + B Counter 0 Incrementer Please see figure 8-1 (page 682), figure 8-63 (page 760) and figure 8-64 (page 760) in Wakerly Setup time Margin = t clk -t ffp(max) - t comb(max) - t setup(min) Hold time Margin = t ffp(min) + t comb(min) - t hold(min) 4/12/06 EE201L Class Notes - Chapter #9 Page 4 / 9

5 What is hold time and why do we need it? Consider a shift register. Serial In Serial Out Relation between t ffpd t h How do we fix hold time violation? How do we fix setup time violation? Where would you be concerned about the maximum delay path through the combinational logic? Where would you be concerned about the minimum delay path through the combinational logic? Comb. 4/12/06 EE201L Class Notes - Chapter #9 Page 5 / 9

6 5 Asynchronous Inputs: Examples of asynchronous inputs: Inputs from human, inputs from other subsystems working on a different independent clock If the asynchronous input changes too late into the clock, the system can go into a wrong state! A 1 0 X = X = 1 C B Wrong state reached due to X changing rather late. X Asynchronous Next State 0 1 State Memory 0 1 Synchronization of asynchronous signals by using a synchronizing FF: XA X_Asynchronous Synchronizing flip-flop Sample-and-hold flip-flop XS X_Synchronized Next State 0 1 State Memory 0 1 Should this sampling edge be the same or opposite of the significant edge of the system? Simple intuitive answer: Well if it is the same edge we create a RACE condition. So it should be opposite edge. That is in fact a naive answer! A more thoughtful answer is that we use the same edge. Because of the finite propagation delay of the synchronizing FF (which is made sure to be greater than the hold time requirements of the receiving system/ffs), the RACE condition is carefully overcome in EVERY digital design. 4/12/06 EE201L Class Notes - Chapter #9 Page 6 / 9

7 The clock for synchronization shall be the (sending/receiving) system's clock. Example from EE201L homework #9: System-33 System-44 System-33 System-44 System-33 System-44 System based on 33 MHZ Clock O-IT ONE System based on 44 MHZ Clock System based on 33 MHZ Clock O_IT 33 MHZ S_ONE S_O_IT ONE 44 MHZ System based on 44 MHZ Clock System based on 33 MHZ Clock O_IT S_O_IT 44 MHZ S_ONE ONE 33 MHZ System based on 44 MHZ Clock esign # 1 esign # 2 esign # 3 esign # 1 experiences synchronization problems as the O-IT signal is asynchronous to the (System-33/ System-44) and also the ONE signal is asynchronous to the (System-33/ System-44). Between esign #2 and # 3, is right and is wrong. 6 What is meant by flip-flops hardened against metastability? It should be noted that even if a flip-flop goes into a metastable state, it is generally difficult for it to remain in such a state. It is like... even if you manage to make a knife stand on its edge for a second, it is likely to fall one way or other very soon. By making the edge of the knife sharper, you reduce the probability of its standing on its edge for notable length of time. Similarly, by increasing the loop gain of the cross connected pair of NAN gates/nor gates making a bistable, any small disturbance (disturbance to the precarious metastable state) will get amplified and push the system to go into one of the two stable states of the bistable. Such flip-flops, which are made to very quickly come out of the metastable state even if they very rarely went in are called flip-flops hardened against metastability. 7 ouble-synchronization helps to reduce the probability of failure due to metastability: XA Increases MTBF (Mean Time Between failures) XS XSS Next State 0 1 State Memory Here we employ two Synchronizing flip-flops. Even if the first one goes into a metastable state, it is expected that it would come out of the metastable state by the time the second flip-slop tries to sample the output of the first flip-flop. More in EE552/EE560: What do we do if we received a multi-bit asynchronous data? No, we do not use multiple synch. FFS /12/06 EE201L Class Notes - Chapter #9 Page 7 / 9

8 8. Setup and hold time window shifts because of path delay in "" or "" The setup and hold time of a flip-flop are 0.3ns and 0.1ns, respectively; but because of the routing issues, some delay may occur on one or both input signals ( and ). The amount of this delay which can be modeled by a buffer is 0.04ns. In the presence of this delay, the setup and hold time of the whole circuit may change. t setup = 0.3ns t hold = 0.1ns A 0.04ns 0.04ns B delay=0.04ns C 0.04ns 0.04ns The setup and hold time of circuit A are t setup = ; t hold = The setup and hold time of circuit B are t setup = ; t hold = The setup and hold time of circuit C are t setup = ; t hold = 9 Result of severe clock-skew problem Figures 8-65 (page 762) and 8-66 (page 763) from Wakerly. 4/12/06 EE201L Class Notes - Chapter #9 Page 8 / 9

9 10 Why does RES (asynchronous RESET) need to be synchronized to produce synchronous RESET? Isn t it true that if we are resetting the system anyway, we are aborting whatever we are doing and going into the INITIAL state. If so, does it matter if we abort synchronously or asynchronously? It is not about when you go into reset. It is about when you come out of reset. The RESET signal is usually generated using an R-C network. Hence it is an asynchronous signal. After the R-C time constant, if the reset signal becomes inactive just before (or at) the significant edge of the clock, then some flip-slops in the state memory may be able to come out of the reset state and start honoring the next-state bits standing at their -inputs, while some other flip-flops may still be in the reset state. This causes the system to go into wrong/illegal states. Let us first explain the problem using the 5-state dish-washer state-machine of EE201L. Let us assume that the ~RESET is asynchronous and becomes inactive just before (or at) the significant edge of the clock (positive edge in this problem). Also assume that the START happens to be true at that time. It is possible for the one-hot flip-flop ONE to continue to remain in the reset state ( ONE = 1), while at the same time the A_WATER flip-flop may come out of reset and go to 1 ( A_WATER = 1). So we have two FFs hot in the one-hot system! Solution: synchronize the asynchronous ~RESET to produce a synchronous reset signal ~SYNC_RESET CS= ~RESET S= START = 0 A WATER CS= S= RINSE RAIN RY ONE Too close to clock edge START = 1 RESET ONE A_WATER RAIN CS START NSL A_WATER RINSE S CS NSL S START NSL ONE RAIN RY ONE VCC Reset PB RESET RESET RESET SYNC_RESET Better to replace this with this. 4/12/06 EE201L Class Notes - Chapter #9 Page 9 / 9