A NOVEL APPROACH TO ACHIEVE HIGH SPEED LOW-POWER HYBRID FLIP-FLOP

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1 A NOVEL APPROACH TO ACHIEVE HIGH SPEED LOW-POWER HYBRID FLIP-FLOP R.Ramya 1, P.Pavithra 2, T. Marutharaj 3 1, 2 PG Scholar, 3 Assistant Professor Theni Kammavar Sangam College of Technology, Theni, Tamil Nadu, (India) ABSTRACT Dual dynamic hybrid flip-flop (DDFF) and a embedded logic module (DDFF-ELM) design will eliminate the large capacitance present in precharge node in various dynamic circuits. A split dynamic node structure is used to drive the output pull-up and pull-down transistor. An area, power, speed method is used to incorporate complex logic functions into the flip flop. A comparison is made in a 90 nm UMC which shows a power reduction of 27% with no speed degradation compared to the conventional flip flops. The proposed system also compares the leakage power and process-voltage-temperature of various design. A 4-b synchronous counter and 4 b Johnson up-down-counter is used to compare the DDFF and DDFF-ELM system with the other designs. The latching overhead and the less power dissipation in the proposed system indicates it is best suited for the high end technologies. Keywords: Embedded Logic, Flip-Flops, High-Speed, Leakage Power, Low-Power. I. INTRODUCTION Technology and speed are always moving forward, from low scale integration to large and VLSI and from megahertz (MHz) to gigahertz (GHz). The system requirements are also rising up with this continuous advancing process of technology and speed of operation. In synchronous systems, high speed has been achieved using advanced pipelining techniques. II. ANALYSIS OF FLIP-FLOP ARCHITECTURES A large number of flip-flops and latches have been published in the past few decades. They can be grouped under the static and dynamic design styles. The former includes the master slave designs, such as the transmission gate based master-slave flip-flop in and the PowerPC 603 master-slave latch. They dissipate comparatively lower power and have a low clock-to-output (CLK-Q) delay. In a synchronous system, the delay overhead associated with the latching elements is expressed by the data-to-output (D-Q) delay rather than CLK- Q delay. Here, D-Q delay refers to the sum of CLK-Q delay and the setup-time of the flip-flop. But the static designs mentioned earlier lack a low D-Q delay because of their large positive setup time. Also, most of them are susceptible to flow-through resulting from CLK overlap. Latches and flip-flops have a direct impact on power consumption and speed of VLSI systems. Therefore study on low-power and high performance latches and flip-flops is inevitable. The goal of this work is to find a small 76 P a g e

2 set (ideally the smallest set) of flip-flop topologies to be included in a library covering a wide range of powerperformance targets. The factors which are desirable in latches and flip-flops are as follows: High speed Low power consumption Robustness and noise stability Small area and less number of transistors Supply voltage scalability Low glitch probability Large internal race immunity Insensitivity to clock edge Insensitivity to process variables Less internal activity when data activity is low 2.1 Power Pc_603 PowerPC 603 is one of the most efficient classic static structures. The large D-Q delay and CLK node capacitances make the design inferior in performance. SDFF is the fastest classic hybrid structure, but is not efficient as far as power consumption is concerned because of the large CLK load as well as the large pre-charge capacitance. Power PC means Performance Optimization With Enhanced RISC Performance Computing. They dissipate comparatively low power and they are also having low clock-to-output (CLK-Q) delay. The advantages of Power PC include low-power keeper structure and low latency direct path. The keeper structure in the circuit saves the leakage power. Latency is the time to complete a single instruction from start to finish. The large D-Q delay resulting from the positive setup-time is one of the disadvantages of this design. The large data and CLK node capacitances make the design inferior in performance. The dynamic flip-flops includes the modern high performance flip-flops. They are divided into purely dynamic designs and pseudo-dynamic structures. The distinctive performance improvements are achieved by having an internal precharge structure and a static output. They are called as the semi-dynamic or hybrid structures. 2.2 Hybrid Latch Flip-Flop (HLFF) Hybrid Latch Flip-Flop is one of today s high-performance flip-flops. HLFF have the benefit of CLK overlap to perform the latching operation. SDFF is the faster than classic hybrid structure, but has high power consumption due to large CLK load and the large precharge capacitance. HLFF is not the faster but has a lower power consumption when compared to SDFF because of the longer stack of nmos transistors at the output node makes it slower than SDFF and causes large hold-time requirement. Due to this large hold time requirement, makes the integration of HLFF to complex circuits difficult process. And also HLFF is inefficient in embedding the logic. 3.3 Semidynamic Flip-Flop (SDFF) HLFF and SDFF come under this category. They have the benefit of CLK overlap to perform the latching operation. SDFF is the faster than classic hybrid structure, but has high power consumption due to large CLK load and the large precharge capacitance.the circuit is composed of a dynamic front-end and a static backend. The circuit operates as the falling edge of clock ClK, the flip-flop enters the precharge phase. Node X is 77 P a g e

3 precharged high, cutting off node Q from the input stage. The static latch INV5-6 holds the previous logic level of Q and QB. The evaluation phase begins with the rising edge of clock CX. If input D is low (i.e., the flop is latching a zero) node X would remain high, held by the INV3-4 latch. Node Q would either remain low or will be discharged through transistors N4-5, driving QB high. Three gate delays after CK rises, node S will be driven low, turning transistor N1 off. This shut-of operation will prevent a subsequent low-to-high transition of D from discharging node X. This feature provides the flip-flop its edge-triggered nature. If input D were high prior to evaluation (i.e., the flop is latching a one), node X would be discharged through the pull down path N1-3. The static latch INV3-4 would hold the value of X even if input D were subsequently driven low. The high-to-low transition of X will turn transistor on, driving Q high and output QB low. The falling transition of X would also force node S to remain high, preventing the shut-off of transistor N1, which is unnecessary after node X has been discharged. 3.4 DDFF The DDFF is designed in such a way that it comes with the reduced area, due to lesser number of transistors used for the design. The basic concept of this structure comes from the overlap based cell. The power dissipation of this flip-flop design is lower than the existing flip-flop. There are two nodes in the circuit among which one is purely dynamic and another is pseudo-dynamic. Node X1 is pseudo-dynamic, with a weak inverter acting as a keeper, whereas, compared to the XCFF, in the new architecture node X2 is purely dynamic. An unconditional shutoff mechanism is provided at the frontend instead of the conditional one in XCFF. The operation of the flip-flop can be divided into two phases: 1) the evaluation phase, when CLK is high. 2) the precharge phase, when CLK is low. 78 P a g e

4 a, PowerPC 603, b, Hybrid Latch Flip-Flop (HLFF), c, Semidynamic flip-flop(sdff), d, DDFF, e, Proposed DDFF-Embedded Logic Module (DDFF-ELM), f, 4-b Johnson up-down counter 3.5 Proposed DDFF-Embedded Logic Module (DDFF-ELM) The efficiency in terms of speed and area comes from the fact that an N-input function can be realized in a positive edge triggered structure using a pull-down network (PDN) consisting of N transistors as Compared to the discrete combination of N a static gate and a flip-flop, this embedded structure offers a very fast and small implementation. Although SDFF is capable of offering efficiency in terms of speed and area, it is not a good solution as far as power consumption is concerned. Not too many attempts have been made to design a flip-flop, which can incorporate logic efficiently in terms of power, speed and area. This embedded structure offers a very fast and small implementation. Although SDFF is capable of offering efficiency in terms of speed and area, it is not a good solution as far as power consumption is concerned. Not too many attempts have been made to design a flip-flop, which can incorporate logic efficiently in terms of power, speed and area. The double-pulsed set-conditional-reset flip-flop (DPSCRFF) is one of the flip-flops capable of incorporating logic. But this structure has an explicit pulse generator to generate two pulses from the global CLK, which can cause large power consumption even when there is no data transition. Also, the three inverter delay between the two pulses. The large hold time requirements prevent it from being directly cascaded without the use of additional buffers. Another flip-flop design aiming at efficient logic embedding is presented. But the overlap based logic cell is similar to the single-phase pulsed flip-flop. Since SDFF is proved to outperform this design, we consider SDFF with embedded logic for comparative purposes B Johnson Up-Down Counter A 4-b Johnson up-down counter with asynchronous reset has been designed. The counter is designed with a set of 2-input multiplexers and flip-flops. In the embedded structure, the discrete combination of multiplexer and flip-flop is replaced by a multiplexer embedded flip-flop. The ELM and the SDFF with embedded logic were incorporated with asynchronous-reset (rst_n) functionality. The Johnson up/down counter, also known as the twisted-ring counter, is exactly the same as the ring counter except that the inverted output of the last flip-flop is connected to the input of the first flip-flop. Up-Down counter is a combination of the up counter and down counter. As the up-down counter has the capability of counting upwards as well as downwards, it is also called multimode counter. In an up counter, each flip-flop is triggered by the normal output of preceding flip-flop; in a down counter is triggered by the inverted output of the preceding flip-flop. In both counters, the first flip-flop is triggered by the input pulses. When the control inputs are both 0 (or) 1, the counter will not count up (or) count down because the clock inputs of next flip-flops wii be held constant at either 0 or 1. Let s say, starts from 000, 100, 110, 111, 011 and 001, 79 P a g e

5 and the sequence is repeated so long as there is input pulse. To initialize the operation of the Johnson counter, it is necessary to reset all flip-flops. CIRCUI T NAME POWER PC Performance comparison of various flip-flops HLFF SDFF DDFF PROPOSED SDFF DDFF-ELM Power 63.82uw 216uw 157uw 167uw 172uw Delay 903ps 984ps 3ns 3ns 3ns IV. CONCLUSION AND FUTURE WORK A novel technique of flip flop design based on DDFF and DDFF-ELM were proposed. A proper pulse width is assumed to make the design simpler. The proposed system offers a power reduction of 37% and 30% compared to the conventional flip-flops at data activates of 25% and 50 %. The comparison with the solid semi-conductor shows there is no power degradation in the proposed system. A power reduction of 26% was observed when the basic system was embedded. The elimination of charge sharing efficiently helps incorporating the complex logic into the flip-flop. The proposed ELM over performs the SDFF in CLK driving power and the power dissipation internally. The efficiency of the proposed system further comes out with the comparison with the 4-b synchronous counter and 4-b Johnson up/down counter. All the above results show that the proposed system is well suited for the modern high-end technologies where power dissipation latching overhead is a major concerned. REFERENCES [1] Asanovic, K., and Ma, A., A double-pulsed set-conditional-reset flipflop, Laboratory for Computer Science, Massachusetts Inst. Technology, Cambridge, Tech. Rep. MIT-LCS-TR-844, May [2] Afzali-Kusha, A., Khademzadeh, A., Nourani, M., and Rasouli, S. H., Low-power single- and doubleedge-triggered flip-flops for high-speed applications, Proc. Inst. Elect. Eng. Circuits Devices Syst., vol. 152, no. 2, pp , Apr [3] Alvandpour, A., and Hansson, M., Comparative analysis of process variation impact on flip-flop powerperformance, in Proc. IEEE Int. Symp. Circuits Syst., May 2007, pp [4] Aleksic, M., Nedovic, N., and Oklobdzija, V. G., Conditional pre-charge techniques for power-efficient dual-edge clocking, in Proc. Int. Symp. Low-Power Electron. Design, 2002, pp [5] Bayoumi, M. A., Darwish, T. K., and Zhao, P., High-performance and low-power conditional discharge flip-flop, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 12, no. 5, pp , May [6] Cooke, M., Mahmoodi, H., Roy, K, and Tirumalashetty, V., Ultra lowpower clocking scheme using energy recovery and clock gating, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 17, no. 1, pp , Jan P a g e

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