Deep Silicon Etch Technology for Advanced MEMS Applications

Transcription

1 Deep Silicon Etch Technology for Advanced MEMS Applications Shenjian Liu, Ph.D. Managing Director, AMEC

2 AMEC Company Profile and Product Line-up AMEC HQ, R&D and MF Facility in Shanghai AMEC Taiwan AMEC Singapore AMEC Japan AMEC Korea AMEC USA EUROPE TELTEC Service Center AMEC Product Line-up Dielectric Etch Poly Etch TSV/MEMS Etch MOCVD VOC Entered international market Processed over 24.5M 65-16nm wafers Start to market from advanced etch for Memory Logic applications Entered international market Domestic market share over 50% Entered domestic market 13 systems delivered to customers Entered domestic market Targeting LCD Industry

3 Presentation Outline The Market Trend The Technical Challenges in MEMS Etch AMEC s Strategy and Solutions Summary

4 The Market Trend

5 MEMS Acceleration

6 Etch Is One of the Critical Process Steps for MEMS Fabrication MEMS AND SENSORS IN MOBILE DEVICES MEMS Etch Example by AMEC Gyrometer Microphone Accelerometer CIS CCD Isolation Source: Yole Development, MSIG Asia, Shanghai, 2016

7 Technical Challenges in MEMS Etch

8 Major Technical Challenges in MEMS Si etch

9 How to Minimize Profile Tilting?

10 Profile Tilting Is One of Major Issues in MEMS Si Etch Si profile tilting affects the resonance frequency of MEMS sensors <0.2 Profile tilting is typically required Vertical Profile Tilt Profile

11 What Is Causing Profile Tilting in MEMS Si Etch? Profile tilting caused by deviation of ion injection angle Two factors influence ion injection angle 1 No uniform plasma Non-uniform Sheath 2 Transition effect at wafer edge Ion injection Bulk plasma Ion inject normal to sheath boundary 2 1 Plasma sheath Wafer

12 Oxide Etch Rate Tilting Angle ( ) Plasma Uniformity Affecting Profile Tilting (5x50 m Si via) Various plasma conditions tested to investigate the effect Less profile tilting with more uniform plasma Plasma uniformity (Oxide Etch Rate uniformity) for various conditions* Experimental Result on Tilting Angle Bad plasma unif Good plasma unif X Position on wafer (mm) Bad plasma unif Good plasma unif X Position (mm) Wafer Titling angle: - 0 +

13 Profile Tilting at Wafer Edge-Sheath Transition Is Critical Profile tilting at wafer edge is improved by optimizing the hardware design at wafer edge Simulation by Dr. Zhou Ning of AMEC Experimental Result (5x50um Si via) Conventional Design with Weak RF Coupling at Wafer Edge Ions Sheath ESC Ceramic Modified Design to Enhance RF Bias Coupling at Wafer Edge Ions Sheath ESC Ceramic Condition: 100 mtorr, 1000sccm Ar, Vdc=204V Wafer Titling angle: - 0 +

14 MEMS Etch Example by AMEC- No Visible Profile Tilting Across Wafer Center Middle Edge 1.5x35 m Trench Etch on 8 Wafer Profile tilting from SEM picture: <0.13 Enabling Technology: Uniform Plasma + Wafer Edge RF Coupling Tuning

15 How to Achieve Smooth Sidewall?

16 Trade Off of Necking and Taper with Non-Bosch Process Lean chemistry: Top Necking Polymerizing Chemistry: Tapered profile Example of Si Via Profile with Non-Bosch Process Ion angle distribution Trade off Deposition Solution: Bosch Process (Cycling of Depo/Etch)

17 Bosch Process Can Easily Form Vertical Profile But with Scallops Why Bosch Process? For Vertical Profile Isotropic etching Deposition Removal of bottom passivation layer by ion bombardment Isotropic etching Resulting profile 10x100 m Si Via

18 Large Scallop Will Lead to Poor Device Performance Major issues of large scallop Inter-via electrical leakage current. Interfacial stress of CVD/ PVD layer Sidewall damage during plasma etch Discontinuous Rough sidewall Smooth sidewall Process flow Nagarajan Ranganathan et al., IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY, 2011 (1), P Sidewall damage during etch Deposition Isotropic Etch Pinhole Poor coverage F Striation

19 Scallops Eliminated by Fast Gas Switching/Shorter Step Time Baseline Step Time Effect on Scallop Size 30% Step time Longer step time Shorter step time Normalized Step Time

20 Challenge A to Realize Short Step Time- Gas Flow Control Sensor Conventional Gas Flow Control: Sensing gas flow with by-bass sensor Slow response due to indirect sensing (typically >0.5sec) Gas flow Gas flow Sensor Gas Flow Control with MEMS*: Direct sensing the flow Fast response (typically <50msec) * Courtesy of SENSIRION Direct Flow Sensing is Necessary for smooth sidewall

21 10x Faster Gas Switching with MEMS Based Gas Flow Controller Flow Response Comparison* Set point 500sccm Reading Conventional MFC 1sec Set point 500sccm MEMS Based MFC Reading 1sec *Set point: 500sccm C4F8, MFC full scale=500sccm C 4 F 8 SF 6 SiF 4 SF x + SF 6 (CF x ) n SiF 4 F Silicon Silicon Silicon

22 Challenge B to Realize Short Step Time- Step Time Accuracy Step time Step variation Case A: Step time=1sec Variation~0.1sec* (10%) Root causes: Communication delay Step time Step variation Case B: Step time=0.2sec Variation~0.1sec (50%) More accurate time control is needed for shorter step time!

23 Large Variation When Step Time Is Short Example of Step Time Variation 2000ms/div Set Point=200ms Set Point=200ms 500ms/div 453ms (actual step time) 255ms (actual step time) Actual Time= ms

24 Step Time Variation Significantly Reduced with New Technloogy Stress test: 1000cycles(900sec) Total Step time (~900sec) Step time variation Before improvement (Ethernet Based) Time variation: 55.7sec (6%) Total Step time (~900sec) Step time variation With New Communication Technology (Fiber Optics based ) Time variation: 1.5sec (0.17%)

25 Example of Scallop Free TSV Etch (12x100 m) Enabling Technology: Fast Gas Switching + New Communication

26 How to Eliminate Bottom Notch?

27 Bottom Notching on SOI Caused by Charge Build Up Mask Si Mask Si SiO2 Sub Si Bottom Notching SiO2 Sub Si (a) (b) (c) (a)soi film stack before Si etching (b) Ion bending due to charge build up on buried oxide layer (c) Notching at SI/oxide interface in a conventional Si etching process

28 Bias Pulsing to Reduce Charge-up CW Mode High Power / Low DC* Pulsed Bias Mode Bias ON (DC >=10%) Ion bending Due to charge build up Mask Bias ON Less ion bending due to less charge and high bias Bias Off Charge relaxation due to neutralization Bias ON Less ion bending due to less charge and high bias Si Bottom Notching SiO2 Sub Si ON OFF DC%=ON /(ON+OFF) Charge build-up takes some time Low DC bias pulsing: turn off RF bias before charge builds up

29 Notch Free MEMS Trench Etch Example Very Low DC% Bias Pulsing Needed for Notch Free Profile

30 Stiction Issue with Cavity by Charge-up During Plasma Etch Upper structure Cavity Lower structure Example of Stiction Issue (Gyrometer) Plasma Electrostatic force Stiction Issue Electrons and Ions Hit the wafer and charges build-up during plasma etch Floating structures are common in MEMS device Electrostatic force due to charge-up causes upper and lower structure stuck together Low Duty Cycle Bias Pulsing Required to Minimize Plasma Charge-up

31 CD and Profile Uniformity Control

32 Deposition Rate in Bosch Process is Temperature Sensitive* Deposition Sensitivity= 1.2% / C * Example of Temperature Sensitivity with C 4 F 8 Chemistry by AMEC

33 Example of Tuning ESC Temperature Setting for CD Uniformity Single Zone ESC Temp: Center=Edge=5 C Dual Zone ESC Temp: Center=5 C/Edge= 0 C CD Range= 0.15 m CD Range= 0.03 m

34 Dual zone ESC for CD and profile uniformity control Condition: 3kW RF power from generator; 1.5kW heat goes to ESC Tunable Center hotter Edge hotter Dual Zone Chiller ESC can be used in high RF power applications Better temperature control than using dual zone backside He Better cooling capacity than regular Single Zone ESC Avoids hot spot issues commonly encountered with embedded heaters running high RF power applications

35 Example of Si Trench Etch for Gyroscope Application (2x40 m) Location Center Middle Edge Profile TCD Center/Edge CD Range =0.04 m on Whole Wafer Enabling Technology: Dual Chiller Zone ESC, etc.

36 AMEC s Solution to Challenges in MEMS Etch

37 AMEC TSV/MEMS Etcher Served Available Market MEMS 3D IC LED 2.5D IC Interposer CIS Dicing Not Serve yet Already Served Innovative chamber design to provide solutions to all technical challenges in MEMS and TSV Etch Compact design to deliver high wafer output per footprint with Low COO with dual chamber design

38 Thank You!