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1 Come and join us at WebLyceum For Past Papers, Quiz, Assignments, GDBs, Video Lectures etc Go to and click Register In Case of any Problem Contact Administrators Rana Muhammad Safdar Bilal Farooq Come and join us at VU Social For Non-Study Material Sharing, Chatting, etc, Go to and click Register (Weblyceum is not responsible for any solved content) Collected and Composed by Bilal Farooq

2 FINALTERM EXAMINATION Spring 2010 CS302- Digital Logic Design Question No: 1 ( Marks: 1 ) - Please choose one A 8-bit serial in / parallel out shift register contains the value 8, clock signal(s) will be required to shift the value completely out of the register Question No: 2 ( Marks: 1 ) - Please choose one A frequency counter Counts pulse width Counts no. of clock pulses in 1 second Counts high and low range of given clock pulse None of given options Question No: 3 ( Marks: 1 ) - Please choose one In a sequential circuit the next state is determined by and State variable, current state Current state, flip-flop output Current state and external input Input and clock signal applied Question No: 4 ( Marks: 1 ) - Please choose one The divide-by-60 counter in digital clock is implemented by using two cascading counters: Mod-6, Mod-10 Mod-50, Mod-10 Mod-10, Mod-50 Mod-50, Mod-6 Collected and Composed by Bilal Farooq (bilal.zaheem@gmail.com)

3 Question No: 5 ( Marks: 1 ) - Please choose one In NOR gate based S-R latch if both S and R inputs are set to logic 0, the previous output state is maintained. True False Question No: 6 ( Marks: 1 ) - Please choose one Flip flops are also called Bi-stable dualvibrators Bi-stable transformer Bi-stable multivibrators Bi-stable singlevibrators Question No: 7 ( Marks: 1 ) - Please choose one The minimum time for which the input signal has to be maintained at the input of flip-flop is called of the flip-flop. Set-up time Hold time Pulse Interval time Pulse Stability time (PST) Question No: 8 ( Marks: 1 ) - Please choose one 74HC163 has two enable input pins which are and ENP, ENT ENI, ENC ENP, ENC ENT, ENI Question No: 9 ( Marks: 1 ) - Please choose one is said to occur when multiple internal variables change due to change in one input variable Clock Skew Race condition Hold delay Hold and Wait Collected and Composed by Bilal Farooq (bilal.zaheem@gmail.com)

4 Question No: 10 ( Marks: 1 ) - Please choose one Given the state diagram of an up/down counter, we can find The next state of a given present state The previous state of a given present state Both the next and previous states of a given state The state diagram shows only the inputs/outputs of a given states Question No: 11 ( Marks: 1 ) - Please choose one The input overrides the input Asynchronous, synchronous Synchronous, asynchronous Preset input (PRE), Clear input (CLR) Clear input (CLR), Preset input (PRE) Question No: 12 ( Marks: 1 ) - Please choose one A logic circuit with an output consists of. two AND gates, two OR gates, two inverters three AND gates, two OR gates, one inverter two AND gates, one OR gate, two inverters two AND gates, one OR gate Question No: 13 ( Marks: 1 ) - Please choose one A decade counter is. Mod-3 counter Mod-5 counter Mod-8 counter Mod-10 counter Question No: 14 ( Marks: 1 ) - Please choose one In asynchronous transmission when the transmission line is idle, It is set to logic low It is set to logic high Remains in previous state Collected and Composed by Bilal Farooq (bilal.zaheem@gmail.com)

5 State of transmission line is not used to start transmission Question No: 15 ( Marks: 1 ) - Please choose one A Nibble consists of bits Question No: 16 ( Marks: 1 ) - Please choose one The output of this circuit is always. 1 0 A Question No: 17 ( Marks: 1 ) - Please choose one Excess-8 code assigns to Question No: 18 ( Marks: 1 ) - Please choose one The voltage gain of the Inverting Amplifier is given by the relation Vout / Vin = - Rf / Ri Vout / Rf = - Vin / Ri Rf / Vin = - Ri / Vout Rf / Vin = Ri / Vout Collected and Composed by Bilal Farooq (bilal.zaheem@gmail.com)

6 Question No: 19 ( Marks: 1 ) - Please choose one LUT is acronym for Look Up Table Local User Terminal Least Upper Time Period None of given options Question No: 20 ( Marks: 1 ) - Please choose one DRAM stands for Dynamic RAM Data RAM Demoduler RAM None of given options Question No: 21 ( Marks: 1 ) - Please choose one The three fundamental gates are AND, NAND, XOR OR, AND, NAND NOT, NOR, XOR NOT, OR, AND Question No: 22 ( Marks: 1 ) - Please choose one Which of the following statement is true regarding above block diagram? Triggering takes place on the negative-going edge of the CLK pulse Triggering takes place on the positive-going edge of the CLK pulse Triggering can take place anytime during the HIGH level of the CLK waveform Triggering can take place anytime during the LOW level of the CLK waveform Collected and Composed by Bilal Farooq (bilal.zaheem@gmail.com)

7 Question No: 23 ( Marks: 1 ) - Please choose one The total amount of memory that is supported by any digital system depends upon The organization of memory The structure of memory The size of decoding unit The size of the address bus of the microprocessor Question No: 24 ( Marks: 1 ) - Please choose one The expression F=A+B+C describes the operation of three bits Gate. OR AND NOT NAND Question No: 25 ( Marks: 1 ) - Please choose one Stack is an acronym for FIFO memory LIFO memory Flash Memory Bust Flash Memory Question No: 26 ( Marks: 1 ) - Please choose one Addition of two octal numbers 36 and 71 results in Question No: 27 ( Marks: 2 ) Define quantization process. Question No: 28 ( Marks: 2 ) Explain the difference between 1-to-4 Demultiplexer and 2-to-4 Binary Decoder? Collected and Composed by Bilal Farooq (bilal.zaheem@gmail.com)

8 Question No: 29 ( Marks: 2 ) A general Sequential circuit consists of a combinational circuit and a memory element. How this memory element is implemented Question No: 30 ( Marks: 2 ) Suppose a 2 bit up-counter, having states A, B, C, D. Write down GOTO statements to show how present states change to next states. Question No: 31 ( Marks: 3 ) Name three Operations that can be performed on FLASH Memory Question No: 32 ( Marks: 3 ) Explain Rotate Right Operation of shift register with the help of diagram. Question No: 33 ( Marks: 3 ) You are given the block diagram of 74HC190 integrated circuit up/down counter, explain the function of labeled inputs/outputs. Question No: 34 ( Marks: 5 ) Draw the state diagram of 3-bit up-down counter, use an external input X, when X sets to logic 1, the counter counts downwards, otherwise upward. Collected and Composed by Bilal Farooq (bilal.zaheem@gmail.com)

9 Question No: 35 ( Marks: 5 ) Differentiate between synchronous and asynchronous RAM. Question No: 36 ( Marks: 5 ) Explain Memory Select or Enable Signals Collected and Composed by Bilal Farooq (bilal.zaheem@gmail.com)

10 Come and join us at WebLyceum For Past Papers, Quiz, Assignments, GDBs, Video Lectures etc Go to and click Register In Case of any Problem Contact Administrators Rana Muhammad Safdar Bilal Farooq Come and join us at VU Social For Non-Study Material Sharing, Chatting, etc, Go to and click Register (Weblyceum is not responsible for any solved content) Collected and Composed by Bilal Farooq

11 FINALTERM EXAMINATION Spring 2009 CS302- Digital Logic Design (Session - 2) Question No: 1 ( Marks: 1 ) - Please choose one The diagram given below represents Demorgans law Associative law Product of sum form Sum of product form Question No: 2 ( Marks: 1 ) - Please choose one Excess-8 code assigns to Question No: 3 ( Marks: 1 ) - Please choose one NOR gate is formed by connecting OR Gate and then NOT Gate NOT Gate and then OR Gate AND Gate and then OR Gate OR Gate and then AND Gate Question No: 4 ( Marks: 1 ) - Please choose one A full-adder has a Cin = 0. What are the sum (<PRIVATE "TYPE=PICT;ALT=sigma"> ) and the carry (Cout) when A = 1 and B = 1? Collected and Composed by Bilal Farooq (bilal.zaheem@gmail.com)

12 = 0, C out = 0 = 0, C out = 0 = 0, C out = 1 = 1, C out = 0 = 1, C out = 1 Question No: 5 ( Marks: 1 ) - Please choose one adder has -A particular half 2 INPUTS AND 1 OUTPUT 2 INPUTS AND 2 OUTPUT 3 INPUTS AND 1 OUTPUT 3 INPUTS AND 2 OUTPUT Question No: 6 ( Marks: 1 ) - Please choose one THE FOUR OUTPUTS OF TWO 4-INPUT MULTIPLEXERS, CONNECTED TO FORM A 16-INPUT MULTIPLEXER, ARE CONNECTED TOGETHER THROUGH A 4-INPUT GATE AND OR NAND XOR Question No: 7 ( Marks: 1 ) - Please choose one A FIELD-PROGRAMMABLE LOGIC ARRAY CAN BE PROGRAMMED BY THE USER AND NOT BY THE MANUFACTURER. TRUE FALSE Question No: 8 ( Marks: 1 ) - Please choose one FLIP FLOPS ARE ALSO CALLED BI-STABLE DUALVIBRATORS BI-STABLE TRANSFORMER BI-STABLE MULTIVIBRATORS Bi-stable singlevibrators Question No: 9 ( Marks: 1 ) - Please choose one A POSITIVE EDGE-TRIGGERED FLIP-FLOP CHANGES ITS STATE WHEN LOW-TO-HIGH TRANSITION OF CLOCK Collected and Composed by Bilal Farooq (bilal.zaheem@gmail.com)

13 HIGH-TO-LOW TRANSITION OF CLOCK ENABLE INPUT (EN) IS SET PRESET INPUT (PRE) IS SET Question No: 10 ( Marks: 1 ) - Please choose one IS ONE OF THE EXAMPLES OF SYNCHRONOUS INPUTS. J-K INPUT EN INPUT Preset input (PRE) CLEAR INPUT (CLR) Question No: 11 ( Marks: 1 ) - Please choose one THE GLITCHES DUE TO RACE CONDITION CAN BE AVOIDED BY USING A GATED FLIP-FLOPS PULSE TRIGGERED FLIP-FLOPS POSITIVE-EDGE TRIGGERED FLIP-FLOPS NEGATIVE-EDGE TRIGGERED FLIP-FLOPS Question No: 12 ( Marks: 1 ) - Please choose one THE DESIGN AND IMPLEMENTATION OF SYNCHRONOUS COUNTERS START FROM TRUTH TABLE K-MAP STATE TABLE STATE DIAGRAM Question No: 13 ( Marks: 1 ) - Please choose one THE HOURS COUNTER IS IMPLEMENTED USING ONLY A SINGLE MOD-12 COUNTER IS REQUIRED MOD-10 AND MOD-6 COUNTERS MOD-10 AND MOD-2 COUNTERS A SINGLE DECADE COUNTER AND A FLIP-FLOP Question No: 14 ( Marks: 1 ) - Please choose one GIVEN THE STATE DIAGRAM OF AN UP/DOWN COUNTER, WE CAN FIND THE NEXT STATE OF A GIVEN PRESENT STATE THE PREVIOUS STATE OF A GIVEN PRESENT STATE BOTH THE NEXT AND PREVIOUS STATES OF A GIVEN STATE The state diagram shows only the inputs/outputs of a given states Collected and Composed by Bilal Farooq (bilal.zaheem@gmail.com)

14 Question No: 15 ( Marks: 1 ) - Please choose one In outputs depend only on the current state. Mealy machine MOORE MACHINE STATE REDUCTION TABLE STATE ASSIGNMENT TABLE Question No: 16 ( Marks: 1 ) - Please choose one A SYNCHRONOUS DECADE COUNTER WILL HAVE FLIP-FLOPS Question No: 17 ( Marks: 1 ) - Please choose one A MULTIPLEXER WITH A REGISTER CIRCUIT CONVERTS SERIAL DATA TO PARALLEL PARALLEL DATA TO SERIAL Serial data to serial PARALLEL DATA TO PARALLEL Question No: 18 ( Marks: 1 ) - Please choose one The alternate solution for a multiplexer and a register circuit is PARALLEL IN / SERIAL OUT SHIFT REGISTER SERIAL IN / PARALLEL OUT SHIFT REGISTER PARALLEL IN / PARALLEL OUT SHIFT REGISTER SERIAL IN / SERIAL OUT SHIFT REGISTER Question No: 19 ( Marks: 1 ) - Please choose one AT T0 THE VALUE STORED IN A 4-BIT LEFT SHIFT WAS 1. WHAT WILL BE THE VALUE OF REGISTER AFTER THREE CLOCK PULSES? Collected and Composed by Bilal Farooq (bilal.zaheem@gmail.com)

15 Question No: 20 ( Marks: 1 ) - Please choose one A 8-BIT SERIAL IN / PARALLEL OUT SHIFT REGISTER CONTAINS THE VALUE 8, CLOCK SIGNAL(S) WILL BE REQUIRED TO SHIFT THE VALUE COMPLETELY OUT OF THE REGISTER Question No: 21 ( Marks: 1 ) - Please choose one 5-BIT JOHNSON COUNTER SEQUENCES THROUGH STATES Question No: 22 ( Marks: 1 ) - Please choose one IN Q OUTPUT OF THE LAST FLIP-FLOP OF THE SHIFT REGISTER IS CONNECTED TO THE DATA INPUT OF THE FIRST FLIP-FLOP OF THE SHIFT REGISTER. MOORE MACHINE Meally machine Johnson counter Ring counter Question No: 23 ( Marks: 1 ) - Please choose one DRAM STANDS FOR DYNAMIC RAM Data RAM Demoduler RAM None of given options Question No: 24 ( Marks: 1 ) - Please choose one IF THE FIFO MEMORY OUTPUT IS ALREADY FILLED WITH DATA THEN IT IS LOCKED; NO DATA IS ALLOWED TO ENTER IT IS NOT LOCKED; THE NEW DATA OVERWRITES THE PREVIOUS DATA. PREVIOUS DATA IS SWAPPED OUT OF MEMORY AND NEW DATA ENTERS NONE OF GIVEN OPTIONS Collected and Composed by Bilal Farooq (bilal.zaheem@gmail.com)

16 Question No: 25 ( Marks: 1 ) - Please choose one LUT is acronym for LOOK UP TABLE LOCAL USER TERMINAL LEAST UPPER TIME PERIOD NONE OF GIVEN OPTIONS Question No: 26 ( Marks: 1 ) - Please choose one OF A D/A CONVERTER IS DETERMINED BY COMPARING THE ACTUAL OUTPUT OF A D/A CONVERTER WITH THE EXPECTED OUTPUT. RESOLUTION Accuracy Quantization Missing Code Question No: 27 ( Marks: 1 ) - Please choose one In the circuit diagram of 3-bit synchronous counterthe red rectangle would be replaced which gate? AND OR NAND XNOR Question No: 28 ( Marks: 1 ) - Please choose one, shown above WHEN BOTH THE INPUTS OF EDGE-TRIGGERED J-K FLOP-FLOP ARE SET TO LOGIC ZERO Collected and Composed by Bilal Farooq (bilal.zaheem@gmail.com)

17 THE FLOP-FLOP IS TRIGGERED Q=0 AND Q =1 Q=1 AND Q =0 THE OUTPUT OF FLIP-FLOP REMAINS UNCHANGED Question No: 29 ( Marks: 1 ) - Please choose one A FREQUENCY COUNTER Counts pulse width COUNTS NO. OF CLOCK PULSES IN 1 SECOND Counts high and low range of given clock pulse NONE OF GIVEN OPTIONS Question No: 30 ( Marks: 1 ) - Please choose one Stack is an acronym for FIFO memory LIFO memory Flash Memory Bust Flash Memory Question No: 31 ( Marks: 1 ) What is the role of MOS transistor in Mask ROM. Question No: 32 ( Marks: 1 ) THE GROUP OF BITS IS SERIALLY SHIFTED (RIGHT-MOST BIT FIRST) INTO AN 8- BIT PARALLEL OUTPUT SHIFT REGISTER WITH AN INITIAL STATE WHAT WILL BE THE CONTENTS OF REGISTER AFTER TWO CLOCK PULSES THE REGISTER CONTAINS? Question No: 33 ( Marks: 2 ) DRAW THE CIRCUIT DIAGRAM OF GATED S-R LATCH. Question No: 34 ( Marks: 2 ) HOW MANY BYTES WILL BE THERE IN 32 K X 4 MEMORY? Collected and Composed by Bilal Farooq (bilal.zaheem@gmail.com)

18 32 X 1024BYTES X 4 = BYTES Question No: 35 ( Marks: 3 ) THE OF FIRST 74HC163 COUNTER IS CONNECTED TO AND INPUTS OF OTHER 74HC COUNTER TO FORM A SINGLE CASCADED COUNTER Question No: 36 ( Marks: 3 ) GIVEN THE FOLLOWING STATEMENT USED IN PLD PROGRAMMING: Y PIN 23 ISTYPE COM ; Explain what does this statement mean? VARIABLE Y AT OUTPUT PIN 23 WHICH IS A COMBINATIONAL OUTPUT AVAILABLE DIRECTLY FROM THE AND-OR GATE ARRAY OUTPUT. Y = VARIABLE Y PIN 23 = PIN NUMBER 23 ISTYPE COM = OUTPUT TYPE COMBINATIONAL Question No: 37 ( Marks: 3 ) WHAT IS MEMORY EXPANSION PROCESS? Question No: 38 ( Marks: 5 ) CONSIDER THE TABLE GIVEN BELOW, APPLY THE STATE REDUCTION PROCESS ON THE STATES GIVEN IN THE TABLE AND REDUCE THE NUMBER OF STATES AS MUCH AS POSSIBLE. PRESENT STATE NEXT STATE OUTPUT X=0 X=1 X=0 X=1 A F B 0 0 B B C 1 1 C A F 0 1 D E D 1 0 E A G 0 1 F D E 0 0 G D E 0 0 Collected and Composed by Bilal Farooq (bilal.zaheem@gmail.com)

19 Question No: 39 ( Marks: 5 ) PERFORMANCE CHARACTERISTICS OF D/A CONVERTERS ARE DETERMINED BY FIVE PARAMETERS. NAME THEM. Question No: 40 ( Marks: 10 ) GIVEN BELOW IS THE CIRCUIT DIAGRAM OF BI-DIRECTIONAL 4-BIT SERIAL IN/SERIAL OUT SHIFT REGISTER. REGISTER SHIFTS DATA LEFT OR RIGHT DEPENDS ON THE RIGHT /LEFT SIGNAL APPLIED. EXPLAIN HOW THIS CIRCUIT SHIFTS DATA LEFT AND RIGHT. Question No: 41 ( Marks: 10 ) BRIEFLY EXPLAIN ADDRESS MULTIPLEXING IN DRAM. Collected and Composed by Bilal Farooq (bilal.zaheem@gmail.com)

20 Come and join us at WebLyceum For Past Papers, Quiz, Assignments, GDBs, Video Lectures etc Go to and click Register In Case of any Problem Contact Administrators Rana Muhammad Safdar Bilal Farooq Come and join us at VU Social For Non-Study Material Sharing, Chatting, etc, Go to and click Register (Weblyceum is not responsible for any solved content) Collected and Composed by Bilal Farooq

21 FINALTERM EXAMINATION Spring 2010 CS302- Digital Logic Design (Session - 4) Question No: 1 ( Marks: 1 ) - Please choose one The ANSI/IEEE Standard 754 defines a Single-Precision Floating Point format for binary numbers. 8-bit 16-bit 32-bit 64-bit Question No: 2 ( Marks: 1 ) - Please choose one The decimal 17 in BCD will be represented as Question No: 3 ( Marks: 1 ) - Please choose one The basic building block for a logical circuit is A Flip-Flop A Logical Gate An Adder None of given options Question No: 4 ( Marks: 1 ) - Please choose one The output of the expression F=A.B.C will be Logic when A=1, B=0, C=1. Undefined One Zero No Output as input is invalid. Collected and Composed by Bilal Farooq (bilal.zaheem@gmail.com)

22 Question No: 5 ( Marks: 1 ) - Please choose one is invalid number of cells in a single group formed by the adjacent cells in K-map Question No: 6 ( Marks: 1 ) - Please choose one The PROM consists of a fixed non-programmable Gate array configured as a decoder. AND OR NOT XOR Question No: 7 ( Marks: 1 ) - Please choose one is one of the examples of synchronous inputs. J-K input EN input Preset input (PRE) Clear Input (CLR) Question No: 8 ( Marks: 1 ) - Please choose one is one of the examples of asynchronous inputs. J-K input S-R input D input Clear Input (CLR) Question No: 9 ( Marks: 1 ) - Please choose one The input overrides the input Asynchronous, synchronous Synchronous, asynchronous Preset input (PRE), Clear input (CLR) Clear input (CLR), Preset input (PRE) Question No: 10 ( Marks: 1 ) - Please choose one occurs when the same clock signal arrives at different times at Collected and Composed by Bilal Farooq (bilal.zaheem@gmail.com)

23 different clock inputs due to propagation delay. Race condition Clock Skew Ripple Effect None of given options Question No: 11 ( Marks: 1 ) - Please choose one Consider an up/down counter that counts between 0 and 15, if external input(x) is 0 the counter counts upward (0000 to 1111) and if external input (X) is 1 the counter counts downward (1111 to 0000), now suppose that the present state is 1100 and X=1, the next state of the counter will be Question No: 12 ( Marks: 1 ) - Please choose one In a state diagram, the transition from a current state to the next state is determined by Current state and the inputs Current state and outputs Previous state and inputs Previous state and outputs Question No: 13 ( Marks: 1 ) - Please choose one is used to minimize the possible no. of states of a circuit. State assignment State reduction Next state table State diagram Question No: 14 ( Marks: 1 ) - Please choose one is used to simplify the circuit that determines the next state. State diagram Next state table State reduction State assignment Question No: 15 ( Marks: 1 ) - Please choose one The best state assignment tends to. Collected and Composed by Bilal Farooq (bilal.zaheem@gmail.com)

24 Maximizes the number of state variables that don t change in a group of related states Minimizes the number of state variables that don t change in a group of related states Minimize the equivalent states None of given options Question No: 16 ( Marks: 1 ) - Please choose one The output of this circuit is always. 1 0 A Question No: 17 ( Marks: 1 ) - Please choose one A 8-bit serial in / parallel out shift register contains the value 8, clock signal(s) will be required to shift the value completely out of the register Question No: 18 ( Marks: 1 ) - Please choose one 5-bit Johnson counter sequences through states Question No: 19 ( Marks: 1 ) - Please choose one Assume that a 4-bit serial in/serial out shift register is initially clear. We wish to store the nibble What will be the 4-bit pattern after the second clock pulse? (Right-most bit first.) Collected and Composed by Bilal Farooq (bilal.zaheem@gmail.com)

25 Question No: 20 ( Marks: 1 ) - Please choose one The address from which the data is read, is provided by Depends on circuitry None of given options RAM Microprocessor Question No: 21 ( Marks: 1 ) - Please choose one FIFO is an acronym for First In, First Out Fly in, Fly Out Fast in, Fast Out None of given options Question No: 22 ( Marks: 1 ) - Please choose one LUT is acronym for Look Up Table Local User Terminal Least Upper Time Period None of given options Question No: 23 ( Marks: 1 ) - Please choose one The voltage gain of the Inverting Amplifier is given by the relation Vout / Vin = - Rf / Ri Vout / Rf = - Vin / Ri Rf / Vin = - Ri / Vout Rf / Vin = Ri / Vout Question No: 24 ( Marks: 1 ) - Please choose one of a D/A converter is determined by comparing the actual output of a D/A converter with the expected output. Resolution Accuracy Quantization Missing Code Collected and Composed by Bilal Farooq (bilal.zaheem@gmail.com)

26 Question No: 25 ( Marks: 1 ) - Please choose one Above is the circuit diagram of. Asynchronous up-counter Asynchronous down-counter Synchronous up-counter Synchronous down-counter Question No: 26 ( Marks: 1 ) - Please choose one The sequence of states that are implemented by a n-bit Johnson counter is n+2 (n plus 2) 2n (n multiplied by 2) 2 n (2 raise to power n) n 2 (n raise to power 2) Question No: 27 ( Marks: 2 ) Draw the Truth-Table of NOR based S-R Latch input output S R QT QT INVALID Question No: 28 ( Marks: 2 ) Two state assignments are given in the table below. Identify which state assignment is best and why? Collected and Composed by Bilal Farooq (bilal.zaheem@gmail.com)

27 States State assignment 1 State assignment 2 A B C D Ans: State assignment 2 is best assignment it Minimizes the number of state variables that don t change in a group of related states. Question No: 29 ( Marks: 2 ) Write down at least two functions of a register. Ans: 1. Registers are operating as a coherent unit to hold and generate data. 2. registers functions also include configuration and start-up of certain features, especially during initialization, buffer storage e.g. video memory for graphics cards, input/output (I/O) of different kinds, Question No: 30 ( Marks: 2 ) Define quantization process. Ans: The process by which we can convert an analogue signal into digital signal (code) is known as quantization process. Question No: 31 ( Marks: 3 ) How can we calculate the frequency of an unknown signal? Ans: The frequency of a particular event is accomplished by counting the number of times that event occurs within a specific time interval, then dividing the count by the length of the time interval. Question No: 32 ( Marks: 3 ) Given the following statement used in PLD programming: Collected and Composed by Bilal Farooq (bilal.zaheem@gmail.com)

28 Y PIN 23 ISTYPE com ; Explain what does this statement mean? Ans: The Y variable is a Combinational output available directly from the AND-OR gate array output. The active-low or active-high output of the Registered Mode can also be specified in the declaration statement Question No: 33 ( Marks: 3 ) Explain dynamic RAM in your own words. Ans: Dram use latch to store a single bit of information.the main drawback of it id the discharge of capacitor over a period of time.here four gates are used in making a singlelatch. In terms of transistors, 4 to 6 transistors are required to implement a single storage cell. In order to build memories with higher densities, a single transistor is used to store a binary value. A single transistor can not store a binary value however it is used to charge and discharge a capacitor. The capacitor can not retain the charge, therefore it has to be periodically charged through a refresh cycle. Question No: 34 ( Marks: 5 ) You are given the Next-state table of a moor machine, using this information draw the state diagram of the machine. Present State Next State Q2 Q1 Q0 Q2 Q1 Q Question No: 35 ( Marks: 5 ) Explain Memory Select or Enable Signals Memory Select or Enable Signal: There are more than one memory chips to store program Collected and Composed by Bilal Farooq (bilal.zaheem@gmail.com)

29 Information in daily use computers. read or write operation is carried out on a single addressable location instantaneously. The unique location is accessed in one of the several memory chips, so single memory chips is selected before a read or write operation can be carried out. All memory chips have a chip enable or chip select signal which has to be activated before the memory can be accessed. Question No: 36 ( Marks: 5 ) Performance characteristics of D/A converters are determined by five parameters. Name them. Ans: Performances characteristics of D/A converters are determined by five parameters are as follow: 1. Accuracy 2. Setting time 3. Monotonicity 4. Linearity 5. Resolution Collected and Composed by Bilal Farooq (bilal.zaheem@gmail.com)

30 Come and join us at WebLyceum For Past Papers, Quiz, Assignments, GDBs, Video Lectures etc Go to and click Register In Case of any Problem Contact Administrators Rana Muhammad Safdar Bilal Farooq Come and join us at VU Social For Non-Study Material Sharing, Chatting, etc, Go to and click Register (Weblyceum is not responsible for any solved content) Collected and Composed by Bilal Farooq

31 FINALTERM EXAMINATION Fall 2009 CS302- Digital Logic Design (Session - 1) Question No: 1 ( Marks: 1 ) - Please choose one The output of an AND gate is one when All of the inputs are one Any of the input is one Any of the input is zero All the inputs are zero Question No: 2 ( Marks: 1 ) - Please choose one The OR Gate performs a Boolean function Addition Subtraction Multiplication Division Question No: 3 ( Marks: 1 ) - Please choose one A Karnaugh map is similar to a truth table because it presents all the possible values of input variables and the resulting output of each value. True False Question No: 4 ( Marks: 1 ) - Please choose one The binary numbers A = 1100 and B = 1001 are applied to the inputs of a comparator. What are the output levels? A > B = 1, A < B = 0, A < B = 1 A > B = 0, A < B = 1, A = B = 0 A > B = 1, A < B = 0, A = B = 0 A > B = 0, A < B = 1, A = B = 1 Collected and Composed by Bilal Farooq (bilal.zaheem@gmail.com)

32 Question No: 5 ( Marks: 1 ) - Please choose one AND Gate level NOT Gate level OR Gate level The diagram above shows the general implementation of form boolean arbitrary POS SOP Question No: 6 ( Marks: 1 ) - Please choose one The device shown here is most likely a Comparator Multiplexer Demultiplexer Parity generator Question No: 7 ( Marks: 1 ) - Please choose one Demultiplexer converts data to data Parallel data, serial data Serial data, parallel data Encoded data, decoded data All of the given options. Collected and Composed by Bilal Farooq (bilal.zaheem@gmail.com)

33 Question No: 8 ( Marks: 1 ) - Please choose one Flip flops are also called Bi-stable dualvibrators Bi-stable transformer Bi-stable multivibrators Bi-stable singlevibrators Question No: 9 ( Marks: 1 ) - Please choose one If S=1 and R=0, then Q(t+1) = for positive edge triggered flip-flop 0 1 Invalid Input is invalid Question No: 10 ( Marks: 1 ) - Please choose one If S=1 and R=1, then Q(t+1) = for negative edge triggered flip-flop 0 1 Invalid Input is invalid Question No: 11 ( Marks: 1 ) - Please choose one The operation of J-K flip-flop is similar to that of the SR flip-flop except that the J- K flip-flop Doesn t have an invalid state Sets to clear when both J = 0 and K = 0 It does not show transition on change in pulse It does not accept asynchronous inputs Question No: 12 ( Marks: 1 ) - Please choose one The minimum time for which the input signal has to be maintained at the input of flip-flop is called of the flip-flop. Set-up time Hold time Pulse Interval time Pulse Stability time (PST) Question No: 13 ( Marks: 1 ) - Please choose one We have a digital circuit. Different parts of circuit operate at different clock frequencies (4MHZ, 2MHZ and 1MHZ), but we have a single clock source having a fix clock frequency (4MHZ), we can get help by Collected and Composed by Bilal Farooq (bilal.zaheem@gmail.com)

34 Using S-R Flop-Flop D-flipflop J-K flip-flop T-Flip-Flop Question No: 14 ( Marks: 1 ) - Please choose one In asynchronous digital systems all the circuits change their state with respect to a common clock True False Question No: 15 ( Marks: 1 ) - Please choose one A positive edge-triggered flip-flop changes its state when Low-to-high transition of clock High-to-low transition of clock Enable input (EN) is set Preset input (PRE) is set Question No: 16 ( Marks: 1 ) - Please choose one A negative edge-triggered flip-flop changes its state when Enable input (EN) is set Preset input (PRE) is set Low-to-high transition of clock High-to-low transition of clock Question No: 17 ( Marks: 1 ) - Please choose one A flip-flop is connected to +5 volts and it draws 5 ma of current during its operation, the power dissipation of the flip-flop is 10 mw 25 mw 64 mw 1024 Question No: 18 ( Marks: 1 ) - Please choose one occurs when the same clock signal arrives at different times at different clock inputs due to propagation delay. Race condition Clock Skew Ripple Effect None of given options Collected and Composed by Bilal Farooq (bilal.zaheem@gmail.com)

35 Question No: 19 ( Marks: 1 ) - Please choose one A counter is implemented using three (3) flip-flops, possibly it will have maximum output status Question No: 20 ( Marks: 1 ) - Please choose one A divide-by-50 counter divides the input signal to a 1 Hz signal. 10 Hz 50 Hz 100 Hz 500 Hz Question No: 21 ( Marks: 1 ) - Please choose one The design and implementation of synchronous counters start from Truth table k-map state table state diagram Question No: 22 ( Marks: 1 ) - Please choose one A synchronous decade counter will have flip-flops Question No: 23 ( Marks: 1 ) - Please choose one The output of this circuit is always. Collected and Composed by Bilal Farooq (bilal.zaheem@gmail.com)

36 1 0 A Question No: 24 ( Marks: 1 ) - Please choose one At T0 the value stored in a 4-bit left shift was 1. What will be the value of register after three clock pulses? Question No: 25 ( Marks: 1 ) - Please choose one In the Q output of the last flip-flop of the shift register is connected to the data input of the first flip-flop. Moore machine Meally machine Johnson counter Ring counter Question No: 26 ( Marks: 1 ) - Please choose one In Q output of the last flip-flop of the shift register is connected to the data input of the first flip-flop of the shift register. Moore machine Meally machine Johnson counter Ring counter Question No: 27 ( Marks: 1 ) - Please choose one Which is not characteristic of a shift register? Serial in/parallel in Serial in/parallel out Parallel in/serial out Parallel in/parallel out Question No: 28 ( Marks: 1 ) - Please choose one Assume that a 4-bit serial in/serial out shift register is initially clear. We wish to Collected and Composed by Bilal Farooq (bilal.zaheem@gmail.com)

37 store the nibble What will be the 4-bit pattern after the second clock pulse? (Right-most bit first.) Question No: 29 ( Marks: 1 ) - Please choose one The of a ROM is the time it takes for the data to appear at the Data Output of the ROM chip after an address is applied at the address input lines Write Time Recycle Time Refresh Time Access Time Question No: 30 ( Marks: 1 ) - Please choose one The sequence of states that are implemented by a n-bit Johnson counter is n+2 (n plus 2) 2n (n multiplied by 2) 2 n (2 raise to power n) n 2 (n raise to power 2) Question No: 31 ( Marks: 1 ) In the statement "X PIN 22 ISTYPE reg.buffer" What is the meaning of the keyword reg.buffer Question No: 32 ( Marks: 1 ) What are the two basic operations which are performed on memory? Reading of information from the memory and Writing of data on the memory. Question No: 33 ( Marks: 2 ) Explain state assignment process. Question No: 34 ( Marks: 2 ) What is RAM Stack, which register stores the address of the top of the stack? Collected and Composed by Bilal Farooq (bilal.zaheem@gmail.com)

38 Question No: 35 ( Marks: 3 ) How can we calculate the frequency of an unknown signal? Question No: 36 ( Marks: 3 ) Explain dynamic RAM in your own words. Question No: 37 ( Marks: 3 ) Suppose a 2 bit up-down counter having states A, B, C, D. the counter counts upward when X=1 and downward when X=0. Write down IF-THEN-ELSE statements to show how present states change to next states and previous states. Question No: 38 ( Marks: 5 ) Explain memory read operation with the help of an example. Question No: 39 ( Marks: 5 ) Draw the next-state table of any sequential counter with the help of J-K flip flop transition Question No: 40 ( Marks: 10 ) You are given the diagram of up-down counter; explain how it works as an up and down counter. Collected and Composed by Bilal Farooq (bilal.zaheem@gmail.com)

39 Question No: 41 ( Marks: 10 ) Consider a state sequence a, b, c, f, d, d, c, f, d, c, a, f, d, c. Starting from initial state a, draw a table for the inputs and outputs for the state diagram given below (up to first ten transitions). Collected and Composed by Bilal Farooq (bilal.zaheem@gmail.com)

40 Come and join us at WebLyceum For Past Papers, Quiz, Assignments, GDBs, Video Lectures etc Go to and click Register In Case of any Problem Contact Administrators Rana Muhammad Safdar Bilal Farooq Come and join us at VU Social For Non-Study Material Sharing, Chatting, etc, Go to and click Register (Weblyceum is not responsible for any solved content) Collected and Composed by Bilal Farooq

41 1. The storage cell in SRAM is a flip flop a capacitor a fuse a magnetic domain CS-302 DIGITAL LOGIC DESIGN FINAL SPRING 2010 I am not sure but I feel that a question was same like that 2. What is the difference between a D latch and a D flip-flop? The D latch has a clock input. The D flip-flop has an enable input. The D latch is used for faster operation. The D flip-flop has a clock input. 3. For a positive edge-triggered J-K flip-flop with both J and K HIGH, the outputs will if the clock goes HIGH. toggle set reset not change I don t remember but I think it was Or gate but you can also think of AND gate as well. 4. The OR gate performs Boolean. multiplication subtraction division addition 5. If an S-R latch has a 1 on the S input and a 0 on the R input and then the S input goes to 0, the latch will be 1. set 2. reset 3. invalid 4. clear Collected and Composed by Bilal Farooq (bilal.zaheem@gmail.com)

42 5. Determine the values of A, B, C, and D that make the sum term equal to zero. A = 1, B = 0, C = 0, D = 0 A = 1, B = 0, C = 1, D = 0 A = 0, B = 1, C = 0, D = 0 A = 1, B = 0, C = 1, D = 1 In the below question they have given the formula Not description, but you check the formula from Handouts 6. The power dissipation, PD, of a logic gate is the product of the dc supply voltage and the peak current dc supply voltage and the average supply current ac supply voltage and the peak current ac supply voltage and the average supply current 7. A Karnaugh map is similar to a truth table because it presents all the possible values of input variables and the resulting output of each value. True False 8. NOR Gate can be used to perform the operation of AND, OR and NOT Gate True False 9. Using multiplexer as parallel to serial converter requires connected to the multiplexer A parallel to serial converter circuit A counter circuit A BCD to Decimal decoder A 2-to-8 bit decoder 10. The 3-variable Karnaugh Map (K-Map) has cells for min or max terms In designing any counter the transition from a current state to the next sate is determined by Current state and inputs Only inputs Only current state current state and outputs Collected and Composed by Bilal Farooq (bilal.zaheem@gmail.com)

43 12. Sum term (Max term) is implemented using gates OR AND NOT OR-AND 13. GIVEN THE STATE DIAGRAM OF AN UP/DOWN COUNTER, WE CAN FIND THE NEXT STATE OF A GIVEN PRESENT STATE THE PREVIOUS STATE OF A GIVEN PRESENT STATE BOTH THE NEXT AND PREVIOUS STATES OF A GIVEN STATE The state diagram shows only the inputs/outputs of a given states 14. AT T0 THE VALUE STORED IN A 4-BIT LEFT SHIFT WAS 1. WHAT WILL BE THE VALUE OF REGISTER AFTER THREE CLOCK PULSES? WHEN BOTH THE INPUTS OF EDGE-TRIGGERED J-K FLOP-FLOP ARE SET TO LOGIC ZERO THE FLOP-FLOP IS TRIGGERED Q=0 AND Q =1 Q=1 AND Q =0 THE OUTPUT OF FLIP-FLOP REMAINS UNCHANGED 16. If S=1 and R=0, then Q(t+1) = for positive edge triggered flip-flop 0 1 Invalid Input is invalid It was either above question or below one. I forget which one was given but one of them was present in paper. If S=1 and R=1, then Q(t+1) = for negative edge triggered flip-flop 0 1 Invalid Input is invalid 17. The minimum time for which the input signal has to be maintained at the input Collected and Composed by Bilal Farooq (bilal.zaheem@gmail.com)

44 of flip-flop is called of the flip-flop. Set-up time Hold time Pulse Interval time Pulse Stability time (PST) 18. We have a digital circuit. Different parts of circuit operate at different clock frequencies (4MHZ, 2MHZ and 1MHZ), but we have a single clock source having a fix clock frequency (4MHZ), we can get help by Using S-R Flop-Flop D-flipflop J-K flip-flop T-Flip-Flop 19. A counter is implemented using three (3) flip-flops, possibly it will have maximum output status In Q output of the last flip-flop of the shift register is connected to the data input of the first flip-flop of the shift register. Moore machine Meally machine Johnson counter Ring counter 21. The of a ROM is the time it takes for the data to appear at the Data Output of the ROM chip after an address is applied at the address input lines Write Time Recycle Time Refresh Time Access Time 22. Bi-stable devices remain in either of their states unless the inputs force the device to switch its state Ten Eight Three Two 23. occurs when the same clock signal arrives at different times at Collected and Composed by Bilal Farooq (bilal.zaheem@gmail.com)

45 different clock inputs due to propagation delay. Race condition Clock Skew Ripple Effect None of given options 24. The alternate solution for a multiplexer and a register circuit is Parallel in / Serial out shift register Serial in / Parallel out shift register Parallel in / Parallel out shift register Serial in / Serial Out shift register 25. Stack is an acronym for FIFO memory LIFO memory Flash Memory Bust Flash Memory 26. A full-adder has a C in = 0. What are the sum (<PRIVATE "TYPE=PICT;ALT=sigma"> ) and the carry (Cout) when A = 1 and B = 1? = 0, C out = 0 = 0, C out = 0 = 0, C out = 1 = 1, C out = 0 = 1, C out = THE GLITCHES DUE TO RACE CONDITION CAN BE AVOIDED BY USING A GATED FLIP-FLOPS PULSE TRIGGERED FLIP-FLOPS POSITIVE-EDGE TRIGGERED FLIP-FLOPS NEGATIVE-EDGE TRIGGERED FLIP-FLOPS 28. THE DESIGN AND IMPLEMENTATION OF SYNCHRONOUS COUNTERS START FROM TRUTH TABLE K-MAP STATE TABLE STATE DIAGRAM 29. THE HOURS COUNTER IS IMPLEMENTED USING Collected and Composed by Bilal Farooq (bilal.zaheem@gmail.com)

46 ONLY A SINGLE MOD-12 COUNTER IS REQUIRED MOD-10 AND MOD-6 COUNTERS MOD-10 AND MOD-2 COUNTERS A SINGLE DECADE COUNTER AND A FLIP-FLOP 30. GIVEN THE STATE DIAGRAM OF AN UP/DOWN COUNTER, WE CAN FIND THE NEXT STATE OF A GIVEN PRESENT STATE THE PREVIOUS STATE OF A GIVEN PRESENT STATE BOTH THE NEXT AND PREVIOUS STATES OF A GIVEN STATE The state diagram shows only the inputs/outputs of a given states 31. LUT is acronym for LOOK UP TABLE LOCAL USER TERMINAL LEAST UPPER TIME PERIOD NONE OF GIVEN OPTIONS 32. OF A D/A CONVERTER IS DETERMINED BY COMPARING THE ACTUAL OUTPUT OF A D/A CONVERTER WITH THE EXPECTED OUTPUT. RESOLUTION Accuracy Quantization Missing Code 33. is used to simplify the circuit that determines the next state. State diagram Next state table State reduction State assignment 34. The high density FLASH memory cell is implemented using 1 floating-gate MOS transistor 2 floating-gate MOS transistors 4 floating-gate MOS transistors 6 floating-gate MOS transistors 35. Q2 :=Q1 OR X OR Q3 The above ABEL expression will be Q2:= Q1 $ X $ Q3 Q2:= Q1 # X # Q3 Q2:= Q1 & X & Q3 Q2:= Q1! X! Q3 Collected and Composed by Bilal Farooq (bilal.zaheem@gmail.com)

47 36. Generally, the Power dissipation of devices remains constant throughout their operation. TTL CMOS 3.5 series CMOS 5 Series Power dissipation of all circuits increases with time. 37. When the control line in tri-state buffer is high the buffer operates like a gate AND OR NOT XOR v CMOS series is characterized by and as compared to the 5 v CMOS series. Low switching speeds, high power dissipation Fast switching speeds, high power dissipation Fast switching speeds, very low power dissipation Low switching speeds, very low power dissipation Explain the next-state table with the help of a table for any sequential circuit. 3 marks What kind of devices use the shift register based First In First Out (FIFO) memory? 2 Marks Differentiate between positive-edge triggered flip-flop and negative edge-triggered flip-flop. 2 marks Write down at least three characteristics of serial in / serial out 4-bit right shift register. 5 marks Explain Flash Analogue-to Digital Converter. 5 marks Explain at least two advantages of the circuit having low power consumption 3 marks Draw the circuit diagram of the 2-input 4-bit Multiplexer. Also write down its function table? 3 marks Implement a 4-bit Johnson Counter using J-K flip-flops 3 marks Collected and Composed by Bilal Farooq (bilal.zaheem@gmail.com)

48 Write down different situations where we need the sequential circuits. 2 marks What are the two basic operations which are performed on memory? How glitches due to race condition can be avoided? Explain memory write operation with the help of an example. HOW MANY BYTES WILL BE THERE IN 16 K X 4 MEMORY? 2 MARKS Collected and Composed by Bilal Farooq (bilal.zaheem@gmail.com)

49 Come and join us at WebLyceum For Past Papers, Quiz, Assignments, GDBs, Video Lectures etc Go to and click Register In Case of any Problem Contact Administrators Rana Muhammad Safdar Bilal Farooq Come and join us at VU Social For Non-Study Material Sharing, Chatting, etc, Go to and click Register (Weblyceum is not responsible for any solved content) Collected and Composed by Bilal Farooq

50 FINALTERM EXAMINATION Fall 2009 CS302- Digital Logic Design (Session - 2) Question No: 1 ( Marks: 1 ) - Please choose one Caveman number system is Base number system Question No: 2 ( Marks: 1 ) - Please choose one The output of an XOR gate is zero (0) when I) All the inputs are zero II) Any of the inputs is zero III) Any of the inputs is one IV) All the inputs are one I Only IV Only I and IV only II and III only Question No: 3 ( Marks: 1 ) - Please choose one The decimal 17 in BCD will be represented as 10001(right opt is not given) Question No: 4 ( Marks: 1 ) - Please choose one A Karnaugh map is similar to a truth table because it presents all the possible values of input variables and the resulting output of each value. True False Collected and Composed by Bilal Farooq (bilal.zaheem@gmail.com)

51 Question No: 5 ( Marks: 1 ) - Please choose one The simplest and most commonly used Decoders are the Decoders n to 2 n (n-1) to 2 n (n-1) to (2 n -1) n to 2 n -1 Question No: 6 ( Marks: 1 ) - Please choose one The Encoder is used as a keypad encoder. 2-to-8 encoder 4-to-16 encoder BCD-to-Decimal Decimal-to-BCD Priority Question No: 7 ( Marks: 1 ) - Please choose one 3-to-8 decoder can be used to implement Standard SOP and POS Boolean expressions True False Question No: 8 ( Marks: 1 ) - Please choose one If S=1 and R=0, then Q(t+1) = for positive edge triggered flip-flop 0 1 Invalid Input is invalid Question No: 9 ( Marks: 1 ) - Please choose one If the S and R inputs of the gated S-R latch are connected together using a gate then there is only a single input to the latch. The input is represented by D instead of S or R (A gated D-Latch) AND OR NOT XOR Collected and Composed by Bilal Farooq (bilal.zaheem@gmail.com)

52 Question No: 10 ( Marks: 1 ) - Please choose one In asynchronous digital systems all the circuits change their state with respect to a common clock True False Question No: 11 ( Marks: 1 ) - Please choose one The low to high or high to low transition of the clock is considered to be a(n) State Edge Trigger One-shot Question No: 12 ( Marks: 1 ) - Please choose one A positive edge-triggered flip-flop changes its state when Low-to-high transition of clock High-to-low transition of clock Enable input (EN) is set Preset input (PRE) is set Question No: 13 ( Marks: 1 ) - Please choose one RCO Stands for Reconfiguration Counter Output Reconfiguration Clock Output Ripple Counter Output Ripple Clock Output Question No: 14 ( Marks: 1 ) - Please choose one Bi-stable devices remain in either of their states unless the inputs force the device to switch its state Ten Eight Three Two Question No: 15 ( Marks: 1 ) - Please choose one is one of the examples of asynchronous inputs. J-K input S-R input Collected and Composed by Bilal Farooq (bilal.zaheem@gmail.com)

53 D input Clear Input (CLR) Question No: 16 ( Marks: 1 ) - Please choose one occurs when the same clock signal arrives at different times at different clock inputs due to propagation delay. Race condition Clock Skew Ripple Effect None of given options Question No: 17 ( Marks: 1 ) - Please choose one A transparent mode means The changes in the data at the inputs of the latch are seen at the output The changes in the data at the inputs of the latch are not seen at the output Propagation Delay is zero (Output is immediately changed when clock signal is applied) Input Hold time is zero (no need to maintain input after clock transition) Question No: 18 ( Marks: 1 ) - Please choose one In outputs depend only on the current state. Mealy machine Moore Machine State Reduction table State Assignment table Question No: 19 ( Marks: 1 ) - Please choose one The alternate solution for a multiplexer and a register circuit is Parallel in / Serial out shift register Serial in / Parallel out shift register Parallel in / Parallel out shift register Serial in / Serial Out shift register Question No: 20 ( Marks: 1 ) - Please choose one The alternate solution for a demultiplexer-register combination circuit is Parallel in / Serial out shift register Serial in / Parallel out shift register Collected and Composed by Bilal Farooq (bilal.zaheem@gmail.com)

54 Parallel in / Parallel out shift register Serial in / Serial Out shift register Question No: 21 ( Marks: 1 ) - Please choose one In asynchronous transmission when the transmission line is idle, It is set to logic low It is set to logic high Remains in previous state State of transmission line is not used to start transmission Question No: 22 ( Marks: 1 ) - Please choose one Smallest unit of binary data is a Bit Nibble Byte Word Question No: 23 ( Marks: 1 ) - Please choose one A Nibble consists of bits Question No: 24 ( Marks: 1 ) - Please choose one A GAL is essentially a. Non-reprogrammable PAL PAL that is programmed only by the manufacturer Very large PAL Reprogrammable PAL Question No: 25 ( Marks: 1 ) - Please choose one A 8-bit serial in / parallel out shift register contains the value 8, clock signal(s) will be required to shift the value completely out of the register Collected and Composed by Bilal Farooq (bilal.zaheem@gmail.com)

55 Question No: 26 ( Marks: 1 ) - Please choose one DRAM stands for Dynamic RAM Data RAM Demoduler RAM None of given options Question No: 27 ( Marks: 1 ) - Please choose one FIFO is an acronym for First In, First Out Fly in, Fly Out Fast in, Fast Out None of given options Question No: 28 ( Marks: 1 ) - Please choose one In the circuit diagram of 3-bit synchronous counter shown above, The red rectangle would be replaced by which gate? AND OR NAND XNOR Question No: 29 ( Marks: 1 ) - Please choose one The sequence of states that are implemented by a n-bit Johnson counter is n+2 (n plus 2) 2n (n multiplied by 2) Collected and Composed by Bilal Farooq (bilal.zaheem@gmail.com)

56 2 n (2 raise to power n) n 2 (n raise to power 2) Question No: 30 ( Marks: 1 ) - Please choose one Stack is an acronym for FIFO memory LIFO memory Flash Memory Bust Flash Memory Question No: 31 ( Marks: 1 ) Generally two types of D/A Converters are used. Name at least one. One type of D/A converter is electromechanical-also called shaft- or position-todigital-and electronic. Question No: 32 ( Marks: 1 ) Name at least one device that converts signals form analog to digital or from digital to analogue. A codec (coder/decoder) is a device that converts an analog signal into a digital signal. Mobile phone converts signals from digital to analogue and from analogue to digital. Question No: 33 ( Marks: 2 ) How glitches due to race condition can be avoided? A new clocking scheme is developed to produce race-free, glitch-free outputs of synchronous digital systems. The maximum input clock frequency for race-free operation is calculated as a single-phase system. Output signals are sampled at twice the input clock frequency, at time instants when the glitches are not there. Using the scheme, glitches generated anywhere within a quarter (T/4) of the input clock period (T) can be eliminated. The margin T/4 is large enough for most practical systems. Hence the scheme is of universal application as verified by the simulation of two 3 µm CMOS gate array ASICs, designed using VINYAS CAD tools. Collected and Composed by Bilal Farooq (bilal.zaheem@gmail.com)

57 Question No: 34 ( Marks: 2 ) For a four bit serial in/serial out shift register is initially set to We want to enter the value How many clock pulses will be required to enter the data and then again bring the contents of register to After 8 clock pulses the 4-bit data is completely shifted out of the shift register. The register is first cleared, forcing all four outputs to zero. The input data is then applied sequentially to the D input of the first flip-flop on the left (FF0). During each clock pulse, one bit is transmitted from left to right Question No: 35 ( Marks: 3 ) Define down counter. In digital logic and computing, a counter is a device which stores (and sometimes displays) the number of times a particular event or process has occurred, often in relationship to a clock signal. Down counters, are those which decrease (decrement) in value. Decrement the counter by one (if it's already zero, this leaves it unchanged) Question No: 36 ( Marks: 3 ) Explain Rotate Left Operation with the help of diagram. The serial output of the register is connected to the serial input of the register. By applying clock pulses data is shifted left. The data shifted out of the serial out pin at the left hand side is re-circulated back into the shift register input at the right hand side. Thus the data is rotated left within the register. Collected and Composed by Bilal Farooq (bilal.zaheem@gmail.com)

58 Question No: 37 ( Marks: 3 ) Explain dynamic RAM in your own words. DRAM Dynamic RAM (DRAM) is a type of RAM that contains a single transistor and a capacitor. DRAM is smaller than SRAM, and therefore can store more data in a smaller area. Because of the charge and discharge times of the capacitor, however, DRAM tends to be slower than SRAM. Many modern types of Main Memory are based on DRAM design because of the high memory densities. Because DRAM is simpler than SRAM, it is typically cheaper to produce. A popular type of RAM, SDRAM, is a variant of DRAM and is not related to SRAM. As digital circuits continue to grow smaller and faster as per Moore's Law, the speed of DRAM is not increasing as rapidly. This means that as time goes on, the speed difference between the processor and the RAM units (so long as the RAM is based on DRAM or variants) will continue to increase, and communications between the two units becomes more inefficient. Question No: 38 ( Marks: 5 ) Explain memory write operation with the help of an example. Memory write operation: The method employs a two-step technique which allows the out-of-order completion of read and write operations. When a write operation requires a resource needed for the completion of a read operation, the data being written is stored in a write data buffer in the memory device. The write data is stored in the buffer until a datapath is available to communicate the data to the memory device's memory core. Once the resource is free (or the memory device, or its controller force the write to complete) the data is written to the memory core of the memory device using the now-free datapath. A diagnostic memory write operation uses the same CSRs as the read. The data is written to the CSR data register, and the address at which the data is to be stored is written to the CSR diagnostic address register. Collected and Composed by Bilal Farooq (bilal.zaheem@gmail.com)

59 Question No: 39 ( Marks: 5 ) Convert the following state diagram into state table Present state Next stat Q2 Q1 Q0 Q2 Q1 Q Question No: 40 ( Marks: 10 ) Given below is the circuit diagram of parallel in / serial out shift register. Explain how this circuit works (serially shifts the data) D 0 D 1 D 2 D 3 SHIFT /LOAD CLK D SET Q flip-flop 1 Q CLR D SET Q flip-flop 2 Q CLR D SET Q Q 0 Q 1 Q 2 flip-flop 3 Q CLR D SET Q flip-flop 4 Q CLR Q 3 Serial Data Out Question No: 41 ( Marks: 10 ) Briefly explain address multiplexing in DRAM. Collected and Composed by Bilal Farooq (bilal.zaheem@gmail.com)

60 Come and join us at WebLyceum For Past Papers, Quiz, Assignments, GDBs, Video Lectures etc Go to and click Register In Case of any Problem Contact Administrators Rana Muhammad Safdar Bilal Farooq Come and join us at VU Social For Non-Study Material Sharing, Chatting, etc, Go to and click Register (Weblyceum is not responsible for any solved content) Collected and Composed by Bilal Farooq

61 CS302 Final Exam (Fall 2009) Total questions 41 Objective questions 31 Subjective question 10 Question (Marks 1) The group of bits is serially shifted (right-most bit first) into an 5-bit parallel output shift register with an initial state What will be the contents of register after three clock pulses the register contains? Question (Marks 1) How clock skew is eliminated? Question (Marks 2) Give the circuit diagram of the Gated SR Latch. Question (Marks 2) How erase operation works in context to Flash memory? Question (Marks 3) How the frequency of an unknown signal is calculated? Collected and Composed by Bilal Farooq

62 Question (Marks 3) Given the statement in PLD programming; Y PIN 23 ISTYPE COM ; Explain what does this statement mean? Question: 38 (Marks 5) Flash analogue to digital converter Question: 39 (Marks 5) How 12(1100) is detected by the third NAND Gate? Why clock signal is added to all the three gates? Question: 40 (Marks 10) The One-Shot is triggered by applying a short pulse at the input of the NOR gate at time interval t1. The One-Shot is in its stable state with output at logic zero at time interval < t1. The logic high triggering pulse at the input of the NOR gate sets its output to Collected and Composed by Bilal Farooq (bilal.zaheem@gmail.com)

63 logic low. Give step wise working of One-Shot Mono-stable multi-vibrator after triggering pulse is applied. Question: 41 (Marks 10) Give pin names of 4-bit Synchronous Counter 74HC163 Collected and Composed by Bilal Farooq

64 Come and join us at WebLyceum For Past Papers, Quiz, Assignments, GDBs, Video Lectures etc Go to and click Register In Case of any Problem Contact Administrators Rana Muhammad Safdar Bilal Farooq Come and join us at VU Social For Non-Study Material Sharing, Chatting, etc, Go to and click Register (Weblyceum is not responsible for any solved content) Collected and Composed by Bilal Farooq

65 FINALTERM EXAMINATION Spring 2010 CS302- Digital Logic Design (Session - 1) Question No: 1 ( Marks: 1 ) - Please choose one "A + B = B + A" is Demorgan s Law Distributive Law Commutative Law Associative Law Question No: 2 ( Marks: 1 ) - Please choose one The diagram given below represents Demorgans law Associative law Product of sum form Sum of product form Question No: 3 ( Marks: 1 ) - Please choose one Following is standard POS expression True False Question No: 4 ( Marks: 1 ) - Please choose one An alternate method of implementing Comparators which allows the Comparators to be easily cascaded without the need for extra logic gates is Using a single comparator Collected and Composed by Bilal Farooq (bilal.zaheem@gmail.com)

66 Using Iterative Circuit based Comparators Connecting comparators in vertical hierarchy Extra logic gates are always required. Question No: 5 ( Marks: 1 ) Demultiplexer is also called - Please choose one Data selector Data router Data distributor Data encoder Question No: 6 ( Marks: 1 ) - Please choose one The operation of J-K flip-flop is similar to that of the SR flip-flop except that the J-K flip-flop Doesn t have an invalid state Sets to clear when both J = 0 and K = 0 It does not show transition on change in pulse It does not accept asynchronous inputs Question No: 7 ( Marks: 1 ) - Please choose one A positive edge-triggered flip-flop changes its state when Low-to-high transition of clock High-to-low transition of clock Enable input (EN) is set Preset input (PRE) is set Question No: 8 ( Marks: 1 ) - Please choose one A flip-flop is connected to +5 volts and it draws 5 ma of current during its operation, the power dissipation of the flip-flop is 10 mw 25 mw 64 mw 1024 Question No: 9 ( Marks: 1 ) - Please choose one counters as the name indicates are not triggered simultaneously. Asynchronous Collected and Composed by Bilal Farooq (bilal.zaheem@gmail.com)

67 Synchronous Positive-Edge triggered Negative-Edge triggered Question No: 10 ( Marks: 1 ) - Please choose one 74HC163 has two enable input pins which are and ENP, ENT ENI, ENC ENP, ENC ENT, ENI Question No: 11 ( Marks: 1 ) - Please choose one The divide-by-60 counter in digital clock is implemented by using two cascading counters: Mod-6, Mod-10 Mod-50, Mod-10 Mod-10, Mod-50 Mod-50, Mod-6 Question No: 12 ( Marks: 1 ) - Please choose one In a state diagram, the transition from a current state to the next state is determined by Current state and the inputs Current state and outputs Previous state and inputs Previous state and outputs Question No: 13 ( Marks: 1 ) - Please choose one A synchronous decade counter will have flip-flops Collected and Composed by Bilal Farooq (bilal.zaheem@gmail.com)

68 Question No: 14 ( Marks: 1 ) - Please choose one is used to minimize the possible no. of states of a circuit. State assignment State reduction Next state table State diagram Question No: 15 ( Marks: 1 ) - Please choose one A multiplexer with a register circuit converts Serial data to parallel Parallel data to serial Serial data to serial Parallel data to parallel Question No: 16 ( Marks: 1 ) - Please choose one The alternate solution for a demultiplexer-register combination circuit is Parallel in / Serial out shift register Serial in / Parallel out shift register Parallel in / Parallel out shift register Serial in / Serial Out shift register Question No: 17 ( Marks: 1 ) - Please choose one A GAL is essentially a. Non-reprogrammable PAL PAL that is programmed only by the manufacturer Very large PAL Reprogrammable PAL Question No: 18 ( Marks: 1 ) - Please choose one The output of this circuit is always. Collected and Composed by Bilal Farooq (bilal.zaheem@gmail.com)

69 1 0 A Question No: 19 ( Marks: 1 ) - Please choose one DRAM stands for Dynamic RAM Data RAM Demoduler RAM None of given options Question No: 20 ( Marks: 1 ) - Please choose one in, all the columns in the same row are either read or written. Sequential Access MOS Access FAST Mode Page Access None of given options Question No: 21 ( Marks: 1 ) - Please choose one FIFO is an acronym for First In, First Out Fly in, Fly Out Fast in, Fast Out None of given options Question No: 22 ( Marks: 1 ) - Please choose one In order to synchronize two devices that consume and produce data at different rates, we can use Read Only Memory Fist In First Out Memory Flash Memory Fast Page Access Mode Memory Collected and Composed by Bilal Farooq (bilal.zaheem@gmail.com)

70 Question No: 23 ( Marks: 1 ) - Please choose one A frequency counter Counts pulse width Counts no. of clock pulses in 1 second Counts high and low range of given clock pulse None of given options Question No: 24 ( Marks: 1 ) - Please choose one The sequence of states that are implemented by a n-bit Johnson counter is n+2 (n plus 2) 2n (n multiplied by 2) 2 n (2 raise to power n) n 2 (n raise to power 2) Question No: 25 ( Marks: 1 ) - Please choose one Stack is an acronym for FIFO memory LIFO memory Flash Memory Bust Flash Memory Question No: 26 ( Marks: 1 ) - Please choose one The 4-bit 2 s complement representation of +5 is Question No: 27 ( Marks: 2 ) Explain the erase operation in context of Flash Memory. Question No: 28 ( Marks: 2 ) Explain the difference between 1-to-4 Demultiplexer and 2-to-4 Binary Decoder? Collected and Composed by Bilal Farooq (bilal.zaheem@gmail.com)

71 Question No: 29 ( Marks: 2 ) Some of the counters (e.g. 74HC163) are called pre-set counters. why? Question No: 30 ( Marks: 2 ) How many bytes will be there in 32 K x 8 memory? Question No: 31 ( Marks: 3 ) Differentiate between truth table and next-state table Question No: 32 ( Marks: 3 ) Name the three types of errors Analogue to Digital converters exhibit during their conversion operation. Question No: 33 ( Marks: 3 ) How can a serial in/parallel out register be used as a serial in/serial out register? Question No: 34 ( Marks: 5 ) Explain the implementation of First In First Out (FIFO) Memory by using RAM. Question No: 35 ( Marks: 5 ) Explain memory read operation with the help of an example. Question No: 36 ( Marks: 5 ) Explain the next-state table with the help of a table for any sequential circuit. Collected and Composed by Bilal Farooq (bilal.zaheem@gmail.com)

72 Come and join us at WebLyceum For Past Papers, Quiz, Assignments, GDBs, Video Lectures etc Go to and click Register In Case of any Problem Contact Administrators Rana Muhammad Safdar Bilal Farooq Come and join us at VU Social For Non-Study Material Sharing, Chatting, etc, Go to and click Register (Weblyceum is not responsible for any solved content) Collected and Composed by Bilal Farooq

73 FINALTERM EXAMINATION Fall 2009 CS302- Digital Logic Design (Session - 1) Question No: 1 ( Marks: 1 ) - Please choose one The output of an AND gate is one when All of the inputs are one Any of the input is one Any of the input is zero All the inputs are zero Question No: 2 ( Marks: 1 ) - Please choose one The OR Gate performs a Boolean function Addition Subtraction Multiplication Division Question No: 3 ( Marks: 1 ) - Please choose one A Karnaugh map is similar to a truth table because it presents all the possible values of input variables and the resulting output of each value. True False Question No: 4 ( Marks: 1 ) - Please choose one The binary numbers A = 1100 and B = 1001 are applied to the inputs of a comparator. What are the output levels? A > B = 1, A < B = 0, A < B = 1 A > B = 0, A < B = 1, A = B = 0 A > B = 1, A < B = 0, A = B = 0 A > B = 0, A < B = 1, A = B = 1 Collected and Composed by Bilal Farooq (bilal.zaheem@gmail.com)

74 Question No: 5 ( Marks: 1 ) - Please choose one AND Gate level NOT Gate level OR Gate level The diagram above shows the general implementation of form boolean arbitrary POS SOP Question No: 6 ( Marks: 1 ) - Please choose one The device shown here is most likely a Comparator Multiplexer Demultiplexer Parity generator Question No: 7 ( Marks: 1 ) - Please choose one Demultiplexer converts data to data Parallel data, serial data Serial data, parallel data Encoded data, decoded data All of the given options. Collected and Composed by Bilal Farooq (bilal.zaheem@gmail.com)

75 Question No: 8 ( Marks: 1 ) - Please choose one Flip flops are also called Bi-stable dualvibrators Bi-stable transformer Bi-stable multivibrators Bi-stable singlevibrators Question No: 9 ( Marks: 1 ) - Please choose one If S=1 and R=0, then Q(t+1) = for positive edge triggered flip-flop 0 1 Invalid Input is invalid Question No: 10 ( Marks: 1 ) - Please choose one If S=1 and R=1, then Q(t+1) = for negative edge triggered flip-flop 0 1 Invalid Input is invalid Question No: 11 ( Marks: 1 ) - Please choose one The operation of J-K flip-flop is similar to that of the SR flip-flop except that the J- K flip-flop Doesn t have an invalid state Sets to clear when both J = 0 and K = 0 It does not show transition on change in pulse It does not accept asynchronous inputs Question No: 12 ( Marks: 1 ) - Please choose one The minimum time for which the input signal has to be maintained at the input of flip-flop is called of the flip-flop. Set-up time Hold time Pulse Interval time Pulse Stability time (PST) Question No: 13 ( Marks: 1 ) - Please choose one We have a digital circuit. Different parts of circuit operate at different clock frequencies (4MHZ, 2MHZ and 1MHZ), but we have a single clock source having a fix clock frequency (4MHZ), we can get help by Collected and Composed by Bilal Farooq (bilal.zaheem@gmail.com)

76 Using S-R Flop-Flop D-flipflop J-K flip-flop T-Flip-Flop Question No: 14 ( Marks: 1 ) - Please choose one In asynchronous digital systems all the circuits change their state with respect to a common clock True False Question No: 15 ( Marks: 1 ) - Please choose one A positive edge-triggered flip-flop changes its state when Low-to-high transition of clock High-to-low transition of clock Enable input (EN) is set Preset input (PRE) is set Question No: 16 ( Marks: 1 ) - Please choose one A negative edge-triggered flip-flop changes its state when Enable input (EN) is set Preset input (PRE) is set Low-to-high transition of clock High-to-low transition of clock Question No: 17 ( Marks: 1 ) - Please choose one A flip-flop is connected to +5 volts and it draws 5 ma of current during its operation, the power dissipation of the flip-flop is 10 mw 25 mw 64 mw 1024 Question No: 18 ( Marks: 1 ) - Please choose one occurs when the same clock signal arrives at different times at different clock inputs due to propagation delay. Race condition Clock Skew Ripple Effect None of given options Collected and Composed by Bilal Farooq (bilal.zaheem@gmail.com)

77 Question No: 19 ( Marks: 1 ) - Please choose one A counter is implemented using three (3) flip-flops, possibly it will have maximum output status Question No: 20 ( Marks: 1 ) - Please choose one A divide-by-50 counter divides the input signal to a 1 Hz signal. 10 Hz 50 Hz 100 Hz 500 Hz Question No: 21 ( Marks: 1 ) - Please choose one The design and implementation of synchronous counters start from Truth table k-map state table state diagram Question No: 22 ( Marks: 1 ) - Please choose one A synchronous decade counter will have flip-flops Question No: 23 ( Marks: 1 ) - Please choose one The output of this circuit is always. Collected and Composed by Bilal Farooq (bilal.zaheem@gmail.com)

78 1 0 A Question No: 24 ( Marks: 1 ) - Please choose one At T0 the value stored in a 4-bit left shift was 1. What will be the value of register after three clock pulses? Question No: 25 ( Marks: 1 ) - Please choose one In the Q output of the last flip-flop of the shift register is connected to the data input of the first flip-flop. Moore machine Meally machine Johnson counter Ring counter Question No: 26 ( Marks: 1 ) - Please choose one In Q output of the last flip-flop of the shift register is connected to the data input of the first flip-flop of the shift register. Moore machine Meally machine Johnson counter Ring counter Question No: 27 ( Marks: 1 ) - Please choose one Which is not characteristic of a shift register? Serial in/parallel in Serial in/parallel out Parallel in/serial out Parallel in/parallel out Question No: 28 ( Marks: 1 ) - Please choose one Assume that a 4-bit serial in/serial out shift register is initially clear. We wish to Collected and Composed by Bilal Farooq (bilal.zaheem@gmail.com)

79 store the nibble What will be the 4-bit pattern after the second clock pulse? (Right-most bit first.) Question No: 29 ( Marks: 1 ) - Please choose one The of a ROM is the time it takes for the data to appear at the Data Output of the ROM chip after an address is applied at the address input lines Write Time Recycle Time Refresh Time Access Time Question No: 30 ( Marks: 1 ) - Please choose one The sequence of states that are implemented by a n-bit Johnson counter is n+2 (n plus 2) 2n (n multiplied by 2) 2 n (2 raise to power n) n 2 (n raise to power 2) Question No: 31 ( Marks: 1 ) In the statement "X PIN 22 ISTYPE reg.buffer" What is the meaning of the keyword reg.buffer Question No: 32 ( Marks: 1 ) What are the two basic operations which are performed on memory? Reading of information from the memory and Writing of data on the memory. Question No: 33 ( Marks: 2 ) Explain state assignment process. Question No: 34 ( Marks: 2 ) What is RAM Stack, which register stores the address of the top of the stack? Collected and Composed by Bilal Farooq (bilal.zaheem@gmail.com)

80 Question No: 35 ( Marks: 3 ) How can we calculate the frequency of an unknown signal? Question No: 36 ( Marks: 3 ) Explain dynamic RAM in your own words. Question No: 37 ( Marks: 3 ) Suppose a 2 bit up-down counter having states A, B, C, D. the counter counts upward when X=1 and downward when X=0. Write down IF-THEN-ELSE statements to show how present states change to next states and previous states. Question No: 38 ( Marks: 5 ) Explain memory read operation with the help of an example. Question No: 39 ( Marks: 5 ) Draw the next-state table of any sequential counter with the help of J-K flip flop transition Question No: 40 ( Marks: 10 ) You are given the diagram of up-down counter; explain how it works as an up and down counter. Collected and Composed by Bilal Farooq (bilal.zaheem@gmail.com)

81 Question No: 41 ( Marks: 10 ) Consider a state sequence a, b, c, f, d, d, c, f, d, c, a, f, d, c. Starting from initial state a, draw a table for the inputs and outputs for the state diagram given below (up to first ten transitions). Collected and Composed by Bilal Farooq (bilal.zaheem@gmail.com)

82 Come and join us at WebLyceum For Past Papers, Quiz, Assignments, GDBs, Video Lectures etc Go to and click Register In Case of any Problem Contact Administrators Rana Muhammad Safdar Bilal Farooq Come and join us at VU Social For Non-Study Material Sharing, Chatting, etc, Go to and click Register (Weblyceum is not responsible for any solved content) Collected and Composed by Bilal Farooq

83 FINALTERM EXAMINATION Spring 2010 CS302- Digital Logic Design (Session - 4) Question No: 1 ( Marks: 1 ) - Please choose one The ANSI/IEEE Standard 754 defines a Single-Precision Floating Point format for binary numbers. 8-bit 16-bit 32-bit 64-bit Question No: 2 ( Marks: 1 ) - Please choose one The decimal 17 in BCD will be represented as Question No: 3 ( Marks: 1 ) - Please choose one The basic building block for a logical circuit is A Flip-Flop A Logical Gate An Adder None of given options Question No: 4 ( Marks: 1 ) - Please choose one The output of the expression F=A.B.C will be Logic when A=1, B=0, C=1. Undefined One Zero No Output as input is invalid. Collected and Composed by Bilal Farooq (bilal.zaheem@gmail.com)

84 Question No: 5 ( Marks: 1 ) - Please choose one is invalid number of cells in a single group formed by the adjacent cells in K-map Question No: 6 ( Marks: 1 ) - Please choose one The PROM consists of a fixed non-programmable Gate array configured as a decoder. AND OR NOT XOR Question No: 7 ( Marks: 1 ) - Please choose one is one of the examples of synchronous inputs. J-K input EN input Preset input (PRE) Clear Input (CLR) Question No: 8 ( Marks: 1 ) - Please choose one is one of the examples of asynchronous inputs. J-K input S-R input D input Clear Input (CLR) Question No: 9 ( Marks: 1 ) - Please choose one The input overrides the input Asynchronous, synchronous Synchronous, asynchronous Preset input (PRE), Clear input (CLR) Clear input (CLR), Preset input (PRE) Question No: 10 ( Marks: 1 ) - Please choose one occurs when the same clock signal arrives at different times at Collected and Composed by Bilal Farooq (bilal.zaheem@gmail.com)

85 different clock inputs due to propagation delay. Race condition Clock Skew Ripple Effect None of given options Question No: 11 ( Marks: 1 ) - Please choose one Consider an up/down counter that counts between 0 and 15, if external input(x) is 0 the counter counts upward (0000 to 1111) and if external input (X) is 1 the counter counts downward (1111 to 0000), now suppose that the present state is 1100 and X=1, the next state of the counter will be Question No: 12 ( Marks: 1 ) - Please choose one In a state diagram, the transition from a current state to the next state is determined by Current state and the inputs Current state and outputs Previous state and inputs Previous state and outputs Question No: 13 ( Marks: 1 ) - Please choose one is used to minimize the possible no. of states of a circuit. State assignment State reduction Next state table State diagram Question No: 14 ( Marks: 1 ) - Please choose one is used to simplify the circuit that determines the next state. State diagram Next state table State reduction State assignment Question No: 15 ( Marks: 1 ) - Please choose one The best state assignment tends to. Collected and Composed by Bilal Farooq (bilal.zaheem@gmail.com)

86 Maximizes the number of state variables that don t change in a group of related states Minimizes the number of state variables that don t change in a group of related states Minimize the equivalent states None of given options Question No: 16 ( Marks: 1 ) - Please choose one The output of this circuit is always. 1 0 A Question No: 17 ( Marks: 1 ) - Please choose one A 8-bit serial in / parallel out shift register contains the value 8, clock signal(s) will be required to shift the value completely out of the register Question No: 18 ( Marks: 1 ) - Please choose one 5-bit Johnson counter sequences through states Question No: 19 ( Marks: 1 ) - Please choose one Assume that a 4-bit serial in/serial out shift register is initially clear. We wish to store the nibble What will be the 4-bit pattern after the second clock pulse? (Right-most bit first.) Collected and Composed by Bilal Farooq (bilal.zaheem@gmail.com)

87 Question No: 20 ( Marks: 1 ) - Please choose one The address from which the data is read, is provided by Depends on circuitry None of given options RAM Microprocessor Question No: 21 ( Marks: 1 ) - Please choose one FIFO is an acronym for First In, First Out Fly in, Fly Out Fast in, Fast Out None of given options Question No: 22 ( Marks: 1 ) - Please choose one LUT is acronym for Look Up Table Local User Terminal Least Upper Time Period None of given options Question No: 23 ( Marks: 1 ) - Please choose one The voltage gain of the Inverting Amplifier is given by the relation Vout / Vin = - Rf / Ri Vout / Rf = - Vin / Ri Rf / Vin = - Ri / Vout Rf / Vin = Ri / Vout Question No: 24 ( Marks: 1 ) - Please choose one of a D/A converter is determined by comparing the actual output of a D/A converter with the expected output. Resolution Accuracy Quantization Missing Code Collected and Composed by Bilal Farooq (bilal.zaheem@gmail.com)

88 Question No: 25 ( Marks: 1 ) - Please choose one Above is the circuit diagram of. Asynchronous up-counter Asynchronous down-counter Synchronous up-counter Synchronous down-counter Question No: 26 ( Marks: 1 ) - Please choose one The sequence of states that are implemented by a n-bit Johnson counter is n+2 (n plus 2) 2n (n multiplied by 2) 2 n (2 raise to power n) n 2 (n raise to power 2) Question No: 27 ( Marks: 2 ) Draw the Truth-Table of NOR based S-R Latch input output S R QT QT INVALID Question No: 28 ( Marks: 2 ) Two state assignments are given in the table below. Identify which state assignment is best and why? Collected and Composed by Bilal Farooq (bilal.zaheem@gmail.com)

89 States State assignment 1 State assignment 2 A B C D Ans: State assignment 2 is best assignment it Minimizes the number of state variables that don t change in a group of related states. Question No: 29 ( Marks: 2 ) Write down at least two functions of a register. Ans: 1. Registers are operating as a coherent unit to hold and generate data. 2. registers functions also include configuration and start-up of certain features, especially during initialization, buffer storage e.g. video memory for graphics cards, input/output (I/O) of different kinds, Question No: 30 ( Marks: 2 ) Define quantization process. Ans: The process by which we can convert an analogue signal into digital signal (code) is known as quantization process. Question No: 31 ( Marks: 3 ) How can we calculate the frequency of an unknown signal? Ans: The frequency of a particular event is accomplished by counting the number of times that event occurs within a specific time interval, then dividing the count by the length of the time interval. Question No: 32 ( Marks: 3 ) Given the following statement used in PLD programming: Collected and Composed by Bilal Farooq (bilal.zaheem@gmail.com)

90 Y PIN 23 ISTYPE com ; Explain what does this statement mean? Ans: The Y variable is a Combinational output available directly from the AND-OR gate array output. The active-low or active-high output of the Registered Mode can also be specified in the declaration statement Question No: 33 ( Marks: 3 ) Explain dynamic RAM in your own words. Ans: Dram use latch to store a single bit of information.the main drawback of it id the discharge of capacitor over a period of time.here four gates are used in making a singlelatch. In terms of transistors, 4 to 6 transistors are required to implement a single storage cell. In order to build memories with higher densities, a single transistor is used to store a binary value. A single transistor can not store a binary value however it is used to charge and discharge a capacitor. The capacitor can not retain the charge, therefore it has to be periodically charged through a refresh cycle. Question No: 34 ( Marks: 5 ) You are given the Next-state table of a moor machine, using this information draw the state diagram of the machine. Present State Next State Q2 Q1 Q0 Q2 Q1 Q Question No: 35 ( Marks: 5 ) Explain Memory Select or Enable Signals Memory Select or Enable Signal: There are more than one memory chips to store program Collected and Composed by Bilal Farooq (bilal.zaheem@gmail.com)

91 Information in daily use computers. read or write operation is carried out on a single addressable location instantaneously. The unique location is accessed in one of the several memory chips, so single memory chips is selected before a read or write operation can be carried out. All memory chips have a chip enable or chip select signal which has to be activated before the memory can be accessed. Question No: 36 ( Marks: 5 ) Performance characteristics of D/A converters are determined by five parameters. Name them. Ans: Performances characteristics of D/A converters are determined by five parameters are as follow: 1. Accuracy 2. Setting time 3. Monotonicity 4. Linearity 5. Resolution Collected and Composed by Bilal Farooq (bilal.zaheem@gmail.com)

92 Come & Join Us at VUSTUDENTS.net For Assignment Solution, GDB, Online Quizzes, Helping Study material, Past Solved Papers, Solved MCQs, Current Papers, E-Books & more. Go to and click Sing up to register. VUSTUENTS.NET is a community formed to overcome the disadvantages of distant learning and virtual environment, where pupils don t have any formal contact with their mentors, This community provides its members with the solution to current as well as the past Assignments, Quizzes, GDBs, and Papers. This community also facilitates its members in resolving the issues regarding subject and university matters, by providing text e-books, notes, and helpful conversations in chat room as well as study groups. Only members are privileged with the right to access all the material, so if you are not a member yet, kindly SIGN UP to get access to the resources of VUSTUDENTS.NET»» Regards»» VUSTUDENTS.NET TEAM. Virtual University of Pakistan Come & Join Us at

93 My today cs301 final paper by I remember some mcqs from my paper which I m sharing here. 1. Whatever is the size of the tree, the search is performed after traversing up to. Maximum level. (log2n) Which one of the following is NOT the property of equivalence relation? Reflexive Symmetric Transitive Associative Binary Search is an algorithm of searching, used with the data. Sorted Unsorted Heterogeneous Random If one pointers of the node in a binary tree are NULL then it will be a/an. Inner node Leaf node Root node None of the given options Come & Join Us at

94 Suppose we are sorting an array of eight integers using quick sort, and we have just finished the first partitioning with the array looking like this: Which statement is correct? The pivot could be either the 7 or the 9. The pivot could be the 7, but it is not the 9. The pivot is not the 7, but it could be the 9. Neither the 7 nor the 9 is the pivot. (the pivot value will be 1 or 5) Which one of the following algorithms is least efficient, Quick Sort Insertion Sort Merge Sort Bubble Sort (NOT Confirmed) Mergesort makes two recursive calls. Which statement is true after these recursive calls finish, but before the merge step? Elements in the first half of the array are less than or equal to elements in the second half of the array. None of the given options. The array elements form a heap. Elements in the second half of the array are less than or equal to elements in the first half of the array. The data of the problem is of 2GB and the hard disk is of 1GB capacity, to solve this problem we should Use better data structures Increase the hard disk space Use the better algorithm Use as much data as we can store on the hard disk Come & Join Us at

95 If a max heap is implemented using a partially filled array called data, and the array contains n elements (n > 0), where is the entry with the greatest value? data[1] data[n-1] data[n] data[2*n+1] Union is a time operation. Constant Polynomial Exponential None of the given options Which of the following is NOT a correct statement about Table ADT. In a table, the type of information in columns may be different. A table consists of several columns, known as entities. The row of a table is called a record. A major use of table is in databases where we build and use tables for keeping information. Consider a min heap, represented by the following array: 3,4,6,7,5 After calling the function deletemin().which of the following is the updated min heap? 4,6,7,5 6,7,5,4 4,5,6,7 4,6,5,7 Come & Join Us at

96 What requirement is placed on an array, so that binary search may be used to locate an entry? The array elements must form a heap. The array must have at least 2 entries. The array must be sorted. The array s size must be a power of two. A binary relation R over S is called an equivalence relation if it has following property(s) Reflexivity Symmetry Transitivity All of the given options If there are N elements in an array then the number of maximum steps needed to find an element using Binary Search is. N N 2 Nlog 2 N log 2 N While building Huffman encoding tree the new node that is the result of joining two nodes has the frequency. Equal to the small frequency Equal to the greater Equal to the sum of the two frequencies Equal to the difference of the two frequencies Come & Join Us at

97 Which of the following statements is correct property of binary trees? A binary tree with N internal nodes has N+1 internal links. A binary tree with N external nodes has 2N internal nodes. A binary tree with N internal nodes has N+1 external nodes. None of above statement is a property of the binary tree A complete binary tree is a tree that is filled, with the possible exception of the bottom level. partially completely incompletely partly Consider the following infix expression: x y * a + b / c Which of the following is a correct equivalent expression(s) for the above? x y -a * b +c / x *y a - b c / + x y a * - b c / + x y a * - b/ + c Remember in your prayers Come & Join Us at

98 Come and join us at WebLyceum For Past Papers, Quiz, Assignments, GDBs, Video Lectures etc Go to and click Register In Case of any Problem Contact Administrators Rana Muhammad Safdar Bilal Farooq Come and join us at VU Social For Non-Study Material Sharing, Chatting, etc, Go to and click Register (Weblyceum is not responsible for any solved content) Collected and Composed by Bilal Farooq

99 Question No: 27 ( Marks: 2 ) Draw the Truth-Table of NOR based S-R Latch input Output S R QT QT INVALID Question No: 28 ( Marks: 2 ) Two state assignments are given in the table below. Identify which state assignment is best and why? States State assignment 1 State assignment 2 A B C D Ans: State assignment 2 is best assignment it Minimizes the number of state variables that don t change in a group of related states. Question No: 29 ( Marks: 2 ) Write down at least two functions of a register. Ans: 1. Registers are operating as a coherent unit to hold and generate data. 2. registers functions also include configuration and start-up of certain features, especially during initialization, buffer storage e.g. video memory for graphics cards, input/output (I/O) of different kinds, Collected and Composed by Bilal Farooq (bilal.zaheem@gmail.com)

100 Question No: 30 ( Marks: 2 ) Define quantization process. Ans: The process by which we can convert an analogue signal into digital signal (code) is known as quantization process. Question No: 31 ( Marks: 3 ) How can we calculate the frequency of an unknown signal? Ans: The frequency of a particular event is accomplished by counting the number of times that event occurs within a specific time interval, then dividing the count by the length of the time interval. Question No: 32 ( Marks: 3 ) Given the following statement used in PLD programming: Y PIN 23 ISTYPE com ; Explain what does this statement mean? Ans: The Y variable is a Combinational output available directly from the AND-OR gate array output. The active-low or active-high output of the Registered Mode can also be specified in the declaration statement Question No: 33 ( Marks: 3 ) Explain dynamic RAM in your own words. Ans: Dynamic random access memory (DRAM) is a type of random access memory that stores each bit of data in a separate capacitor within an integrated circuit. Since real capacitors leak charge and the information finally fades unless the capacitor charge is refreshed sometimes. Collected and Composed by Bilal Farooq (bilal.zaheem@gmail.com)

101 Question No: 34 ( Marks: 5 ) You are given the Next-state table of a moor machine, using this information draw the state diagram of the machine. Ans: Present State Next State Q2 Q1 Q0 Q2 Q1 Q State diagram of a Moore Machine Question No: 35 ( Marks: 5 ) Explain Memory Select or Enable Signals Memory Select or Enable Signal: There are more than one memory chips to store program Information in daily use computers. read or write operation is carried out on a single addressable location instantaneously. The unique location is accessed in one of the several memory chips, so single memory chips is selected before a read or write operation can be carried out. All Collected and Composed by Bilal Farooq (bilal.zaheem@gmail.com)

102 memory chips have a chip enable or chip select signal which has to be activated before the memory can be accessed Flash memory operations Ans: FLASH Memory Operations FLASH Memory operations are classified into 1. Programming Operation 2. Read Operation 3. Erase Operation enable signal and memory select signal Ans: Memory Select or Enable Signal In a computer system there are many memory chips to store program information. At any particular instant a read or write operation is carried out on a single addressable location. The unique location can only be accessed in one of the several memory chips, thus a single memory chip has to be selected before a read or write operation can be carried out. All memory chips have a chip enable or chip select signal which has to be activated before the memory can be accessed. Flash analogue to digital convertor Ans: Flash Analogue-to Digital Converter: The Flash Analogue-to Digital converter is based on a resistor potential divider. Where multiple resistors of the same value form a voltage divider. A reference voltage is applied at one end of the potential divider which divides the voltage equally across all the resistors. The input analogue voltage is applied at the noninverting inputs of a set of Op-Amp based comparators. The inverting input of each comparator is connected to the resistive voltage divider which provides reference voltages for all the comparators. If the input voltage is larger than the reference voltage the output of the comparator is logic high otherwise it is logic low. The outputs of all the comparators are connected to the input of a precedence encoder which converts the comparator outputs to a binary coded equivalent value. State table and state diagram. how many bytes 16 K memory has Ans: 16 x 1024 = Draw the state diagram of 3-bit UP counter (5) Ans: Collected and Composed by Bilal Farooq (bilal.zaheem@gmail.com)

103 State diagram of a 3-bit Up-Counter What is ROM.Brefily Explain. (5) ANS: ROM Read-Only Memory: A ROM contains permanent data that can not be changed. Thus ROM memory does not allow write operation. A ROM stores data that are used repeatedly in system applications, such as tables, conversions and programmed instructions for system initialization and operation. ROMs retain data when the power is turned off. ROMs are of different types. Mask ROM: Data is permanently stored during the manufacturing process. PROM: Programmable ROM allows storage of data by the user using a PROM programmer. The PROM once programmed stores the data permanently. EPROM: Erasable PROM allows erasing of stored data and reprogramming. UV EPROM: Data is erased by exposing the PROM to Ultraviolet light. EEPROM: Electrically Erasable PROM is erased electrically. EEPROM allows in circuit programming and does not need to be removed from the circuit for erasure or programming. Explain Binary-Weighted-Input Digital to Analogu Converter. (5) Ans: Collected and Composed by Bilal Farooq (bilal.zaheem@gmail.com)

104 Binary-Weighted-Input Digital to Analogue Converter: The Binary-Weighted-Input Digital to Analogue converter is based on a summer circuit which sums the input currents based on the binary input and represents it as a voltage output. In the Binary-Weighted-Input Method a resistor network is used with resistor values representing the binary weights of the input bits of the digital code. The binary is applied at the resistor inputs. A current will flow through the resistor if the input voltage applied is logic high. No current flows through a resistor if the input voltage applied is logic low. The magnitude of the current flowing through each resistor depends upon the value of the resistor. The total current flowing through each resistor adds up and flows through the feedback resistor Rf which is connected between the output and the inverting input of the Op-Amp. The output voltage of the Op-Amp is determined by the voltage drop across the Rf resistance. Draw the Truth table for NOR gate (2) ANS: Inputs Output A B F Write the 1 difference between Johnson counter and Ring Counter. (3mark) Ans: In a Johnson counter, the Q (Q compliment) output of the last flip-flop In a Ring Counter, the Q output of the last of the shift register is connected to the flip-flop of the shift register is data input of the first flip-flop. connected to the data input of the first flip-flop of the shift register. What is Ripple counter (3) Ans: Ripple Counters: Ripple counters are implemented by connecting together multiple flip flops together. The triggering clock signal is connected to the clock input of the first flip flop. The clock inputs of the remaining flip flops are connected to the Q or Q output of the previous flip flop. On a clock transition at the clock input of the first flip flops the output state of the flip flop changes. With the transition in the Collected and Composed by Bilal Farooq (bilal.zaheem@gmail.com)

105 output state of the first flip flops there is also a transition at the clock input to the second flip flop as the output of the first flip flop is connected to the clock input of the second flip flop. Explain Flash Memory. (3) Flash memory is a non-volatile memory device that retains its data when the power is off. The device is similar to EPROM with the exception that it can be electrically format, whereas an EPROM must be exposed to ultra-violet light to format. Question No: 32 ( Marks: 1 ) What are the two basic operations which are performed on memory? Reading of information from the memory and Writing of data on the memory. Question No: 33 ( Marks: 2 ) Explain state assignment process. Ans: Each state in a sequential circuit is identified by a unique combination of binary bits. Unless the output of the sequential is directly taken form the flip flop outputs such as counters the states can be selected to allow minimum bit changes when changing from one state to the other. Keeping the bits changes to minimum when changing from one state to the next and results in simpler combinational circuits that determine the next state. Question No: 34 ( Marks: 2 ) What is RAM Stack, which register stores the address of the top of the stack? Ans: Shift Register based stack implementation finds use in specialized digital systems. A practical way to implement the program stack which a program under execution uses to access variables is by means of the RAM memory. The stack is known as a RAM stack. A special purpose register known as the Stack Pointer Register stores the address of the top of the stack and a reserved area in the RAM memory. Collected and Composed by Bilal Farooq (bilal.zaheem@gmail.com)

106 Question No: 35 ( Marks: 3 ) How can we calculate the frequency of an unknown signal? Ans: The frequency of the unknown signal can be calculated by counting the number of clock pulses of the unknown signal and dividing the count number by the time interval in which the clock pulses are counted. Question No: 38 ( Marks: 5 ) Explain memory read operation with the help of an example. Ans: Memory Read operation Memory Read operation is carried out by first selecting the memory chip by activating the Memory Select signal. The Read signal is asserted to configure the memory circuitry for reading data from the memory. Example: An address (1011) is applied on the Address Lines. The internal address decoder of the memory decodes the address and selects one unique row from which data is read. Question No: 31 ( Marks: 1 ) What is the role of MOS transistor in Mask ROM. Ans: The storage cell in a Mask ROM is implemented using a MOS transistor. Question No: 39 ( Marks: 5 ) Draw the next-state table of any sequential counter with the help of J-K flip flop transition ANS: Present State Next State J-K flip-flop inputs Q2 Q1 Q0 Q2 Q1 Q0 J2 K2 J1 K1 J0 K X 0 X 1 X X 1 X X X X 0 1 X X X 1 X X 0 0 X 1 X X 0 1 X X X 0 X 0 1 X x 1 X 1 X 1 Collected and Composed by Bilal Farooq (bilal.zaheem@gmail.com)

107 Question No: 33 ( Marks: 2 ) DRAW THE CIRCUIT DIAGRAM OF GATED S-R LATCH. Ans: S 3 1 Q EN R 4 Gated S-R Latch 2 Q HOW MANY BYTES WILL BE THERE IN 32 K X 4 MEMORY? 32 X 1024BYTES X 4 = BYTES Question No: 36 ( Marks: 3 ) GIVEN THE FOLLOWING STATEMENT USED IN PLD PROGRAMMING: Y PIN 23 ISTYPE COM ; Explain what does this statement mean? VARIABLE Y AT OUTPUT PIN 23 WHICH IS A COMBINATIONAL OUTPUT AVAILABLE DIRECTLY FROM THE AND-OR GATE ARRAY OUTPUT. Y = VARIABLE Y PIN 23 = PIN NUMBER 23 ISTYPE COM = OUTPUT TYPE COMBINATIONAL Question No: 37 ( Marks: 3 ) WHAT IS MEMORY EXPANSION PROCESS? Collected and Composed by Bilal Farooq (bilal.zaheem@gmail.com)

108 Digital systems require different amounts of memory in the form of RAM and ROM memory depending upon specific applications. A computer requires large amounts of RAM memory to store multiple application programs data and the operating system. In a computer the RAM is reserved to support the video memory, stack and I/O buffers. The ROM used by a computer is relatively very small as it stores few bytes of code used to boot the computer system on power up. Micro controller based digital system designed for specific applications do not have large memory requirement and in fact the total memory requirement of such micro controller systems is met by on board RAM and ROM having a total storage capacity of few hundred of kilobytes. Computer and Digital systems have the capability to allow RAM memory to be expanded as the needed arises by inserting extra memory in dedicated memory sockets on the computer motherboard. Question No: 39 ( Marks: 5 ) PERFORMANCE CHARACTERISTICS OF D/A CONVERTERS ARE DETERMINED BY FIVE PARAMETERS. NAME THEM. Ans: 1. Resolution 2. Accuracy 3. Linearity 4. Monotonicity 5. Settling Time Question No: 33 ( Marks: 2 ) What kind of devices use the shift register based First In First Out (FIFO) memory? Ans: FIFOs are used commonly in electronic circuits for buffering and flow control which is from hardware to software. In hardware form a FIFO primarily consists of a set of read and write pointers, storage and control logic. Storage may be SRAM, flip-flops, latches or any other suitable form of storage. For FIFOs of nontrivial size a dual-port SRAM is usually used where one port is used for writing and the other is used for reading. Collected and Composed by Bilal Farooq (bilal.zaheem@gmail.com)

109 Question No: 34 ( Marks: 2 ) Differentiate between positive-edge triggered flip-flop and negative edgetriggered flip-flop. Ans: A negative edge triggered flip-flop generates an output pulse in response to a negative edge of a clock signal. A first set of nodes receives data input signals, and a second set of nodes receives select input signals for selecting one data input signal as a selected data input signal. The clock node receives the clock signal which has a positive edge and a negative edge. A header circuit connects to the second set of nodes and to the clock node, and integrates the clock signal with the select input signals to generate at least one control signal. A pulse generator circuit connects to the first set of nodes, the header circuit and the output node. The pulse generator circuit generates an output pulse on the output node in response to a control signal and the selected data input signal. The operation and truth table for a negative edge-triggered flip-flop are the same as those for a positive except that the falling edge of the clock pulse is the triggering edge. Question No: 35 ( Marks: 3 ) Name some of the important operating characteristics of flip-flops Ans; The operating characteristics mention here apply to all flip-flops regardless of the particular form of the circuit. They are typically found in data sheets for integrated circuits. They specify the performance, operating requirements, and operating limitations of the circuit. Propagation Delay Time - is the interval of time required after an input signal has been applied for the resulting output change to occur. Set-Up Time - is the minimum interval required for the logic levels to be maintained constantly on the inputs (J and K, or S and R, or D) prior to the triggering edge of the clock pulse in order for the levels to be reliably clocked into the flip-flop. Hold Time - is the minimum interval required for the logic levels to remain on the inputs after the triggering edge of the clock pulse in order for the levels to be reliably clocked into the flip-flop. Maximum Clock Frequency - is the highest rate that a flip-flop can be reliably triggered. Power Dissipation - is the total power consumption of the device. Pulse Widths - are the minimum pulse widths specified by the manufacturer for the Clock, SET and CLEAR inputs. Collected and Composed by Bilal Farooq (bilal.zaheem@gmail.com)

110 Question No: 36 ( Marks: 3 ) What is memory expansion process? Computers ad digital system have the capability to to allow RAM memory to be extended as the needed arise by inserting extra memory in dedicated memory sockets on the computer motherboard.th e total amount of memory that is supported by any digital system depends upon the size of the address bus of micro processor or a micro controller. Question No: 37 ( Marks: 3 ) Write down at least three characteristics of serial in / serial out 4-bit right shift register. Ans: A serial-in/serial-out shift register has a clock input, a data input, and a data output from the last stage. In general, the other stage outputs are not available Otherwise, it would be a serial-in, parallel-out shift register.. The waveforms below are applicable to either one of the preceding two versions of the serial-in, serial-out shift register. The three pairs of arrows show that a three stage shift register temporarily stores 3-bits of data and delays it by three clock periods from input to output. Question No: 38 ( Marks: 5 ) Explain Flash Analogue-to Digital Converter. Flash Analogue-to Digital Converter: A flash analogue to digital converter is the fastest type of converter we use. Like the successive approximation converter it works by comparing the input signal to a reference voltage, but a flash converter has as many comparators as there are steps in the comparison. An 8-bit converter, therefore, has 2 to the power 8, or 256, comparators. The resistor net and comparators provide an input to the combinational logic circuit, so the conversion time is just the propagation delay through the network - it is not limited by the clock rate or some convergence sequence. It is the fastest type of ADC available, but requires a comparator for each value of output (63 for 6-bit, 255 for 8-bit, etc.) Such ADCs are available in IC form up to 8-bit and 10-bit flash ADCs (1023 comparators) are planned. The encoder logic executes a truth table to convert the ladder of inputs to the binary number output. Question No: 39 ( Marks: 5 ) Explain the next-state table with the help of a table for any sequential circuit. Collected and Composed by Bilal Farooq (bilal.zaheem@gmail.com)

111 State Table The state table representation of a sequential circuit consists of three sections labelled present state, next state and output. The present state designates the state of flip-flops before the occurrence of a clock pulse. The next state shows the states of flip-flops after the clock pulse, and the output section lists the value of the output variables during the present state. Present state Next state x=0 Next state x=1 Out put x=0 Out put x=1 Q1Q Question No: 40 ( Marks: 10 ) Why the inputs of S-R, J-K and D-flip-flops are called synchronous inputs. What are asynchronous inputs, explain effect of PRE and CLR inputs on flip-flops. Ans: The normal data inputs to a flip flop (D, S and R, or J and K) are referred to as synchronous inputs because they have effect on the outputs (Q and not-q) only in step, or in sync, with the clock signal transitions. These extra inputs that I now bring to your attention are called asynchronous because they can set or reset the flip-flop regardless of the status of the clock signal. Typically, they're called preset and clear: Collected and Composed by Bilal Farooq (bilal.zaheem@gmail.com)

112 When the preset input is activated, the flip-flop will be set (Q=1, not-q=0) regardless of any of the synchronous inputs or the clock. When the clear input is activated, the flip-flop will be reset (Q=0, not-q=1), regardless of any of the synchronous inputs or the clock. So, what happens if both preset and clear inputs are activated? Surprise, surprise: we get an invalid state on the output, where Q and not-q go to the same state, the same as our old friend, the S-R latch! Preset and clear inputs find use when multiple flip-flops are ganged together to perform a function on a multi-bit binary word, and a single line is needed to set or reset them all at once. Asynchronous inputs, just like synchronous inputs, can be engineered to be active-high or active-low. If they're active-low, there will be an inverting bubble at that input lead on the block symbol, just like the negative edge-trigger clock inputs. Sometimes the designations "PRE" and "CLR" will be shown with inversion bars above them, to further denote the negative logic of these inputs: Collected and Composed by Bilal Farooq (bilal.zaheem@gmail.com)

113 Question No: 41 ( Marks: 10 ) Explain the following in context of Memory: Address signals A memory circuit, in using address transition detection to equilibrate bit lines, generates a summation address transition signal for the row address as well as a summation address transition signal for the column address. There is a transition detector for each address signal. The outputs of the transition detectors for the row address signals are summed in at least two logic stages using CMOS logic gates to generate the summation address signal for the row address. Similarly, the outputs of the transition detectors for the column address signals are summed in at least two logic stages using CMOS logic gates to generate the summation address signal for the column address. Data signals Method of how information is transferred; usually it is transferred in binary code in signals or pulses. A phase lock oscillator includes a phase discriminator that develops an error signal by comparing a clock from a voltage controlled oscillator with incoming random data bits. In the absence of data, the phase lock oscillator is inactive. However, when data is sensed, a logic and delay network in the phase discriminator develops an error voltage of suitable polarity and amplitude, indicative of the lead or lag between the data and clock signals. The error voltage is applied to the voltage controlled oscillator to modify the frequency and phase of the clock. Furthermore, first and second integrations are provided by the phase discriminator and an integrator respectively so that the steady state phase error is held close to zero. It is known that spurious variations in the mechanical or electrical parameters of a storage system cause unwanted displacement and shift of the signal being processed, thus necessitating frequency and phase compensation. To this end, synchronizing systems, servosystems, phase lock oscillator circuits, separation circuits and the like are employed. Collected and Composed by Bilal Farooq (bilal.zaheem@gmail.com)

114 Come and join us at WebLyceum For Past Papers, Quiz, Assignments, GDBs, Video Lectures etc Go to and click Register In Case of any Problem Contact Administrators Rana Muhammad Safdar Bilal Farooq Come and join us at VU Social For Non-Study Material Sharing, Chatting, etc, Go to and click Register (Weblyceum is not responsible for any solved content) Collected and Composed by Bilal Farooq

115 FINALTERM EXAMINATION Fall 2009 CS302- Digital Logic Design (Session - 4) Question No: 1 ( Marks: 1 ) - Please choose one NOR Gate can be used to perform the operation of AND, OR and NOT Gate FALSE TRUE Question No: 2 ( Marks: 1 ) - Please choose one The output of an XNOR gate is 1 when I) All the inputs are zero II) Any of the inputs is zero III) Any of the inputs is one IV) All the inputs are one I Only IV Only I and IV only II and III only Question No: 3 ( Marks: 1 ) - Please choose one NAND gate is formed by connecting AND Gate and then NOT Gate NOT Gate and then AND Gate AND Gate and then OR Gate OR Gate and then AND Gate Question No: 4 ( Marks: 1 ) - Please choose one Consider A=1,B=0,C=1. A, B and C represent the input of three bit NAND gate the output of the NAND gate will be Zero One Undefined No output as input is invalid Collected and Composed by Bilal Farooq (bilal.zaheem@gmail.com)

116 Question No: 5 ( Marks: 1 ) - Please choose one The capability that allows the PLDs to be programmed after they have been installed on a circuit board is called Radiation-Erase programming method (REPM) In-System Programming (ISP) In-chip Programming (ICP) Electronically-Erase programming method(eepm) Question No: 6 ( Marks: 1 ) - Please choose one The ABEL symbol for OR operation is! & # $ Question No: 7 ( Marks: 1 ) - Please choose one If S=1 and R=1, then Q(t+1) = for negative edge triggered flip-flop 0 1 Invalid Input is invalid Question No: 8 ( Marks: 1 ) - Please choose one The operation of J-K flip-flop is similar to that of the SR flip-flop except that the J- K flip-flop Doesn t have an invalid state Sets to clear when both J = 0 and K = 0 It does not show transition on change in pulse It does not accept asynchronous inputs Question No: 9 ( Marks: 1 ) - Please choose one For a gated D-Latch if EN=1 and D=1 then Q(t+1) = 0 1 Q(t) Invalid Question No: 10 ( Marks: 1 ) - Please choose one In asynchronous digital systems all the circuits change their state with respect to a common clock Collected and Composed by Bilal Farooq (bilal.zaheem@gmail.com)

117 True False Question No: 11 ( Marks: 1 ) - Please choose one A positive edge-triggered flip-flop changes its state when Low-to-high transition of clock High-to-low transition of clock Enable input (EN) is set Preset input (PRE) is set Question No: 12 ( Marks: 1 ) - Please choose one is one of the examples of asynchronous inputs. J-K input S-R input D input Clear Input (CLR) Question No: 13 ( Marks: 1 ) - Please choose one The input overrides the input Asynchronous, synchronous Synchronous, asynchronous Preset input (PRE), Clear input (CLR) Clear input (CLR), Preset input (PRE) Question No: 14 ( Marks: 1 ) - Please choose one Following Is the circuit diagram of mono-stable device which gate will be replaced by the red colored rectangle in the circuit. AND NAND NOR XNOR Question No: 15 ( Marks: 1 ) - Please choose one In outputs depend only on the combination of current state and inputs. Collected and Composed by Bilal Farooq (bilal.zaheem@gmail.com)

118 Mealy machine Moore Machine State Reduction table State Assignment table Question No: 16 ( Marks: 1 ) - Please choose one is used to simplify the circuit that determines the next state. State diagram Next state table State reduction State assignment Question No: 17 ( Marks: 1 ) - Please choose one A multiplexer with a register circuit converts Serial data to parallel Parallel data to serial Serial data to serial Parallel data to parallel Question No: 18 ( Marks: 1 ) - Please choose one In asynchronous transmission when the transmission line is idle, It is set to logic low It is set to logic high Remains in previous state State of transmission line is not used to start transmission Question No: 19 ( Marks: 1 ) - Please choose one In the following statement Z PIN 20 ISTYPE reg.invert ; The keyword reg.invert indicates An inverted register input An inverted register input at pin 20 Active-high Registered Mode output Active-low Registered Mode output Question No: 20 ( Marks: 1 ) - Please choose one A Nibble consists of bits Collected and Composed by Bilal Farooq (bilal.zaheem@gmail.com)

119 Question No: 21 ( Marks: 1 ) - Please choose one The output of this circuit is always. 1 0 A Question No: 22 ( Marks: 1 ) - Please choose one At T0 the value stored in a 4-bit left shift was 1. What will be the value of register after three clock pulses? Question No: 23 ( Marks: 1 ) - Please choose one A bidirectional 4-bit shift register is storing the nibble Its input is LOW. The nibble 0111 is waiting to be entered on the serial data-input line. After two clock pulses, the shift register is storing Question No: 24 ( Marks: 1 ) - Please choose one The high density FLASH memory cell is implemented using 1 floating-gate MOS transistor 2 floating-gate MOS transistors Collected and Composed by Bilal Farooq (bilal.zaheem@gmail.com)

120 4 floating-gate MOS transistors 6 floating-gate MOS transistors Question No: 25 ( Marks: 1 ) - Please choose one In order to synchronize two devices that consume and produce data at different rates, we can use Read Only Memory Fist In First Out Memory Flash Memory Fast Page Access Mode Memory Question No: 26 ( Marks: 1 ) - Please choose one If the FIFO Memory output is already filled with data then It is locked; no data is allowed to enter It is not locked; the new data overwrites the previous data. Previous data is swapped out of memory and new data enters None of given options Question No: 27 ( Marks: 1 ) - Please choose one The process of converting the analogue signal into a digital representation (code) is known as Strobing Amplification Quantization Digitization Question No: 28 ( Marks: 1 ) - Please choose one Above is the circuit diagram of. Asynchronous up-counter Asynchronous down-counter Collected and Composed by Bilal Farooq (bilal.zaheem@gmail.com)

121 Synchronous up-counter Synchronous down-counter Question No: 29 ( Marks: 1 ) - Please choose one ( A + B)(A + B + C)(A + C) is an example of Product of sum form Sum of product form Demorgans law Associative law Question No: 30 ( Marks: 1 ) - Please choose one Q2 :=Q1 OR X OR Q3 The above ABEL expression will be Q2:= Q1 $ X $ Q3 Q2:= Q1 # X # Q3 Q2:= Q1 & X & Q3 Q2:= Q1! X! Q3 Question No: 31 ( Marks: 1 ) How the hour counter is implemented in a digital clock (i.e. how many counters are used and what is their configuration Mod)? Question No: 32 ( Marks: 1 ) The top of the stack contains the value 5 and bottom of the stack contains the value 6, a pop (read data from stack) operation was executed, which value would be read? Question No: 33 ( Marks: 2 ) What kind of devices use the shift register based First In First Out (FIFO) memory? FIFOs are used commonly in electronic circuits for buffering and flow control which is from hardware to software. In hardware form a FIFO primarily consists of a set of read and write pointers, storage and control logic. Storage may be Collected and Composed by Bilal Farooq (bilal.zaheem@gmail.com)

122 SRAM, flip-flops, latches or any other suitable form of storage. For FIFOs of nontrivial size a dual-port SRAM is usually used where one port is used for writing and the other is used for reading. Question No: 34 ( Marks: 2 ) Differentiate between positive-edge triggered flip-flop and negative edgetriggered flip-flop. A negative edge triggered flip-flop generates an output pulse in response to a negative edge of a clock signal. A first set of nodes receives data input signals, and a second set of nodes receives select input signals for selecting one data input signal as a selected data input signal. The clock node receives the clock signal which has a positive edge and a negative edge. A header circuit connects to the second set of nodes and to the clock node, and integrates the clock signal with the select input signals to generate at least one control signal. A pulse generator circuit connects to the first set of nodes, the header circuit and the output node. The pulse generator circuit generates an output pulse on the output node in response to a control signal and the selected data input signal. The operation and truth table for a negative edge-triggered flip-flop are the same as those for a positive except that the falling edge of the clock pulse is the triggering edge. Question No: 35 ( Marks: 3 ) Name some of the important operating characteristics of flip-flops The operating characteristics mention here apply to all flip-flops regardless of the particular form of the circuit. They are typically found in data sheets for integrated circuits. They specify the performance, operating requirements, and operating limitations of the circuit. Propagation Delay Time - is the interval of time required after an input signal has been applied for the resulting output change to occur. Set-Up Time - is the minimum interval required for the logic levels to be maintained constantly on the inputs (J and K, or S and R, or D) prior to the triggering edge of the clock pulse in order for the levels to be reliably clocked into the flip-flop. Hold Time - is the minimum interval required for the logic levels to remain on the inputs after the triggering edge of the clock pulse in order for the levels to be reliably clocked into the flip-flop. Maximum Clock Frequency - is the highest rate that a flip-flop can be reliably triggered. Collected and Composed by Bilal Farooq (bilal.zaheem@gmail.com)

123 Power Dissipation - is the total power consumption of the device. Pulse Widths - are the minimum pulse widths specified by the manufacturer for the Clock, SET and CLEAR inputs. Question No: 36 ( Marks: 3 ) What is memory expansion process? Computers ad digital system have the capability to to allow RAM memory to be extended as the needed arise by inserting extra memory in dedicated memory sockets on the computer motherboard.th e total amount of memory that is supported by any digital system depends upon the size of the address bus of micro processor or a micro controller. Question No: 37 ( Marks: 3 ) Write down at least three characteristics of serial in / serial out 4-bit right shift register. Ans: A serial-in/serial-out shift register has a clock input, a data input, and a data output from the last stage. In general, the other stage outputs are not available Otherwise, it would be a serial-in, parallel-out shift register.. The waveforms below are applicable to either one of the preceding two versions of the serial-in, serial-out shift register. The three pairs of arrows show that a three stage shift register temporarily stores 3-bits of data and delays it by three clock periods from input to output. Question No: 38 ( Marks: 5 ) Explain Flash Analogue-to Digital Converter. Flash Analogue-to Digital Converter: A flash analogue to digital converter is the fastest type of converter we use. Like the successive approximation converter it works by comparing the input signal to a reference voltage, but a flash converter has as many comparators as there are steps in the comparison. An 8-bit converter, therefore, has 2 to the power 8, or 256, comparators. The resistor net and comparators provide an input to the combinational logic circuit, so the conversion time is just the propagation delay through the network - it is not limited by the clock rate or some convergence sequence. It is the fastest type of ADC available, but requires a comparator for each value of output (63 for 6-bit, 255 for 8-bit, etc.) Such ADCs are available in IC form up to 8-bit and 10-bit flash ADCs (1023 comparators) are planned. The encoder logic executes a truth table to convert the ladder of inputs to the binary number output. Collected and Composed by Bilal Farooq (bilal.zaheem@gmail.com)

124 Question No: 39 ( Marks: 5 ) Explain the next-state table with the help of a table for any sequential circuit. Ans State Table The state table representation of a sequential circuit consists of three sections labelled present state, next state and output. The present state designates the state of flip-flops before the occurrence of a clock pulse. The next state shows the states of flip-flops after the clock pulse, and the output section lists the value of the output variables during the present state. Present state Q1Q2 Next state x=0 Next state x=1 Out put x=0 Out put x= Question No: 40 ( Marks: 10 ) Why the inputs of S-R, J-K and D-flip-flops are called synchronous inputs. What are asynchronous inputs, explain effect of PRE and CLR inputs on flip-flops. Ans: The normal data inputs to a flip flop (D, S and R, or J and K) are referred to as synchronous inputs because they have effect on the outputs (Q and not-q) only in step, or in sync, with the clock signal transitions. These extra inputs that I now bring to your attention are called asynchronous because they can set or reset the flip-flop regardless of the status of the clock signal. Typically, they're called preset and clear: Collected and Composed by Bilal Farooq (bilal.zaheem@gmail.com)

125 When the preset input is activated, the flip-flop will be set (Q=1, not-q=0) regardless of any of the synchronous inputs or the clock. When the clear input is activated, the flip-flop will be reset (Q=0, not-q=1), regardless of any of the synchronous inputs or the clock. So, what happens if both preset and clear inputs are activated? Surprise, surprise: we get an invalid state on the output, where Q and not-q go to the same state, the same as our old friend, the S-R latch! Preset and clear inputs find use when multiple flip-flops are ganged together to perform a function on a multi-bit binary word, and a single line is needed to set or reset them all at once. Asynchronous inputs, just like synchronous inputs, can be engineered to be activehigh or active-low. If they're active-low, there will be an inverting bubble at that input lead on the block symbol, just like the negative edge-trigger clock inputs. Sometimes the designations "PRE" and "CLR" will be shown with inversion bars above them, to further denote the negative logic of these inputs: Collected and Composed by Bilal Farooq (bilal.zaheem@gmail.com)

126 Question No: 41 ( Marks: 10 ) Explain the following in context of Memory: Address signals A memory circuit, in using address transition detection to equilibrate bit lines, generates a summation address transition signal for the row address as well as a summation address transition signal for the column address. There is a transition detector for each address signal. The outputs of the transition detectors for the row address signals are summed in at least two logic stages using CMOS logic gates to generate the summation address signal for the row address. Similarly, the outputs of the transition detectors for the column address signals are summed in at least two logic stages using CMOS logic gates to generate the summation address signal for the column address. Data signals Method of how information is transferred; usually it is transferred in binary code in signals or pulses. A phase lock oscillator includes a phase discriminator that develops an error signal by comparing a clock from a voltage controlled oscillator with incoming random data bits. In the absence of data, the phase lock oscillator is inactive. However, when data is sensed, a logic and delay network in the phase discriminator develops an error voltage of suitable polarity and amplitude, indicative of the lead or lag between the data and clock signals. The error voltage is applied to the voltage controlled oscillator to modify the frequency and phase of the clock. Furthermore, first and second integrations are provided by the phase Collected and Composed by Bilal Farooq (bilal.zaheem@gmail.com)

127 discriminator and an integrator respectively so that the steady state phase error is held close to zero. It is known that spurious variations in the mechanical or electrical parameters of a storage system cause unwanted displacement and shift of the signal being processed, thus necessitating frequency and phase compensation. To this end, synchronizing systems, servosystems, phase lock oscillator circuits, separation circuits and the like are employed. Collected and Composed by Bilal Farooq (bilal.zaheem@gmail.com)

128 CS302 CURRENT FINAL TERM 2011 Question#1 Marks 2 Give advantages of Counters are available in integrated circuits? Question #2 Marks 2 Successive approximation counter have a fixed consecutive time Is tarha ka qs tha Question #4 Marks 2 How many states in 8 bit Johnson counter? Question #5 Marks 3 Diff b/w truth table and next state table Question #6 Marks 3 How hexadecimal number is converted into binary number give one example? Question #7 Marks 3 Diff b/w ROM n PROM? Question #8 Marks 3 How we can implement full adder from two half adder? Question #9 Marks 5 Make State diagram? Question #10 Expain FRGA? Marks 5 Question #11 Marks 5 Differentiate b/w memory density and memory capacity? Question #12 Is ki output one ai A. B A. B. C. D

129 Question # 1 of 10 ( Start time: 10:22:36 AM ) Total Marks: 1 A divide-by-10 Johnson counter requires Select correct option: ten flip-flops four flip-flops five flip-flops twelve flip-flops In the keyboard encoder, how many times per second does the ring counter scan the key board? Select correct option: 600 scans/second 625 scans/second 650 scans/second 700 scans/second Click here to Save Answer & Move to Next Question Question # 3 of 10 ( Start time: 10:25:36 AM ) Total Marks: 1 Smallest unit of data is Select correct option:

130 a bit a 4-bits nibble an 8-bits word a 16-bits word The 64-cell array organized as 8 x 8 cell array is considered Select correct option: as an 64 byte memory as a 16 byte memory as an 8 byte memory as an 4 byte memory Click here to Save Answer & Move to Next Question The 64-cell array organized as 8 x 8 cell array is considered Select correct option: as an 64 byte memory

131 as a 16 byte memory as an 8 byte memory as an 4 byte memory Click here to Save Answer & Move to Next Question memory read cycle To write data to the memory, the write cycle is initiated by Select correct option: applying the address signals. assigning the values to variables. reserving the space for variables. applying the data signals. Click here to Save Answer & Move to Next Question Which of the following is the drawback of DRAM? Select correct option: Discharging of the capacitor over a period of time.

132 All the information stored in terms of binary bits wou extra circuitry is required to refresh the capacitor All of the above are true Click here to Save Answer & Move to Next Question A stage in the shift register consists of Select correct option: a latch a flip flop a byte of storage four bits of storage Click here to Save Answer & Move to Next Question To parallel load a byte of data into a shift register, there must be Select correct option: one clock pulse one clock pulse for each 1 in the data

133 eight clock pulse one clock pulse for each 0 in the data With a 100 KHz clock frequency, eight bits can be serially entered into a shift register in Click here to Save Answer & Move to Next Question Select correct option: 80 micro seconds 8 micro seconds 80 mili seconds 10 micro seconds Click here to Save Answer & Move to Next Question

134 FINALTERM EXAMINATION Spring 2010 CS302- Digital Logic Design (Session - 4) Time: 90 min Marks: 58 For Teacher's Use Only Q Total No. Marks Q No Marks Q No Marks Q No Marks Q No Marks

135 Question No: 1 ( Marks: 1 ) - Please choose one The ANSI/IEEE Standard 754 defines a Single-Precision Floating Point format for binary numbers. 8-bit 16-bit 32-bit 64-bit Question No: 2 ( Marks: 1 ) - Please choose one The decimal 17 in BCD will be represented as Question No: 3 ( Marks: 1 ) - Please choose one The basic building block for a logical circuit is A Flip-Flop A Logical Gate An Adder None of given options Question No: 4 ( Marks: 1 ) - Please choose one The output of the expression F=A.B.C will be Logic when A=1, B=0, C=1. Undefined One Zero No Output as input is invalid. Question No: 5 ( Marks: 1 ) - Please choose one is invalid number of cells in a single group formed by the adjacent cells in K- map

136 Question No: 6 ( Marks: 1 ) - Please choose one The PROM consists of a fixed non-programmable Gate array configured as a decoder. AND OR NOT XOR Question No: 7 ( Marks: 1 ) - Please choose one is one of the examples of synchronous inputs. J-K input EN input Preset input (PRE) Clear Input (CLR) Question No: 8 ( Marks: 1 ) - Please choose one is one of the examples of asynchronous inputs. J-K input S-R input D input Clear Input (CLR) Question No: 9 ( Marks: 1 ) - Please choose one The input overrides the input Asynchronous, synchronous Synchronous, asynchronous Preset input (PRE), Clear input (CLR) Clear input (CLR), Preset input (PRE) Question No: 10 ( Marks: 1 ) - Please choose one occurs when the same clock signal arrives at different times at different clock inputs due to propagation delay. Race condition Clock Skew Ripple Effect None of given options Question No: 11 ( Marks: 1 ) - Please choose one Consider an up/down counter that counts between 0 and 15, if external input(x) is 0 the counter counts upward (0000 to 1111) and if external input (X) is 1 the counter counts downward (1111 to 0000), now suppose that the present state is 1100 and X=1, the next state of the counter will be

137 Question No: 12 ( Marks: 1 ) - Please choose one In a state diagram, the transition from a current state to the next state is determined by Current state and the inputs Current state and outputs Previous state and inputs Previous state and outputs Question No: 13 ( Marks: 1 ) - Please choose one is used to minimize the possible no. of states of a circuit. State assignment State reduction Next state table State diagram Question No: 14 ( Marks: 1 ) - Please choose one is used to simplify the circuit that determines the next state. State diagram Next state table State reduction State assignment Question No: 15 ( Marks: 1 ) - Please choose one The best state assignment tends to. Maximizes the number of state variables that don t change in a group of related states Minimizes the number of state variables that don t change in a group of related states Minimize the equivalent states None of given options Question No: 16 ( Marks: 1 ) - Please choose one The output of this circuit is always.

138 1 0 A Question No: 17 ( Marks: 1 ) - Please choose one A 8-bit serial in / parallel out shift register contains the value 8, clock signal(s) will be required to shift the value completely out of the register Question No: 18 ( Marks: 1 ) - Please choose one 5-bit Johnson counter sequences through states Question No: 19 ( Marks: 1 ) - Please choose one Assume that a 4-bit serial in/serial out shift register is initially clear. We wish to store the nibble What will be the 4-bit pattern after the second clock pulse? (Right-most bit first.) Question No: 20 ( Marks: 1 ) - Please choose one The address from which the data is read, is provided by

139 Depends on circuitry None of given options RAM Microprocessor Question No: 21 ( Marks: 1 ) - Please choose one FIFO is an acronym for First In, First Out Fly in, Fly Out Fast in, Fast Out None of given options Question No: 22 ( Marks: 1 ) - Please choose one LUT is acronym for Look Up Table Local User Terminal Least Upper Time Period None of given options Question No: 23 ( Marks: 1 ) - Please choose one The voltage gain of the Inverting Amplifier is given by the relation V out / V in = - R f / R i V out / R f = - V in / R i R f / V in = - R i / V out R f / V in = R i / V out Question No: 24 ( Marks: 1 ) - Please choose one of a D/A converter is determined by comparing the actual output of a D/A converter with the expected output. Resolution Accuracy Quantization Missing Code Question No: 25 ( Marks: 1 ) - Please choose one

140 Above is the circuit diagram of. Asynchronous up-counter Asynchronous down-counter Synchronous up-counter Synchronous down-counter Question No: 26 ( Marks: 1 ) - Please choose one The sequence of states that are implemented by a n-bit Johnson counter is n+2 (n plus 2) 2n (n multiplied by 2) 2 n (2 raise to power n) n 2 (n raise to power 2) Question No: 27 ( Marks: 2 ) Draw the Truth-Table of NOR based S-R Latch input output S R Q T Q T INVALID Question No: 28 ( Marks: 2 ) Two state assignments are given in the table below. Identify which state assignment is best and why? States State assignment 1 State assignment 2 A B 01 01

141 C D Ans: State assignment 2 is best assignment it Minimizes the number of state variables that don t change in a group of related states. Question No: 29 ( Marks: 2 ) Write down at least two functions of a register. Ans: 1. Registers are operating as a coherent unit to hold and generate data. 2. registers functions also include configuration and start-up of certain features, especially during initialization, buffer storage e.g. video memory for graphics cards, input/output (I/O) of different kinds, Question No: 30 ( Marks: 2 ) Define quantization process. Ans: The process by which we can convert an analogue signal into digital signal (code) is known as quantization process. Question No: 31 ( Marks: 3 ) How can we calculate the frequency of an unknown signal? Ans: The frequency of a particular event is accomplished by counting the number of times that event occurs within a specific time interval, then dividing the count by the length of the time interval. Question No: 32 ( Marks: 3 ) Given the following statement used in PLD programming: Y PIN 23 ISTYPE com ; Explain what does this statement mean? Ans: The Y variable is a Combinational output available directly from the AND-OR gate array output. The active-low or active-high output of the Registered Mode can also be specified in the declaration statement

142 Question No: 33 ( Marks: 3 ) Explain dynamic RAM in your own words. Ans: Dram use latch to store a single bit of information.the main drawback of it id the discharge of capacitor over a period of time.here four gates are used in making a singlelatch. In terms of transistors, 4 to 6 transistors are required to implement a single storage cell. In order to build memories with higher densities, a single transistor is used to store a binary value. A single transistor can not store a binary value however it is used to charge and discharge a capacitor. The capacitor can not retain the charge, therefore it has to be periodically charged through a refresh cycle. Question No: 34 ( Marks: 5 ) You are given the Next-state table of a moor machine, using this information draw the state diagram of the machine. Present State Next State Q 2 Q 1 Q 0 Q 2 Q 1 Q Question No: 35 ( Marks: 5 ) Explain Memory Select or Enable Signals Memory Select or Enable Signal: There are more than one memory chips to store program Information in daily use computers. read or write operation is carried out on a single addressable location instantaneously. The unique location is accessed in one of the several memory chips, so single memory chips is selected before a read or write operation can be carried out. All memory chips have a chip enable or chip select signal which has to be activated before the memory can be accessed.

143 Question No: 36 ( Marks: 5 ) Performance characteristics of D/A converters are determined by five parameters. Name them. Ans: Performances characteristics of D/A converters are determined by five parameters are as follow: 1. Accuracy 2. Setting time 3. Monotonicity 4. Linearity 5. Resolution

144 FINALTERM EXAMINATION SEMESTER FALL 2004 CS302-Digital Logic Design (S1) Total Marks:70 Duration:120 Min Maximum Time Allowed: (2 Hours) Please read the following instructions carefully before attempting any of the questions: 1. Attempt all questions. 2. Calculators are NOT allowed. 3. Do not ask any questions about the contents of this examination from anyone. a. If you think that there is something wrong with any of the questions, attempt it to the best of your understanding. b. If you believe that some essential piece of information is missing, make an appropriate assumption and use it to solve the problem. 4. Circuit Diagrams, Equations and Truth Tables should be clear.

145 Write down all the steps in Subjective Questions. Marks will be deducted for missing steps. **WARNING: Please note that Virtual University takes serious note of unfair means. Anyone found involved in cheating will get an `F` grade in this course. 1 Student ID / Login ID Name PVC Name / Code Date

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147 For Teacher s use only Question Q1 Q2 Q3 Q4 Q5 Q6 Q7 Total Marks Question No: 1 Marks: a) Convert each of the following POS expression to minimum SOP expression using a Karnaugh Map. ( A B)( A B C )(B C D)( A B C D) b) Convert the decimal numbers 78 and 34 into Octal. Using octal addition, add the two numbers and convert the octal result back into decimal and verify the answer. Question No: 2 Marks: 8 Draw the timing diagram of QA, QA, QB and QB. Assume the Positive edge triggering.

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149 3 Question No: 3 Marks: 10 Show the complete timing diagram for the 5 stage synchronous binary counter. HIGH FF0 LSB J 4 J 0 J J J Q0 Q1 Q2 Q3 Q4 C C C C C K0 K1 K2 K3 K 4 CLK Question No: 4 Marks: 10

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151 It is required to construct a memory with 256 words, 16 bits per word. Cores are available in a matrix of 16 rows and 16 columns. a) How many matrices are needed? b) How many flip-flops are in the address and buffer registers? c) How many cores receive current during a read cycle? d) How many cores receive at least half-current during a write cycle? Question No: 5 Marks: 8 Show the data output waveform for a 4-bit register with the parallel input data and the clock and SHIFT / LOAD waveform given in the figure. The serial data input (SER) is a 0. The parallel data inputs are D0=1, D1=0, D2=1, D3=0 as shown. Develop the data-output waveform in relation to the inputs. 4 D D D D SHIFT/LOAD Data out SER Q 3 CLK C CLK SHIFT/LOAD Data out Q 3 Question No: 6 Marks: 10 Implement a 4-bit Johnson Counter using J-K flip-flops Question No: 7 Marks: 8 Briefly answer the following questions: a) What does sampling mean? b) Why you must hold a sampled value? c) If the highest frequency component in an analog signal is 20kHz, what is minimum sample frequency? d) What determines the accuracy of quantization process?

152 FINALTERM EXAMINATION Spring 2009 CS302- Digital Logic Design (Session - 2) Question No: 1 ( Marks: 1 ) - Please choose one The diagram given below represents Demorgans law Associative law Product of sum form Sum of product form Question No: 2 ( Marks: 1 ) - Please choose one Excess-8 code assigns to Question No: 3 ( Marks: 1 ) - Please choose one NOR gate is formed by connecting OR Gate and then NOT Gate NOT Gate and then OR Gate AND Gate and then OR Gate OR Gate and then AND Gate Question No: 4 ( Marks: 1 ) - Please choose one A full-adder has a C in = 0. What are the sum (<PRIVATE "TYPE=PICT;ALT=sigma"> ) and the carry (C out ) when A = 1 and B = 1? = 0, C out = 0 = 0, C out = 0 = 0, C out = 1

153 = 1, C out = 0 = 1, C out = 1 Question No: 5 ( Marks: 1 ) - Please choose one adder has-a particular half 2 INPUTS AND 1 OUTPUT 2 INPUTS AND 2 OUTPUT 3 INPUTS AND 1 OUTPUT 3 INPUTS AND 2 OUTPUT Question No: 6 ( Marks: 1 ) - Please choose one THE FOUR OUTPUTS OF TWO 4-INPUT MULTIPLEXERS, CONNECTED TO FORM A 16-INPUT MULTIPLEXER, ARE CONNECTED TOGETHER THROUGH A 4-INPUT GATE AND OR NAND XOR Question No: 7 ( Marks: 1 ) - Please choose one A FIELD-PROGRAMMABLE LOGIC ARRAY CAN BE PROGRAMMED BY THE USER AND NOT BY THE MANUFACTURER. TRUE FALSE Question No: 8 ( Marks: 1 ) - Please choose one FLIP FLOPS ARE ALSO CALLED BI-STABLE DUALVIBRATORS BI-STABLE TRANSFORMER BI-STABLE MULTIVIBRATORS Bi-stable singlevibrators Question No: 9 ( Marks: 1 ) - Please choose one A POSITIVE EDGE-TRIGGERED FLIP-FLOP CHANGES ITS STATE WHEN LOW-TO-HIGH TRANSITION OF CLOCK HIGH-TO-LOW TRANSITION OF CLOCK ENABLE INPUT (EN) IS SET PRESET INPUT (PRE) IS SET Question No: 10 ( Marks: 1 ) - Please choose one IS ONE OF THE EXAMPLES OF SYNCHRONOUS INPUTS. J-K INPUT EN INPUT

154 Preset input (PRE) CLEAR INPUT (CLR) Question No: 11 ( Marks: 1 ) - Please choose one THE GLITCHES DUE TO RACE CONDITION CAN BE AVOIDED BY USING A GATED FLIP-FLOPS PULSE TRIGGERED FLIP-FLOPS POSITIVE-EDGE TRIGGERED FLIP-FLOPS NEGATIVE-EDGE TRIGGERED FLIP-FLOPS Question No: 12 ( Marks: 1 ) - Please choose one THE DESIGN AND IMPLEMENTATION OF SYNCHRONOUS COUNTERS START FROM TRUTH TABLE K-MAP STATE TABLE STATE DIAGRAM Question No: 13 ( Marks: 1 ) - Please choose one THE HOURS COUNTER IS IMPLEMENTED USING ONLY A SINGLE MOD-12 COUNTER IS REQUIRED MOD-10 AND MOD-6 COUNTERS MOD-10 AND MOD-2 COUNTERS A SINGLE DECADE COUNTER AND A FLIP-FLOP Question No: 14 ( Marks: 1 ) - Please choose one GIVEN THE STATE DIAGRAM OF AN UP/DOWN COUNTER, WE CAN FIND THE NEXT STATE OF A GIVEN PRESENT STATE THE PREVIOUS STATE OF A GIVEN PRESENT STATE BOTH THE NEXT AND PREVIOUS STATES OF A GIVEN STATE The state diagram shows only the inputs/outputs of a given states Question No: 15 ( Marks: 1 ) - Please choose one In outputs depend only on the current state. Mealy machine MOORE MACHINE

155 STATE REDUCTION TABLE STATE ASSIGNMENT TABLE Question No: 16 ( Marks: 1 ) - Please choose one A SYNCHRONOUS DECADE COUNTER WILL HAVE FLIP-FLOPS Question No: 17 ( Marks: 1 ) - Please choose one A MULTIPLEXER WITH A REGISTER CIRCUIT CONVERTS SERIAL DATA TO PARALLEL PARALLEL DATA TO SERIAL Serial data to serial PARALLEL DATA TO PARALLEL Question No: 18 ( Marks: 1 ) - Please choose one The alternate solution for a multiplexer and a register circuit is PARALLEL IN / SERIAL OUT SHIFT REGISTER SERIAL IN / PARALLEL OUT SHIFT REGISTER PARALLEL IN / PARALLEL OUT SHIFT REGISTER SERIAL IN / SERIAL OUT SHIFT REGISTER Question No: 19 ( Marks: 1 ) - Please choose one AT T0 THE VALUE STORED IN A 4-BIT LEFT SHIFT WAS 1. WHAT WILL BE THE VALUE OF REGISTER AFTER THREE CLOCK PULSES? Question No: 20 ( Marks: 1 ) - Please choose one A 8-BIT SERIAL IN / PARALLEL OUT SHIFT REGISTER CONTAINS THE VALUE 8, CLOCK SIGNAL(S) WILL BE REQUIRED TO SHIFT THE VALUE COMPLETELY OUT OF THE REGISTER

156 4 8 Question No: 21 ( Marks: 1 ) - Please choose one 5-BIT JOHNSON COUNTER SEQUENCES THROUGH STATES Question No: 22 ( Marks: 1 ) - Please choose one IN Q OUTPUT OF THE LAST FLIP-FLOP OF THE SHIFT REGISTER IS CONNECTED TO THE DATA INPUT OF THE FIRST FLIP-FLOP OF THE SHIFT REGISTER. MOORE MACHINE Meally machine Johnson counter Ring counter Question No: 23 ( Marks: 1 ) - Please choose one DRAM STANDS FOR DYNAMIC RAM Data RAM Demoduler RAM None of given options Question No: 24 ( Marks: 1 ) - Please choose one IF THE FIFO MEMORY OUTPUT IS ALREADY FILLED WITH DATA THEN IT IS LOCKED; NO DATA IS ALLOWED TO ENTER IT IS NOT LOCKED; THE NEW DATA OVERWRITES THE PREVIOUS DATA. PREVIOUS DATA IS SWAPPED OUT OF MEMORY AND NEW DATA ENTERS NONE OF GIVEN OPTIONS Question No: 25 ( Marks: 1 ) - Please choose one LUT is acronym for LOOK UP TABLE LOCAL USER TERMINAL LEAST UPPER TIME PERIOD NONE OF GIVEN OPTIONS

157 Question No: 26 ( Marks: 1 ) - Please choose one OF A D/A CONVERTER IS DETERMINED BY COMPARING THE ACTUAL OUTPUT OF A D/A CONVERTER WITH THE EXPECTED OUTPUT. RESOLUTION Accuracy Quantization Missing Code Question No: 27 ( Marks: 1 ) - Please choose one In the circuit diagram of 3-bit synchronous counterthe red rectangle would,shown above be replaced which gate? AND OR NAND XNOR Question No: 28 ( Marks: 1 ) - Please choose one WHEN BOTH THE INPUTS OF EDGE-TRIGGERED J-K FLOP-FLOP ARE SET TO LOGIC ZERO THE FLOP-FLOP IS TRIGGERED Q=0 AND Q =1 Q=1 AND Q =0 THE OUTPUT OF FLIP-FLOP REMAINS UNCHANGED Question No: 29 ( Marks: 1 ) - Please choose one A FREQUENCY COUNTER

158 Counts pulse width COUNTS NO. OF CLOCK PULSES IN 1 SECOND Counts high and low range of given clock pulse NONE OF GIVEN OPTIONS Question No: 30 ( Marks: 1 ) - Please choose one Stack is an acronym for FIFO memory LIFO memory Flash Memory Bust Flash Memory Question No: 31 ( Marks: 1 ) What is the role of MOS transistor in Mask ROM. Question No: 32 ( Marks: 1 ) THE GROUP OF BITS IS SERIALLY SHIFTED (RIGHT-MOST BIT FIRST) INTO AN 8-BIT PARALLEL OUTPUT SHIFT REGISTER WITH AN INITIAL STATE WHAT WILL BE THE CONTENTS OF REGISTER AFTER TWO CLOCK PULSES THE REGISTER CONTAINS? Question No: 33 ( Marks: 2 ) DRAW THE CIRCUIT DIAGRAM OF GATED S-R LATCH. Question No: 34 ( Marks: 2 ) HOW MANY BYTES WILL BE THERE IN 32 K X 4 MEMORY? 32 X 1024BYTES X 4 = BYTES Question No: 35 ( Marks: 3 ) THE OF FIRST 74HC163 COUNTER IS CONNECTED TO AND INPUTS OF OTHER 74HC COUNTER TO FORM A SINGLE CASCADED COUNTER Question No: 36 ( Marks: 3 )

159 GIVEN THE FOLLOWING STATEMENT USED IN PLD PROGRAMMING: Y PIN 23 ISTYPE COM ; Explain what does this statement mean? VARIABLE Y AT OUTPUT PIN 23 WHICH IS A COMBINATIONAL OUTPUT AVAILABLE DIRECTLY FROM THE AND-OR GATE ARRAY OUTPUT. Y = VARIABLE Y PIN 23 = PIN NUMBER 23 ISTYPE COM = OUTPUT TYPE COMBINATIONAL Question No: 37 ( Marks: 3 ) WHAT IS MEMORY EXPANSION PROCESS? Question No: 38 ( Marks: 5 ) CONSIDER THE TABLE GIVEN BELOW, APPLY THE STATE REDUCTION PROCESS ON THE STATES GIVEN IN THE TABLE AND REDUCE THE NUMBER OF STATES AS MUCH AS POSSIBLE. PRESENT STATE NEXT STATE OUTPUT X=0 X=1 X=0 X=1 A F B 0 0 B B C 1 1 C A F 0 1 D E D 1 0 E A G 0 1 F D E 0 0 G D E 0 0 Question No: 39 ( Marks: 5 ) PERFORMANCE CHARACTERISTICS OF D/A CONVERTERS ARE DETERMINED BY FIVE PARAMETERS. NAME THEM. Question No: 40 ( Marks: 10 ) GIVEN BELOW IS THE CIRCUIT DIAGRAM OF BI-DIRECTIONAL 4-BIT SERIAL IN/SERIAL OUT SHIFT REGISTER. REGISTER SHIFTS DATA LEFT OR RIGHT DEPENDS ON THE RIGHT /LEFT RIGHT. SIGNAL APPLIED. EXPLAIN HOW THIS CIRCUIT SHIFTS DATA LEFT AND

160 Question No: 41 ( Marks: 10 ) BRIEFLY EXPLAIN ADDRESS MULTIPLEXING IN DRAM.

161 MIDTERM EXAMINATION Spring 2009 CS302- Digital Logic Design (Session - 1) Question No: 1 ( Marks: 1 ) - Please choose one can be reprogrammed because instead of fuses logic is used in it E 2 CMOS TTL CMOS+ None of the given options Question No: 2 ( Marks: 1 ) - Please choose one device shown here is most likely a Comparator Multiplexer Demultiplexer Parity generator Question No: 3 ( Marks: 1 ) - Please choose one 1110 is applied at the input of BCD-to-Decimal decoder which output pin will be activated: 2 nd 4 th 14 th No output wire will be activated Question No: 4 ( Marks: 1 ) - Please choose one Half-Adder Logic circuit contains 2 XOR Gates True False Question No: 5 ( Marks: 1 ) - Please choose one GAL The If A

162 particular Full Adder has 3 inputs and 2 output 3 inputs and 3 output 2 inputs and 3 output 2 inputs and 2 output Question No: 6 ( Marks: 1 ) - Please choose one Sum A B C CarryOut C( A B) AB are the Sum and CarryOut expression of Half Adder Full Adder 3-bit parralel adder MSI adder cicuit Question No: 7 ( Marks: 1 ) - Please choose one Karnaugh map is similar to a truth table because it presents all the possible values of input variables and the resulting output of each value. True False Question No: 8 ( Marks: 1 ) - Please choose one output A < B is set to 1 when the input combinations is A=10, B=01 A=11, B=01 A=01, B=01 A=01, B=10 Question No: 9 ( Marks: 1 ) - Please choose one 4-variable Karnaugh Map (K-Map) has cells for min or max terms Question No: 10 ( Marks: 1 ) - Please choose one A The The

163 Generally, the Power dissipation of devices remains constant throughout their operation. TTL CMOS 3.5 series CMOS 5 Series Power dissipation of all circuits increases with time. Question No: 11 ( Marks: 1 ) - Please choose one decimal 8 is represented as using Gray-Code Question No: 12 ( Marks: 1 ) - Please choose one (A+B).(A+C) = B+C A+BC AB+C AC+B Question No: 13 ( Marks: 1 ) - Please choose one + C) = A.B + A.C is the expression of Demorgan s Law Commutative Law Distributive Law Associative Law Question No: 14 ( Marks: 1 ) - Please choose one NOR Gate can be used to perform the operation of AND, OR and NOT Gate FALSE TRUE Question No: 15 ( Marks: 1 ) - Please choose one The A.(B

164 ANSI/IEEE Standard 754 Mantissa is represented by 32-bits bits 8-bits 16-bits 32-bits 64-bits Question No: 16 ( Marks: 1 ) - Please choose one Caveman number system is Base _5 number system Question No: 17 ( Marks: 1 ) Briefly state the basic principle of Repeated Multiplication-by-2 Method. Question No: 18 ( Marks: 1 ) standard Boolean expressions can be converted into truth table format. Question No: 19 ( Marks: 2 ) What will be the out put of the diagram given below Question No: 20 ( Marks: 3 ) In How

165 When an Input (source) file is created in ABEL a module is created which has three sections. Name These three sections. Question No: 21 ( Marks: 5 ) Explain AND Gate and some of its uses Question No: 22 ( Marks: 10 ) Write down different situations where we need the sequential circuits.

166 MIDTERM EXAMINATION Spring 2009 CS302- Digital Logic Design (Session - 1) Question No: 1 ( Marks: 1 ) - Please choose one the binary number the weight of the most significant digit is 2 4 (2 raise to power 4) 2 3 (2 raise to power 3) 2 0 (2 raise to power 0) 2 1 (2 raise to power 1) Question No: 2 ( Marks: 1 ) - Please choose one S-R latch can be implemented by using gates AND, OR NAND, NOR NAND, XOR NOT, XOR Question No: 3 ( Marks: 1 ) - Please choose one latch has stable states One Two Three Four Question No: 4 ( Marks: 1 ) - Please choose one Sequential circuits have storage elements True False Question No: 5 ( Marks: 1 ) - Please choose one ABEL symbol for XOR operation is $ #! In An A The

167 & Question No: 6 ( Marks: 1 ) - Please choose one Demultiplexer is not available commercially. True False Question No: 7 ( Marks: 1 ) - Please choose one Using multiplexer as parallel to serial converter requires connected to the multiplexer A parallel to serial converter circuit A counter circuit A BCD to Decimal decoder A 2-to-8 bit decoder Question No: 8 ( Marks: 1 ) - Please choose one device shown here is most likely a Comparator Multiplexer Demultiplexer Parity generator Question No: 9 ( Marks: 1 ) - Please choose one main use of the Multiplexer is to Select data from multiple sources and to route it to a single Destination Select data from Single source and to route it to a multiple Destinations Select data from Single source and to route to single destination Select data from multiple sources and to route to multiple destinations A The The

168 Question No: 10 ( Marks: 1 ) - Please choose one logic circuit with an output two AND gates, two OR gates, two inverters three AND gates, two OR gates, one inverter two AND gates, one OR gate, two inverters two AND gates, one OR gate consists of. Question No: 11 ( Marks: 1 ) - Please choose one binary value of 1010 is converted to the product term True False Question No: 12 ( Marks: 1 ) - Please choose one 3-variable Karnaugh Map (K-Map) has cells for min or max terms Question No: 13 ( Marks: 1 ) - Please choose one Following is standard POS expression True False Question No: 14 ( Marks: 1 ) - Please choose one The output of the expression F=A+B+C will be Logic when A=0, B=1, C=1. the symbol + here represents OR Gate. A The The

169 Undefined One Zero 10 (binary) Question No: 15 ( Marks: 1 ) - Please choose one The Extended ASCII Code (American Standard Code for Information Interchange) is a code 2-bit 7-bit 8-bit 16-bit Question No: 16 ( Marks: 1 ) - Please choose one diagram given below represents Demorgans law Associative law Product of sum form Sum of product form Question No: 17 ( Marks: 1 ) How can a PLD be programmed? Question No: 18 ( Marks: 1 ) How many input and output bits do a Half-Adder contain? Question No: 19 ( Marks: 2 ) Explain the difference between 1-to-4 Demultiplexer 2-to-4 Binary Decoder? Question No: 20 ( Marks: 3 ) The

170 Name the three declarations that are included in declaration section of the module that is created when an Input (source) file is created in ABEL. Question No: 21 ( Marks: 5 ) Explain with example how noise affects Operation of a CMOS AND Gate circuit. Question No: 22 ( Marks: 10 ) explain the SOP based implementation of the Adjacent 1s Detector Circuit

171 CS302- Digital Logic Design LATEST SOLVED MCQS FROM FINAL TERM PAPERS Latest Mcqs MC PSMD01(IEMS) FINALTERM EXAMINATION Spring 2011 Question No: 1 ( Marks: 1 ) - Please choose one A 8-bit serial in / parallel out shift register contains the value 8, clock signal(s) will be required to shift the value completely out of the register (Page 356) Question No: 2 ( Marks: 1 ) - Please choose one In a sequential circuit the next state is determined by and State variable, current state Current state, flip-flop output Current state and external input (Page 318) Input and clock signal applied Question No: 3 ( Marks: 1 ) - Please choose one The divide-by-60 counter in digital clock is implemented by using two cascading counters: Mod-6, Mod-10 (Page 299) Mod-50, Mod-10 Mod-10, Mod-50 Mod-50, Mod-6 Question No: 4 ( Marks: 1 ) - Please choose one In NOR gate based S-R latch if both S and R inputs are set to logic 0, the previous output state is maintained. True (Page 221) False

172 Question No: 5 ( Marks: 1 ) - Please choose one The minimum time for which the input signal has to be maintained at the input of flip-flop is called of the flip-flop. Set-up time Hold time (Page 242) Pulse Interval time Pulse Stability time (PST) Question No: 6 ( Marks: 1 ) - Please choose one 74HC163 has two enable input pins which are and ENP, ENT (Page 285) ENI, ENC ENP, ENC ENT, ENI Question No: 7 ( Marks: 1 ) - Please choose one is said to occur when multiple internal variables change due to change in one input variable Clock Skew Race condition (Page 267) Hold delay Hold and Wait Question No: 8 ( Marks: 1 ) - Please choose one The input overrides the input Asynchronous, synchronous (Page 369) Synchronous, asynchronous Preset input (PRE), Clear input (CLR) Clear input (CLR), Preset input (PRE) Question No: 9 ( Marks: 1 ) - Please choose one A decade counter is. Mod-3 counter Mod-5 counter Mod-8 counter Mod-10 counter (Page 274) Question No: 10 ( Marks: 1 ) - Please choose one In asynchronous transmission when the transmission line is idle, It is set to logic low It is set to logic high (Page 356) Remains in previous state State of transmission line is not used to start transmission

173 Question No: 11 ( Marks: 1 ) A Nibble consists of bits - Please choose one 2 4 (Page 394) 8 16 Question No: 12 ( Marks: 1 ) - Please choose one The output of this circuit is always. 1 0 A Click here for detail Question No: 13 ( Marks: 1 ) - Please choose one Excess-8 code assigns to (Page 34) Question No: 14 ( Marks: 1 ) - Please choose one The voltage gain of the Inverting Amplifier is given by the relation Vout / Vin = - Rf / Ri (Page 446) Vout / Rf = - Vin / Ri Rf / Vin = - Ri / Vout Rf / Vin = Ri / Vout Question No: 15 ( Marks: 1 ) LUT is acronym for - Please choose one Look Up Table (Page 439) Local User Terminal Least Upper Time Period None of given options

174 Question No: 16 ( Marks: 1 ) - Please choose one The three fundamental gates are AND, NAND, XOR OR, AND, NAND NOT, NOR, XOR NOT, OR, AND (Page 40) Question No: 17 ( Marks: 1 ) - Please choose one The total amount of memory that is supported by any digital system depends upon The organization of memory The structure of memory The size of decoding unit The size of the address bus of the microprocessor (Page 430) Question No: 18 ( Marks: 1 ) - Please choose one Stack is an acronym for FIFO memory LIFO memory (Page 429) Flash Memory Bust Flash Memory Question No: 19 ( Marks: 1 ) - Please choose one Addition of two octal numbers 36 and 71 results in Question No: 20 ( Marks: 1 ) - Please choose one is one of the examples of synchronous inputs. J-K input (Page 235) EN input Preset input (PRE) Clear Input (CLR) Question No: 21 ( Marks: 1 ) - Please choose one occurs when the same clock signal arrives at different times at different clock inputs due to propagation delay. Race condition Clock Skew (Page 226) Ripple Effect None of given options

175 Question No: 22 ( Marks: 1 ) - Please choose one Consider an up/down counter that counts between 0 and 15, if external input(x) is 0 the counter counts upward (0000 to 1111) and if external input (X) is 1 the counter counts downward (1111 to 0000), now suppose that the present state is 1100 and X=1, the next state of the counter will be (not sure) Question No: 23 ( Marks: 1 ) - Please choose one In a state diagram, the transition from a current state to the next state is determined by Current state and the inputs (Page 332) Current state and outputs Previous state and inputs Previous state and outputs Question No: 24 ( Marks: 1 ) - Please choose one is used to simplify the circuit that determines the next state. State diagram Next state table State reduction State assignment (Page 335) Question No: 25 ( Marks: 1 ) - Please choose one A 8-bit serial in / parallel out shift register contains the value 8, clock signal(s) will be required to shift the value completely out of the register (Page 356) rep Question No: 26 ( Marks: 1 ) - Please choose one Assume that a 4-bit serial in/serial out shift register is initially clear. We wish to store the nibble What will be the 4-bit pattern after the second clock pulse? (Right-most bit first.) Click here for detail 1111

176 Question No: 27 ( Marks: 1 ) - Please choose one LUT is acronym for Look Up Table (Page 439) rep Local User Terminal Least Upper Time Period None of given options. Question No: 28 ( Marks: 1 ) - Please choose one The diagram given below represents Demorgans law Associative law Product of sum form Sum of product form (Page 78) Question No: 29 ( Marks: 1 ) - Please choose one The operation of J-K flip-flop is similar to that of the SR flip-flop except that the J-K flip-flop Doesn t have an invalid state (Page 232) Sets to clear when both J = 0 and K = 0 It does not show transition on change in pulse It does not accept asynchronous inputs Question No: 30 ( Marks: 1 ) - Please choose one A multiplexer with a register circuit converts Serial data to parallel Parallel data to serial (Page 356) rep Serial data to serial Parallel data to parallel Question No: 31 ( Marks: 1 ) - Please choose one A GAL is essentially a. Non-reprogrammable PAL PAL that is programmed only by the manufacturer Very large PAL Reprogrammable PAL (Page 183)

177 Question No: 32 ( Marks: 1 ) - Please choose one in, all the columns in the same row are either read or written. Sequential Access MOS Access FAST Mode Page Access (Page 413) None of given options Question No: 33 ( Marks: 1 ) - Please choose one In order to synchronize two devices that consume and produce data at different rates, we can use Read Only Memory Fist In First Out Memory (Page 425) Flash Memory Fast Page Access Mode Memory Question No: 34 ( Marks: 1 ) - Please choose one A positive edge-triggered flip-flop changes its state when Low-to-high transition of clock (Page 228) High-to-low transition of clock Enable input (EN) is set Preset input (PRE) is set FINALTERM EXAMINATION Spring 2010 Question No: 1 ( Marks: 1 ) - Please choose one A 8-bit serial in / parallel out shift register contains the value 8, clock signal(s) will be required to shift the value completely out of the register (Page 356) rep Question No: 2 ( Marks: 1 ) - Please choose one A frequency counter Counts pulse width Counts no. of clock pulses in 1 second (Page 301) Counts high and low range of given clock pulse None of given options

178 Question No: 3 ( Marks: 1 ) - Please choose one In a sequential circuit the next state is determined by and State variable, current state Current state, flip-flop output Current state and external input Input and clock signal applied (Page 305) Question No: 4 ( Marks: 1 ) - Please choose one The divide-by-60 counter in digital clock is implemented by using two cascading counters: Mod-6, Mod-10 Mod-50, Mod-10 Mod-10, Mod-50 Mod-50, Mod-6 (Page 229) rep Question No: 5 ( Marks: 1 ) - Please choose one In NOR gate based S-R latch if both S and R inputs are set to logic 0, the previous output state is maintained. True (Page 221) rep False Question No: 6 ( Marks: 1 ) - Please choose one Flip flops are also called Bi-stable dualvibrators Bi-stable transformer Bi-stable multivibrators (Page 228) Bi-stable singlevibrators Question No: 7 ( Marks: 1 ) - Please choose one The minimum time for which the input signal has to be maintained at the input of flip-flop is called of the flip-flop. Set-up time Hold time (Page 242) rep Pulse Interval time Pulse Stability time (PST) Question No: 8 ( Marks: 1 ) - Please choose one 74HC163 has two enable input pins which are and ENP, ENT (Page 285) ENI, ENC ENP, ENC ENT, ENI

179 Question No: 9 ( Marks: 1 ) - Please choose one is said to occur when multiple internal variables change due to change in one input variable Clock Skew Race condition (Page 267) Hold delay Hold and Wait Question No: 10 ( Marks: 1 ) - Please choose one Given the state diagram of an up/down counter, we can find The next state of a given present state (Page 371) The previous state of a given present state Both the next and previous states of a given state The state diagram shows only the inputs/outputs of a given states Question No: 11 ( Marks: 1 ) - Please choose one The input overrides the input Asynchronous, synchronous (Page 369) rep Synchronous, asynchronous Preset input (PRE), Clear input (CLR) Clear input (CLR), Preset input (PRE) Question No: 12 ( Marks: 1 ) - Please choose one A logic circuit with an output consists of. two AND gates, two OR gates, two inverters three AND gates, two OR gates, one inverter two AND gates, one OR gate, two inverters (Lecture 8) two AND gates, one OR gate Question No: 13 ( Marks: 1 ) - Please choose one A decade counter is. Mod-3 counter Mod-5 counter Mod-8 counter Mod-10 counter (Page 274)

180 Question No: 14 ( Marks: 1 ) - Please choose one In asynchronous transmission when the transmission line is idle, It is set to logic low It is set to logic high (Page 356) rep Remains in previous state State of transmission line is not used to start transmission Question No: 15 ( Marks: 1 ) - Please choose one A Nibble consists of bits 2 4 (Page 394) 8 16 Question No: 16 ( Marks: 1 ) - Please choose one The output of this circuit is always. 1 0 A Click here for detail rep Question No: 17 ( Marks: 1 ) - Please choose one Excess-8 code assigns to (Page 34) rep Question No: 18 ( Marks: 1 ) - Please choose one The voltage gain of the Inverting Amplifier is given by the relation V out / V in = - R f / R i (Page 446) V out / R f = - V in / R i R f / V in = - R i / V out R f / V in = R i / V out

181 Question No: 19 ( Marks: 1 ) - Please choose one LUT is acronym for Look Up Table (Page 439) Local User Terminal Least Upper Time Period None of given options rep Question No: 20 ( Marks: 1 ) - Please choose one DRAM stands for Dynamic RAM (Page 407) Data RAM Demoduler RAM None of given options Question No: 21 ( Marks: 1 ) - Please choose one The three fundamental gates are AND, NAND, XOR OR, AND, NAND NOT, NOR, XOR NOT, OR, AND (Page 40) Question No: 22 ( Marks: 1 ) - Please choose one Which of the following statement is true regarding above block diagram? Triggering takes place on the negative-going edge of the CLK pulse Triggering takes place on the positive-going edge of the CLK pulse Triggering can take place anytime during the HIGH level of the CLK waveform Triggering can take place anytime during the LOW level of the CLK waveform Question No: 23 ( Marks: 1 ) - Please choose one The total amount of memory that is supported by any digital system depends upon The organization of memory The structure of memory The size of decoding unit The size of the address bus of the microprocessor (Page 430) rep

182 Question No: 24 ( Marks: 1 ) - Please choose one The expression F=A+B+C describes the operation of three bits Gate. OR (Page 42) AND NOT NAND Question No: 25 ( Marks: 1 ) - Please choose one Stack is an acronym for FIFO memory LIFO memory (Page 429) rep Flash Memory Bust Flash Memory Question No: 26 ( Marks: 1 ) - Please choose one Addition of two octal numbers 36 and 71 results in FINALTERM EXAMINATION Spring 2010 Question No: 1 ( Marks: 1 ) - Please choose one The ANSI/IEEE Standard 754 defines a Single-Precision Floating Point format for binary numbers. 8-bit 16-bit 32-bit (Page 25) 64-bit Question No: 2 ( Marks: 1 ) - Please choose one The decimal 17 in BCD will be represented as (According to rule) 11110

183 Question No: 3 ( Marks: 1 ) - Please choose one The basic building block for a logical circuit is A Flip-Flop A Logical Gate (Page 7) An Adder None of given options Question No: 4 ( Marks: 1 ) - Please choose one The output of the expression F=A.B.C will be Logic when A=1, B=0, C=1. Undefined One Zero (According to rule) No Output as input is invalid. Question No: 5 ( Marks: 1 ) - Please choose one is invalid number of cells in a single group formed by the adjacent cells in K-map (According to rule 2^n ) 16 Question No: 6 ( Marks: 1 ) - Please choose one The PROM consists of a fixed non-programmable Gate array configured as a decoder. AND (Page 182) OR NOT XOR Question No: 7 ( Marks: 1 ) - Please choose one is one of the examples of synchronous inputs. J-K input (Page 235) rep EN input Preset input (PRE) Clear Input (CLR) Question No: 8 ( Marks: 1 ) - Please choose one is one of the examples of asynchronous inputs. J-K input S-R input D input Clear Input (CLR) (Page 235)

184 Question No: 9 ( Marks: 1 ) - Please choose one The input overrides the input Asynchronous, synchronous (Page 369) rep Synchronous, asynchronous Preset input (PRE), Clear input (CLR) Clear input (CLR), Preset input (PRE) Question No: 10 ( Marks: 1 ) - Please choose one occurs when the same clock signal arrives at different times at different clock inputs due to propagation delay. Race condition Clock Skew (Page 226) rep Ripple Effect None of given options Question No: 11 ( Marks: 1 ) - Please choose one Consider an up/down counter that counts between 0 and 15, if external input(x) is 0 the counter counts upward (0000 to 1111) and if external input (X) is 1 the counter counts downward (1111 to 0000), now suppose that the present state is 1100 and X=1, the next state of the counter will be (not sure) Question No: 12 ( Marks: 1 ) - Please choose one In a state diagram, the transition from a current state to the next state is determined by Current state and the inputs (Page 232) Current state and outputs Previous state and inputs Previous state and outputs Question No: 13 ( Marks: 1 ) - Please choose one is used to minimize the possible no. of states of a circuit. State assignment (Page 341) State reduction Next state table State diagram

185 Question No: 14 ( Marks: 1 ) - Please choose one is used to simplify the circuit that determines the next state. State diagram Next state table State reduction State assignment (Page 335) Question No: 15 ( Marks: 1 ) - Please choose one The best state assignment tends to. Maximizes the number of state variables that don t change in a group of related states (Page 337) Minimizes the number of state variables that don t change in a group of related states Minimize the equivalent states None of given options Question No: 16 ( Marks: 1 ) - Please choose one The output of this circuit is always. 1 0 A Click here for detail rep Question No: 17 ( Marks: 1 ) - Please choose one A 8-bit serial in / parallel out shift register contains the value 8, clock signal(s) will be required to shift the value completely out of the register (Page 356) rep Question No: 18 ( Marks: 1 ) - Please choose one 5-bit Johnson counter sequences through states 7 10 (Page 354) 32 25

186 Question No: 19 ( Marks: 1 ) - Please choose one Assume that a 4-bit serial in/serial out shift register is initially clear. We wish to store the nibble What will be the 4-bit pattern after the second clock pulse? (Right-most bit first.) Click here for detail 1111 rep Question No: 20 ( Marks: 1 ) - Please choose one The address from which the data is read, is provided by Depends on circuitry None of given options RAM Microprocessor (Page 397) Question No: 21 ( Marks: 1 ) - Please choose one FIFO is an acronym for First In, First Out (Page 424) Fly in, Fly Out Fast in, Fast Out None of given options Question No: 22 ( Marks: 1 ) - Please choose one LUT is acronym for Look Up Table (Page 439) rep Local User Terminal Least Upper Time Period None of given options Question No: 23 ( Marks: 1 ) - Please choose one The voltage gain of the Inverting Amplifier is given by the relation V out / V in = - R f / R i (Page 446) V out / R f = - V in / R i R f / V in = - R i / V out R f / V in = R i / V out

187 Question No: 24 ( Marks: 1 ) - Please choose one of a D/A converter is determined by comparing the actual output of a D/A converter with the expected output. Resolution Accuracy (Page 460) rep Quantization Missing Code Question No: 25 ( Marks: 1 ) - Please choose one Above is the circuit diagram of. Asynchronous up-counter (Page 270) Asynchronous down-counter Synchronous up-counter Synchronous down-counter Question No: 26 ( Marks: 1 ) - Please choose one The sequence of states that are implemented by a n-bit Johnson counter is n+2 (n plus 2) 2n (n multiplied by 2) (Page 354) 2 n (2 raise to power n) n 2 (n raise to power 2) Question No: 1 ( Marks: 1 ) - Please choose one "A + B = B + A" is Demorgan s Law Distributive Law Commutative Law (Page 72) Associative Law FINALTERM EXAMINATION Spring 2010

188 Question No: 2 ( Marks: 1 ) - Please choose one The diagram given below represents Demorgans law Associative law Product of sum form Sum of product form (Page 78) rep Question No: 3 ( Marks: 1 ) - Please choose one Following is standard POS expression True (Lecture 9) False Question No: 4 ( Marks: 1 ) - Please choose one An alternate method of implementing Comparators which allows the Comparators to be easily cascaded without the need for extra logic gates is Using a single comparator Using Iterative Circuit based Comparators (Page 155) Connecting comparators in vertical hierarchy Extra logic gates are always required. Question No: 5 ( Marks: 1 ) Demultiplexer is also called - Please choose one Data selector Data router Data distributor (Page 178) Data encoder Question No: 6 ( Marks: 1 ) - Please choose one The operation of J-K flip-flop is similar to that of the SR flip-flop except that the J-K flip-flop Doesn t have an invalid state (Page 232) rep Sets to clear when both J = 0 and K = 0 It does not show transition on change in pulse It does not accept asynchronous inputs

189 Question No: 7 ( Marks: 1 ) - Please choose one A positive edge-triggered flip-flop changes its state when Low-to-high transition of clock (Page 228) rep High-to-low transition of clock Enable input (EN) is set Preset input (PRE) is set Question No: 8 ( Marks: 1 ) - Please choose one A flip-flop is connected to +5 volts and it draws 5 ma of current during its operation, the power dissipation of the flip-flop is 10 mw 25 mw (Page 242) 64 mw 1024 Question No: 9 ( Marks: 1 ) - Please choose one counters as the name indicates are not triggered simultaneously. Asynchronous (Page 269) Synchronous Positive-Edge triggered Negative-Edge triggered Question No: 10 ( Marks: 1 ) - Please choose one 74HC163 has two enable input pins which are and ENP, ENT (Page 285) rep ENI, ENC ENP, ENC ENT, ENI Question No: 11 ( Marks: 1 ) - Please choose one The divide-by-60 counter in digital clock is implemented by using two cascading counters: Mod-6, Mod-10 (Page 299) Mod-50, Mod-10 Mod-10, Mod-50 Mod-50, Mod-6

190 Question No: 12 ( Marks: 1 ) - Please choose one In a state diagram, the transition from a current state to the next state is determined by Current state and the inputs (Page 332) Current state and outputs Previous state and inputs Previous state and outputs Question No: 13 ( Marks: 1 ) - Please choose one A synchronous decade counter will have flip-flops 3 4 (Page 281) 7 10 Question No: 14 ( Marks: 1 ) - Please choose one is used to minimize the possible no. of states of a circuit. State assignment (Page 341) rep State reduction Next state table State diagram Question No: 15 ( Marks: 1 ) - Please choose one A multiplexer with a register circuit converts Serial data to parallel Parallel data to serial Serial data to serial Parallel data to parallel (Page 356) rep Question No: 16 ( Marks: 1 ) - Please choose one The alternate solution for a demultiplexer-register combination circuit is Parallel in / Serial out shift register Serial in / Parallel out shift register (Page 356) Parallel in / Parallel out shift register Serial in / Serial Out shift register Question No: 17 ( Marks: 1 ) - Please choose one A GAL is essentially a. Non-reprogrammable PAL PAL that is programmed only by the manufacturer Very large PAL Reprogrammable PAL (Page 183) rep

191 Question No: 18 ( Marks: 1 ) - Please choose one The output of this circuit is always. 1 0 A Click here For detail rep Question No: 20 ( Marks: 1 ) - Please choose one in, all the columns in the same row are either read or written. Sequential Access MOS Access FAST Mode Page Access (Page 413) rep None of given options Question No: 21 ( Marks: 1 ) - Please choose one FIFO is an acronym for First In, First Out (Page 424) rep Fly in, Fly Out Fast in, Fast Out None of given options Question No: 22 ( Marks: 1 ) - Please choose one In order to synchronize two devices that consume and produce data at different rates, we can use Read Only Memory Fist In First Out Memory (Page 425) rep Flash Memory Fast Page Access Mode Memory Question No: 23 ( Marks: 1 ) - Please choose one A frequency counter Counts pulse width Counts no. of clock pulses in 1 second (Page 301) rep Counts high and low range of given clock pulse None of given options

192 Question No: 24 ( Marks: 1 ) - Please choose one The sequence of states that are implemented by a n-bit Johnson counter is n+2 (n plus 2) 2n (n multiplied by 2) (Page 354) rep 2 n (2 raise to power n) n 2 (n raise to power 2) Question No: 25 ( Marks: 1 ) - Please choose one Stack is an acronym for FIFO memory LIFO memory (Page 429) rep Flash Memory Bust Flash Memory Question No: 26 ( Marks: 1 ) - Please choose one The 4-bit 2 s complement representation of +5 is (Page 22) FINALTERM EXAMINATION Spring 2010 Question No: 1 ( Marks: 1 ) The storage cell in SRAM is a flip flop a capacitor (Page 407) a fuse a magnetic domain - Please choose one Question No: 2 ( Marks: 1 ) - Please choose one What is the difference between a D latch and a D flip-flop? The D latch has a clock input. The D flip-flop has an enable input. The D latch is used for faster operation. The D flip-flop has a clock input. Click here for detail

193 Question No: 3 ( Marks: 1 ) - Please choose one For a positive edge-triggered J-K flip-flop with both J and K HIGH, the outputs will if the clock goes HIGH. toggle Click here for detail set reset not change Question No: 4 ( Marks: 1 ) - Please choose one The OR gate performs Boolean. multiplication subtraction division addition (Page 42) Question No: 5 ( Marks: 1 ) - Please choose one If an S-R latch has a 1 on the S input and a 0 on the R input and then the S input goes to 0, the latch will be set (Page 219) reset invalid clear 5. Determine the values of A, B, C, and D that make the sum term A(bar) + B+C(bar)+D equal to zero. A = 1, B = 0, C = 0, D = 0 A = 1, B = 0, C = 1, D = 0 (Lecture 8) A = 0, B = 1, C = 0, D = 0 A = 1, B = 0, C = 1, D = 1 Question No: 6 ( Marks: 1 ) - Please choose one The power dissipation, PD, of a logic gate is the product of the dc supply voltage and the peak current Click here for detail dc supply voltage and the average supply current ac supply voltage and the peak current ac supply voltage and the average supply current Question No: 7 ( Marks: 1 ) - Please choose one A Karnaugh map is similar to a truth table because it presents all the possible values of input variables and the resulting output of each value. True Click here for detail False Question No: 8 ( Marks: 1 ) - Please choose one NOR Gate can be used to perform the operation of AND, OR and NOT Gate True (Page 50) False

194 Question No: 9 ( Marks: 1 ) - Please choose one Using multiplexer as parallel to serial converter requires connected to the multiplexer A parallel to serial converter circuit (Page 244) A counter circuit A BCD to Decimal decoder A 2-to-8 bit decoder Question No: 10 ( Marks: 1 ) - Please choose one The 3-variable Karnaugh Map (K-Map) has cells for min or max terms 4 8 (Page 89) Question No: 11 ( Marks: 1 ) - Please choose one In designing any counter the transition from a current state to the next sate is determined by Current state and inputs (Page 332) Only inputs Only current state current state and outputs Question No: 12 ( Marks: 1 ) - Please choose one Sum term (Max term) is implemented using gates OR (Page 78) AND NOT OR-AND Question No: 13 ( Marks: 1 ) - Please choose one Given the state diagram of an up/down counter, we can find The next state of a given present state (Page 371) rep The previous state of a given present state Both the next and previous states of a given state The state diagram shows only the inputs/outputs of a given states Question No: 14 ( Marks: 1 ) - Please choose one AT T0 THE VALUE STORED IN A 4-BIT LEFT SHIFT WAS 1. WHAT WILL BE THE VALUE OF REGISTER AFTER THREE CLOCK PULSES? (not sure)

195 Question No: 15 ( Marks: 1 ) - Please choose one WHEN BOTH THE INPUTS OF EDGE-TRIGGERED J-K FLOP-FLOP ARE SET TO LOGIC ZERO THE FLOP-FLOP IS TRIGGERED Q=0 AND Q =1 Q=1 AND Q =0 (Page 233) THE OUTPUT OF FLIP-FLOP REMAINS UNCHANGED Question No: 16 ( Marks: 1 ) - Please choose one If S=1 and R=0, then Q(t+1) = for positive edge triggered flip-flop 0 1 (Page 230) Invalid Input is invalid If S=1 and R=1, then Q(t+1) = for negative edge triggered flip-flop 0 1 Invalid (Page 233) Input is invalid Question No: 17 ( Marks: 1 ) - Please choose one The minimum time for which the input signal has to be maintained at the input of flip-flop is called of the flip-flop. Set-up time Hold time (Page 242) rep Pulse Interval time Pulse Stability time (PST) Question No: 18 ( Marks: 1 ) - Please choose one We have a digital circuit. Different parts of circuit operate at different clock frequencies (4MHZ, 2MHZ and 1MHZ), but we have a single clock source having a fix clock frequency (4MHZ), we can get help by Using S-R Flop-Flop D-flipflop J-K flip-flop (Page 252) T-Flip-Flop Question No: 19 ( Marks: 1 ) - Please choose one A counter is implemented using three (3) flip-flops, possibly it will have maximum output status (Page 272) 15

196 Question No: 20 ( Marks: 1 ) - Please choose one In Q output of the last flip-flop of the shift register is connected to the data input of the first flip-flop of the shift register. Moore machine Meally machine Johnson counter Ring counter (Page 355) Question No: 21 ( Marks: 1 ) - Please choose one The of a ROM is the time it takes for the data to appear at the Data Output of the ROM chip after an address is applied at the address input lines Write Time Recycle Time Refresh Time Access Time (Page 417) Question No: 22 ( Marks: 1 ) - Please choose one Bi-stable devices remain in either of their states unless the inputs force the device to switch its state Ten Eight Three Two (Page 262) Question No: 23 ( Marks: 1 ) - Please choose one occurs when the same clock signal arrives at different times at different clock inputs due to propagation delay. Race condition Clock Skew (Page 226) rep Ripple Effect None of given options Question No: 24 ( Marks: 1 ) - Please choose one The alternate solution for a multiplexer and a register circuit is Parallel in / Serial out shift register (Page 356) Serial in / Parallel out shift register Parallel in / Parallel out shift register Serial in / Serial Out shift register Question No: 25 ( Marks: 1 ) - Please choose one Stack is an acronym for FIFO memory LIFO memory (Page 429) rep Flash Memory Bust Flash Memory

197 Question No: 26 ( Marks: 1 ) - Please choose one A full-adder has a Cin = 0. What are the sum (<PRIVATE "TYPE=PICT;ALT=sigma"> ) and the carry (Cout) when A = 1 and B = 1? = 0, Cout = 0 = 0, Cout = 1 (Page 135) = 1, Cout = 0 = 1, Cout = 1 Question No: 27 ( Marks: 1 ) - Please choose one THE GLITCHES DUE TO RACE CONDITION CAN BE AVOIDED BY USING A GATED FLIP-FLOPS PULSE TRIGGERED FLIP-FLOPS POSITIVE-EDGE TRIGGERED FLIP-FLOPS NEGATIVE-EDGE TRIGGERED FLIP-FLOPS (Page 267) Question No: 28 ( Marks: 1 ) - Please choose one The design and implementation of synchronous counters start from Truth table k-map state table state diagram (Page 319) Question No: 29 ( Marks: 1 ) - Please choose one THE HOURS COUNTER IS IMPLEMENTED USING ONLY A SINGLE MOD-12 COUNTER IS REQUIRED MOD-10 AND MOD-6 COUNTERS MOD-10 AND MOD-2 COUNTERS A SINGLE DECADE COUNTER AND A FLIP-FLOP (Page 299) Question No: 30 ( Marks: 1 ) - Please choose one Given the state diagram of an up/down counter, we can find The next state of a given present state (Page 371) rep The previous state of a given present state Both the next and previous states of a given state The state diagram shows only the inputs/outputs of a given states Question No: 31 ( Marks: 1 ) - Please choose one LUT is acronym for Look Up Table (Page 439) rep Local User Terminal Least Upper Time Period None of given options

198 Question No: 32 ( Marks: 1 ) - Please choose one of a D/A converter is determined by comparing the actual output of a D/A converter with the expected output. Resolution Accuracy (Page 460) rep Quantization Missing Code Question No: 33 ( Marks: 1 ) - Please choose one is used to simplify the circuit that determines the next state. State diagram Next state table State reduction State assignment (Page 335) rep Question No: 34 ( Marks: 1 ) - Please choose one The high density FLASH memory cell is implemented using 1 floating-gate MOS transistor (Page 419) 2 floating-gate MOS transistors 4 floating-gate MOS transistors 6 floating-gate MOS transistors Question No: 35 ( Marks: 1 ) - Please choose one Q2 :=Q1 OR X OR Q3 The above ABEL expression will be Q2:= Q1 $ X $ Q3 Q2:= Q1 # X # Q3 (Page 210) Q2:= Q1 & X & Q3 Q2:= Q1! X! Q3 Question No: 36 ( Marks: 1 ) - Please choose one Generally, the Power dissipation of devices remains constant throughout their operation. TTL (Page 65) CMOS 3.5 series CMOS 5 Series Power dissipation of all circuits increases with time. Question No: 37 ( Marks: 1 ) - Please choose one When the control line in tri-state buffer is high the buffer operates like a gate AND OR NOT (Page 196) XOR

199 Question No: 38 ( Marks: 1 ) - Please choose one 3.3 v CMOS series is characterized by and as compared to the 5 v CMOS series. Low switching speeds, high power dissipation Fast switching speeds, high power dissipation Fast switching speeds, very low power dissipation (Page 61) Low switching speeds, very low power dissipation Question No: 1 ( Marks: 1 ) - Please choose one The output of an AND gate is one when All of the inputs are one (Page 40) Any of the input is one Any of the input is zero All the inputs are zero Question No: 2 ( Marks: 1 ) - Please choose one The OR Gate performs a Boolean function Addition (Page 42) rep Subtraction Multiplication Division FINALTERM EXAMINATION Fall 2009 Question No: 3 ( Marks: 1 ) - Please choose one A Karnaugh map is similar to a truth table because it presents all the possible values of input variables and the resulting output of each value. True rep False Click here for Detail Question No: 4 ( Marks: 1 ) - Please choose one The binary numbers A = 1100 and B = 1001 are applied to the inputs of a comparator. What are the output levels? A > B = 1, A < B = 0, A < B = 1 A > B = 0, A < B = 1, A = B = 0 A > B = 1, A < B = 0, A = B = 0 (Page 109) A > B = 0, A < B = 1, A = B = 1

200 Question No: 5 ( Marks: 1 ) - Please choose one AND Gate level NOT Gate level OR Gate level The diagram above shows the general implementation of form boolean arbitrary POS (Page 122) SOP Question No: 6 ( Marks: 1 ) - Please choose one The device shown here is most likely a Comparator Multiplexer Click here for detail Demultiplexer Parity generator Question No: 7 ( Marks: 1 ) - Please choose one Demultiplexer converts data to data Parallel data, serial data Serial data, parallel data (Page 356) Encoded data, decoded data All of the given options.

201 Question No: 8 ( Marks: 1 ) - Please choose one Flip flops are also called Bi-stable dualvibrators Bi-stable transformer Bi-stable multivibrators (Page 228) rep Bi-stable singlevibrators Question No: 9 ( Marks: 1 ) - Please choose one If S=1 and R=0, then Q(t+1) = for positive edge triggered flip-flop 0 1 (Page 230) Invalid Input is invalid Question No: 10 ( Marks: 1 ) - Please choose one If S=1 and R=1, then Q(t+1) = for negative edge triggered flip-flop 0 1 Invalid (Page 230) Input is invalid Question No: 11 ( Marks: 1 ) - Please choose one The operation of J-K flip-flop is similar to that of the SR flip-flop except that the J-K flip-flop Doesn t have an invalid state (Page 232) rep Sets to clear when both J = 0 and K = 0 It does not show transition on change in pulse It does not accept asynchronous inputs Question No: 12 ( Marks: 1 ) - Please choose one The minimum time for which the input signal has to be maintained at the input of flip-flop is called of the flip-flop. Set-up time Hold time (Page 242) Pulse Interval time Pulse Stability time (PST) Question No: 13 ( Marks: 1 ) - Please choose one We have a digital circuit. Different parts of circuit operate at different clock frequencies (4MHZ, 2MHZ and 1MHZ), but we have a single clock source having a fix clock frequency (4MHZ), we can get help by Using S-R Flop-Flop D-flipflop J-K flip-flop (Page 252) T-Flip-Flop

202 Question No: 14 ( Marks: 1 ) - Please choose one In asynchronous digital systems all the circuits change their state with respect to a common clock True False (Page 245) Question No: 15 ( Marks: 1 ) - Please choose one A positive edge-triggered flip-flop changes its state when Low-to-high transition of clock (Page 228) rep High-to-low transition of clock Enable input (EN) is set Preset input (PRE) is set Question No: 16 ( Marks: 1 ) - Please choose one A negative edge-triggered flip-flop changes its state when Enable input (EN) is set Preset input (PRE) is set Low-to-high transition of clock High-to-low transition of clock (Page 228) Question No: 17 ( Marks: 1 ) - Please choose one A flip-flop is connected to +5 volts and it draws 5 ma of current during its operation, the power dissipation of the flip-flop is 10 mw 25 mw (Page 242) 64 mw 1024 Question No: 18 ( Marks: 1 ) - Please choose one occurs when the same clock signal arrives at different times at different clock inputs due to propagation delay. Race condition Clock Skew (Page 226) rep Ripple Effect None of given options Question No: 19 ( Marks: 1 ) - Please choose one A counter is implemented using three (3) flip-flops, possibly it will have maximum output status (Page 272) rep 15

203 Question No: 20 ( Marks: 1 ) - Please choose one A divide-by-50 counter divides the input signal to a 1 Hz signal. 10 Hz 50 Hz (Page 298) 100 Hz 500 Hz Question No: 21 ( Marks: 1 ) - Please choose one The design and implementation of synchronous counters start from Truth table k-map state table state diagram (Page 319) Question No: 22 ( Marks: 1 ) - Please choose one A synchronous decade counter will have flip-flops 3 4 (Page 281) rep 7 10 Question No: 23 ( Marks: 1 ) - Please choose one The output of this circuit is always. 1 0 A Click here for Detail rep Question No: 24 ( Marks: 1 ) - Please choose one At T0 the value stored in a 4-bit left shift was 1. What will be the value of register after three clock pulses? (not sure) rep

204 Question No: 25 ( Marks: 1 ) - Please choose one In the Q output of the last flip-flop of the shift register is connected to the data input of the first flipflop. Moore machine Meally machine Johnson counter (Page 354 ) Ring counter Question No: 26 ( Marks: 1 ) - Please choose one In Q output of the last flip-flop of the shift register is connected to the data input of the first flip-flop of the shift register. Moore machine Meally machine Johnson counter Ring counter (Page 355) rep Question No: 27 ( Marks: 1 ) - Please choose one Which is not characteristic of a shift register? Serial in/parallel in (Page 346) Serial in/parallel out Parallel in/serial out Parallel in/parallel out Question No: 28 ( Marks: 1 ) - Please choose one Assume that a 4-bit serial in/serial out shift register is initially clear. We wish to store the nibble What will be the 4-bit pattern after the second clock pulse? (Right-most bit first.) Click here for detail rep Question No: 29 ( Marks: 1 ) - Please choose one The of a ROM is the time it takes for the data to appear at the Data Output of the ROM chip after an address is applied at the address input lines Write Time Recycle Time Refresh Time Access Time (Page 417) rep

205 Question No: 30 ( Marks: 1 ) - Please choose one The sequence of states that are implemented by a n-bit Johnson counter is n+2 (n plus 2) 2n (n multiplied by 2) (Page 354) rep 2 n (2 raise to power n) n 2 (n raise to power 2) FINALTERM EXAMINATION Fall 2009 Question No: 1 ( Marks: 1 ) - Please choose one NOR Gate can be used to perform the operation of AND, OR and NOT Gate FALSE TRUE (Page 250) Question No: 2 ( Marks: 1 ) - Please choose one The output of an XNOR gate is 1 when I) All the inputs are zero II) Any of the inputs is zero III) Any of the inputs is one IV) All the inputs are one I Only IV Only I and IV only II and III only (Page 53) Question No: 3 ( Marks: 1 ) - Please choose one NAND gate is formed by connecting AND Gate and then NOT Gate (Page 45) NOT Gate and then AND Gate AND Gate and then OR Gate OR Gate and then AND Gate Question No: 4 ( Marks: 1 ) - Please choose one Consider A=1,B=0,C=1. A, B and C represent the input of three bit NAND gate the output of the NAND gate will be Zero One (Page 46) Undefined No output as input is invalid

206 Question No: 5 ( Marks: 1 ) - Please choose one The capability that allows the PLDs to be programmed after they have been installed on a circuit board is called Radiation-Erase programming method (REPM) In-System Programming (ISP) (Page 194) In-chip Programming (ICP) Electronically-Erase programming method(eepm) Question No: 6 ( Marks: 1 ) - Please choose one The ABEL symbol for OR operation is! & # $ (Page 201) rep Question No: 7 ( Marks: 1 ) - Please choose one If S=1 and R=1, then Q(t+1) = for negative edge triggered flip-flop 0 1 Invalid (Page 230) rep Input is invalid Question No: 8 ( Marks: 1 ) - Please choose one The operation of J-K flip-flop is similar to that of the SR flip-flop except that the J-K flip-flop Doesn t have an invalid state (Page 232) rep Sets to clear when both J = 0 and K = 0 It does not show transition on change in pulse It does not accept asynchronous inputs Question No: 9 ( Marks: 1 ) - Please choose one For a gated D-Latch if EN=1 and D=1 then Q(t+1) = 0 1 (Page 227) rep Q(t) Invalid Question No: 10 ( Marks: 1 ) - Please choose one In asynchronous digital systems all the circuits change their state with respect to a common clock True False (Page 245) rep

207 Question No: 11 ( Marks: 1 ) - Please choose one A positive edge-triggered flip-flop changes its state when Low-to-high transition of clock (Page 228) rep High-to-low transition of clock Enable input (EN) is set Preset input (PRE) is set Question No: 12 ( Marks: 1 ) - Please choose one is one of the examples of asynchronous inputs. J-K input S-R input D input Clear Input (CLR) (Page 235) rep Question No: 13 ( Marks: 1 ) - Please choose one The input overrides the input Asynchronous, synchronous (Page 369) rep Synchronous, asynchronous Preset input (PRE), Clear input (CLR) Clear input (CLR), Preset input (PRE) Question No: 14 ( Marks: 1 ) - Please choose one Following Is the circuit diagram of mono-stable device which gate will be replaced by the red colored rectangle in the circuit. AND NAND NOR XNOR (Page 262) Question No: 15 ( Marks: 1 ) - Please choose one In outputs depend only on the combination of current state and inputs. Mealy machine (Page 332) Moore Machine State Reduction table State Assignment table

208 Question No: 16 ( Marks: 1 ) - Please choose one is used to simplify the circuit that determines the next state. State diagram Next state table State reduction State assignment (Page 335) rep Question No: 17 ( Marks: 1 ) - Please choose one A multiplexer with a register circuit converts Serial data to parallel Parallel data to serial (Page 356) rep Serial data to serial Parallel data to parallel Question No: 18 ( Marks: 1 ) - Please choose one In asynchronous transmission when the transmission line is idle, It is set to logic low It is set to logic high (Page 356) rep Remains in previous state State of transmission line is not used to start transmission Question No: 19 ( Marks: 1 ) - Please choose one In the following statement Z PIN 20 ISTYPE reg.invert ; The keyword reg.invert indicates An inverted register input An inverted register input at pin 20 Active-high Registered Mode output Active-low Registered Mode output (Page 360) Question No: 20 ( Marks: 1 ) A Nibble consists of bits - Please choose one 2 4 (Page 394) 8 16

209 Question No: 21 ( Marks: 1 ) - Please choose one The output of this circuit is always. 1 0 A Click here for detail rep Question No: 22 ( Marks: 1 ) - Please choose one At T0 the value stored in a 4-bit left shift was 1. What will be the value of register after three clock pulses? (not sure) rep Question No: 23 ( Marks: 1 ) - Please choose one A bidirectional 4-bit shift register is storing the nibble Its input is LOW. The nibble 0111 is waiting to be entered on the serial data-input line. After two clock pulses, the shift register is storing Click he re for detail Question No: 24 ( Marks: 1 ) - Please choose one The high density FLASH memory cell is implemented using 1 floating-gate MOS transistor (Page 419) rep 2 floating-gate MOS transistors 4 floating-gate MOS transistors 6 floating-gate MOS transistors Question No: 25 ( Marks: 1 ) - Please choose one In order to synchronize two devices that consume and produce data at different rates, we can use Read Only Memory Fist In First Out Memory (Page 425) Flash Memory Fast Page Access Mode Memory

210 Question No: 26 ( Marks: 1 ) - Please choose one If the FIFO Memory output is already filled with data then It is locked; no data is allowed to enter It is not locked; the new data overwrites the previous data. Previous data is swapped out of memory and new data enters None of given options Question No: 27 ( Marks: 1 ) - Please choose one The process of converting the analogue signal into a digital representation (code) is known as Strobing Amplification Quantization (Page 445) Digitization Question No: 28 ( Marks: 1 ) - Please choose one Above is the circuit diagram of. Asynchronous up-counter (Page 270) rep Asynchronous down-counter Synchronous up-counter Synchronous down-counter Question No: 29 ( Marks: 1 ) - Please choose one ( A B)(A B C)(A C) is an example of Product of sum form (Page 77) Sum of product form Demorgans law Associative law Question No: 30 ( Marks: 1 ) - Please choose one Q2 :=Q1 OR X OR Q3 The above ABEL expression will be Q2:= Q1 $ X $ Q3 Q2:= Q1 # X # Q3 (Page 210) Q2:= Q1 & X & Q3 Q2:= Q1! X! Q3

211 FINALTERM EXAMINATION Fall 2009 Question No: 1 ( Marks: 1 ) - Please choose one Caveman number system is Base number system 2 5 (Page 11) Question No: 2 ( Marks: 1 ) - Please choose one The output of an XOR gate is zero (0) when I) All the inputs are zero II) Any of the inputs is zero III) Any of the inputs is one IV) All the inputs are one I Only IV Only I and IV only (Page 53) II and III only Question No: 3 ( Marks: 1 ) - Please choose one The decimal 17 in BCD will be represented as 10001(right opt is not given) (According to rule) rep Question No: 4 ( Marks: 1 ) - Please choose one A Karnaugh map is similar to a truth table because it presents all the possible values of input variables and the resulting output of each value. True Click here for Detail rep False Question No: 5 ( Marks: 1 ) - Please choose one The simplest and most commonly used Decoders are the Decoders n to 2n (Page 158) (n-1) to 2n (n-1) to (2n-1) n to 2n-1

212 Question No: 6 ( Marks: 1 ) - Please choose one The Encoder is used as a keypad encoder. 2-to-8 encoder 4-to-16 encoder BCD-to-Decimal Decimal-to-BCD Priority (Page 166) Question No: 7 ( Marks: 1 ) - Please choose one 3-to-8 decoder can be used to implement Standard SOP and POS Boolean expressions True (Page 161) False Question No: 8 ( Marks: 1 ) - Please choose one If S=1 and R=0, then Q(t+1) = for positive edge triggered flip-flop 0 1 (Page 230) Invalid Input is invalid Question No: 9 ( Marks: 1 ) - Please choose one If the S and R inputs of the gated S-R latch are connected together using a gate then there is only a single input to the latch. The input is represented by D instead of S or R (A gated D-Latch) AND OR NOT (Page 226) XOR Question No: 10 ( Marks: 1 ) - Please choose one In asynchronous digital systems all the circuits change their state with respect to a common clock True False (Page 245) rep Question No: 11 ( Marks: 1 ) - Please choose one The low to high or high to low transition of the clock is considered to be a(n) State Edge (Page 228) Trigger One-shot

213 Question No: 12 ( Marks: 1 ) - Please choose one A positive edge-triggered flip-flop changes its state when Low-to-high transition of clock (Page 228) High-to-low transition of clock Enable input (EN) is set Preset input (PRE) is set Question No: 13 ( Marks: 1 ) - Please choose one RCO Stands for Reconfiguration Counter Output Reconfiguration Clock Output Ripple Counter Output Ripple Clock Output (Page 285) Question No: 14 ( Marks: 1 ) - Please choose one Bi-stable devices remain in either of their states unless the inputs force the device to switch its state Ten Eight Three Two (Page 262) rep Question No: 15 ( Marks: 1 ) - Please choose one is one of the examples of asynchronous inputs. J-K input S-R input D input Clear Input (CLR) (Page 255) rep Question No: 16 ( Marks: 1 ) - Please choose one occurs when the same clock signal arrives at different times at different clock inputs due to propagation delay. Race condition Clock Skew (Page 226) rep Ripple Effect None of given options Question No: 17 ( Marks: 1 ) - Please choose one A transparent mode means The changes in the data at the inputs of the latch are seen at the output (Page 245) The changes in the data at the inputs of the latch are not seen at the output Propagation Delay is zero (Output is immediately changed when clock signal is applied) Input Hold time is zero (no need to maintain input after clock transition)

214 Question No: 18 ( Marks: 1 ) - Please choose one In outputs depend only on the current state. Mealy machine Moore Machine (Page 332) State Reduction table State Assignment table Question No: 19 ( Marks: 1 ) - Please choose one The alternate solution for a multiplexer and a register circuit is Parallel in / Serial out shift register (Page 356) rep Serial in / Parallel out shift register Parallel in / Parallel out shift register Serial in / Serial Out shift register Question No: 20 ( Marks: 1 ) - Please choose one The alternate solution for a demultiplexer-register combination circuit is Parallel in / Serial out shift register Serial in / Parallel out shift register Parallel in / Parallel out shift register Serial in / Serial Out shift register (Page 356) rep Question No: 21 ( Marks: 1 ) - Please choose one In asynchronous transmission when the transmission line is idle, It is set to logic low It is set to logic high (Page 356) rep Remains in previous state State of transmission line is not used to start transmission Question No: 22 ( Marks: 1 ) - Please choose one Smallest unit of binary data is a Bit (Page 394) Nibble Byte Word Question No: 23 ( Marks: 1 ) - Please choose one A Nibble consists of bits 2 4 (Page 394) rep 8 16

215 Question No: 24 ( Marks: 1 ) - Please choose one A GAL is essentially a. Non-reprogrammable PAL PAL that is programmed only by the manufacturer Very large PAL Reprogrammable PAL (Page 183) rep Question No: 25 ( Marks: 1 ) - Please choose one A 8-bit serial in / parallel out shift register contains the value 8, clock signal(s) will be required to shift the value completely out of the register (Page 356) rep Question No: 26 ( Marks: 1 ) - Please choose one DRAM stands for Dynamic RAM (Page 407) rep Data RAM Demoduler RAM None of given options Question No: 27 ( Marks: 1 ) - Please choose one FIFO is an acronym for First In, First Out (Page 424) rep Fly in, Fly Out Fast in, Fast Out None of given options (Diagram is missing) Question No: 28 ( Marks: 1 ) - Please choose one In the circuit diagram of 3-bit synchronous counter shown above, The red rectangle would be replaced by which gate? AND OR NAND XNOR Question No: 29 ( Marks: 1 ) - Please choose one The sequence of states that are implemented by a n-bit Johnson counter is n+2 (n plus 2) 2n (n multiplied by 2) 2n (2 raise to power n) n2 (n raise to power 2) (Page 354) rep

216 Question No: 30 ( Marks: 1 ) - Please choose one Stack is an acronym for FIFO memory LIFO memory (Page 429) rep Flash Memory Bust Flash Memory FINALTERM EXAMINATION Fall 2009 Question No: 1 ( Marks: 1 ) - Please choose one The diagram given below represents Demorgans law Associative law Product of sum form Sum of product form (Page 78) rep Question No: 2 ( Marks: 1 ) - Please choose one Excess-8 code assigns to (Page 34) rep

217 Question No: 3 ( Marks: 1 ) - Please choose one NOR gate is formed by connecting OR Gate and then NOT Gate (Page 47) NOT Gate and then OR Gate AND Gate and then OR Gate OR Gate and then AND Gate Question No: 4 ( Marks: 1 ) - Please choose one A full-adder has a Cin = 0. What are the sum (<PRIVATE "TYPE=PICT;ALT=sigma"> ) and the carry (Cout) when A = 1 and B = 1? = 0, Cout = 0 = 0, Cout = 1 (Page 135) = 1, Cout = 0 = 1, Cout = 1 rep Question No: 5 ( Marks: 1 ) - Please choose one A particular half adder has 2 INPUTS AND 1 OUTPUT 2 INPUTS AND 2 OUTPUT (Page 134) 3 INPUTS AND 1 OUTPUT 3 INPUTS AND 2 OUTPUT Question No: 6 ( Marks: 1 ) - Please choose one THE FOUR OUTPUTS OF TWO 4-INPUT MULTIPLEXERS, CONNECTED TO FORM A 16-INPUT MULTIPLEXER, ARE CONNECTED TOGETHER THROUGH A 4-INPUT GATE AND OR (Page 171) NAND XOR Question No: 7 ( Marks: 1 ) - Please choose one A FIELD-PROGRAMMABLE LOGIC ARRAY CAN BE PROGRAMMED BY THE USER AND NOT BY THE MANUFACTURER. TRUE (Page 182) FALSE Question No: 8 ( Marks: 1 ) - Please choose one Flip flops are also called Bi-stable dualvibrators Bi-stable transformer Bi-stable multivibrators (Page 228) Bi-stable singlevibrators

218 Question No: 9 ( Marks: 1 ) - Please choose one A positive edge-triggered flip-flop changes its state when Low-to-high transition of clock (Page 228) High-to-low transition of clock Enable input (EN) is set Preset input (PRE) is set Question No: 10 ( Marks: 1 ) - Please choose one is one of the examples of synchronous inputs. J-K input (Page 235) EN input Preset input (PRE) Clear Input (CLR) Question No: 11 ( Marks: 1 ) - Please choose one THE GLITCHES DUE TO RACE CONDITION CAN BE AVOIDED BY USING A GATED FLIP-FLOPS PULSE TRIGGERED FLIP-FLOPS POSITIVE-EDGE TRIGGERED FLIP-FLOPS NEGATIVE-EDGE TRIGGERED FLIP-FLOPS (Page 267) rep Question No: 12 ( Marks: 1 ) - Please choose one The design and implementation of synchronous counters start from Truth table k-map state table state diagram (Page 319) rep Question No: 13 ( Marks: 1 ) - Please choose one THE HOURS COUNTER IS IMPLEMENTED USING ONLY A SINGLE MOD-12 COUNTER IS REQUIRED MOD-10 AND MOD-6 COUNTERS MOD-10 AND MOD-2 COUNTERS A SINGLE DECADE COUNTER AND A FLIP-FLOP (Page 299) rep Question No: 14 ( Marks: 1 ) - Please choose one Given the state diagram of an up/down counter, we can find The next state of a given present state (Page 371) rep The previous state of a given present state Both the next and previous states of a given state The state diagram shows only the inputs/outputs of a given states

219 Question No: 15 ( Marks: 1 ) - Please choose one In outputs depend only on the current state. Mealy machine Moore Machine (Page 332) rep State Reduction table State Assignment table Question No: 16 ( Marks: 1 ) - Please choose one A synchronous decade counter will have flip-flops 3 4 (Page 281) 7 10 Question No: 17 ( Marks: 1 ) - Please choose one A multiplexer with a register circuit converts Serial data to parallel Parallel data to serial (Page 356) rep Serial data to serial Parallel data to parallel Question No: 18 ( Marks: 1 ) - Please choose one The alternate solution for a multiplexer and a register circuit is Parallel in / Serial out shift register (Page 356) Serial in / Parallel out shift register Parallel in / Parallel out shift register Serial in / Serial Out shift register Question No: 19 ( Marks: 1 ) - Please choose one AT T0 THE VALUE STORED IN A 4-BIT LEFT SHIFT WAS 1. WHAT WILL BE THE VALUE OF REGISTER AFTER THREE CLOCK PULSES? (not sure) rep Question No: 20 ( Marks: 1 ) - Please choose one A 8-bit serial in / parallel out shift register contains the value 8, clock signal(s) will be required to shift the value completely out of the register (Page 356)

220 Question No: 21 ( Marks: 1 ) - Please choose one 5-BIT JOHNSON COUNTER SEQUENCES THROUGH STATES 7 10 (Page 354) rep Question No: 22 ( Marks: 1 ) - Please choose one In Q output of the last flip-flop of the shift register is connected to the data input of the first flip-flop of the shift register. Moore machine Meally machine Johnson counter Ring counter (Page 355) Question No: 23 ( Marks: 1 ) - Please choose one DRAM stands for Dynamic RAM (Page 407) rep Data RAM Demoduler RAM None of given options Question No: 24 ( Marks: 1 ) - Please choose one If the FIFO Memory output is already filled with data then It is locked; no data is allowed to enter It is not locked; the new data overwrites the previous data. Previous data is swapped out of memory and new data enters None of given options Question No: 25 ( Marks: 1 ) - Please choose one LUT is acronym for Look Up Table (Page 439) rep Local User Terminal Least Upper Time Period None of given options Question No: 26 ( Marks: 1 ) - Please choose one of a D/A converter is determined by comparing the actual output of a D/A converter with the expected output. Resolution Accuracy (Page 460) rep Quantization Missing Code

221 (Diagram is missing) Question No: 27 ( Marks: 1 ) - Please choose one In the circuit diagram of 3-bit synchronous counterthe red rectangle, shown above would be replaced which gate? AND OR NAND XNOR Question No: 28 ( Marks: 1 ) - Please choose one WHEN BOTH THE INPUTS OF EDGE-TRIGGERED J-K FLOP-FLOP ARE SET TO LOGIC ZERO THE FLOP-FLOP IS TRIGGERED Q=0 AND Q =1 Q=1 AND Q =0 THE OUTPUT OF FLIP-FLOP REMAINS UNCHANGED (page 223) Question No: 29 ( Marks: 1 ) - Please choose one A frequency counter Counts pulse width Counts no. of clock pulses in 1 second (Page 301) Counts high and low range of given clock pulse None of given options rep Question No: 30 ( Marks: 1 ) - Please choose one Stack is an acronym for FIFO memory LIFO memory (Page 429) rep Flash Memory Bust Flash Memory

222 CS302- Digital Logic Design SOLVED SUBJECTIVE FROM FINAL TERM PAPERS Jun 03,2011 Latest Subjective MC PSMD01(IEMS) FINAL TERM EXAMINATION Fall In the highest frequency component in an analog signal is 20 KHz, what is the minimum sample frequency (Marks 2) Answer:- Click here for detail In the highest frequency component in an analog signal is 20 KHz, and minimum sample frequency is 40 KHz. 2. Write down the ABEL symbols that are used for NOT, AND, OR and XOR operations. (Marks 2) Answer:- Page 201 Logic Operation ABEL Symbol NOT! AND & OR # XOR $ 3. Differentiate between Moore machine and Mealy machine. (Marks 2) Answer:- Page 318 The Sequential circuit whose output depends on the current state and the input is known as Mealy Machine. Sequential circuit whose output is determined by the current state only is known as Moore Machine. 4. How many bytes will be there in 16K x 8 memory? (Marks 2) Answer:- Page 395 A 16 K x 8 memory, stores 16K bytes or 16 x 1024 = bytes or bits. 1. How many address bits are required for a 2048-bit memory organized as a 256 x 8 memory? (Marks 3) 2. Explain Rotate Right Operation of shift register with the help of Diagram. (Marks 3) Answer:- Page 354 The serial output of the register is connected to the serial input of the register. By applying clock pulses data is shifted right. The data shifted out of the serial out pin at the right hand side is re-circulated back into the shift register input at the left hand side. Thus the data is rotated right within the register.

223 3. Difference between State Assignment and State Reduction process. (Marks 3) Answer:- (Page 332 & 335) 1. In state Reduction A state diagram show the sequence of current and next states through which the state machine sequences while in State Assignment Each state in a sequential circuit is identified by a unique combination of binary bits. 2. In state Reduction the transition from a current state to the next state is determined by current state and the inputs while in State Assignment the states can be selected to allow minimum bit changes when changing from one state to the other. 3. State Assignment results in simpler combinational circuits that determine the next state while Reduction in the number of state results in fewer flip-flops and a simpler circuit. 4. Explain Full-Adder Sum and Carry out Boolean Expression. (Marks 3) Answer:- (Page 135) Full-Adder Sum & Carry Out Boolean Expressions The Sum and Carry Out expressions of the Full-Adder can be determined from the function table. The Full-Adder Sum and Carry Out outputs are defined by the expressions Sum = ABC + ABC + ABC + ABC Sum = A(BC + BC) + A(BC + BC) Sum = A(B C) + A(B C) Sum = A B C CarryOut = ABC + ABC + ABC + ABC CarryOut = C(AB + AB) + AB(C + C) CarryOut = C(A B) + AB 1. Explain Latches in your own words. (Marks 5) Answer:- (Page 218) A latch is a temporary storage device that has two stable states. A latch output can change from one state to the other by applying appropriate inputs. A latch normally has two inputs, the binary input combinations at the latch input allows the latch to change its state. A latch has two outputs Q and its complement Q(bar). The latch is said to be in logic high state when Q=1 and Q(bar)=0 and it is in the logic low state when Q=0 and Q(bar)=1. When the latch is set to a certain state it retains its state unless the inputs are changed to set the latch to a new state. Thus a latch is a memory element which is able to retain the information stored in it.

224 2. Differentiate between synchronous and asynchronous memory. (Marks 5) Answer:- (Page 406) In the Asynchronous memory the various input signals are asynchronous and are not tied to the clock, whereas in the Synchronous memory all the inputs are synchronized with respect to the clock and are latched into their various registers on an active clock pulse edge. 4. Draw state diagram of Moore machine. (Marks 5) Answer:- (Page 338) FINAL TERM EXAMINATION Spring 2011 Question No: ( Marks: 2 ) Write down at least two applications of a shiftregister. Answer:- (Page 356) The two applications of the shift registers are 1. Serial to Parallel converter 2. Keyboard encoder Question No: ( Marks: 2 ) Explain memory expansion process. Answer:- (Page 430) Computer and Digital systems have the capability to allow RAM memory to be expanded as the needed arises by inserting extra memory in dedicated memory sockets on the computer motherboard.

225 Question No: ( Marks: 2 ) Draw the NOR based S-R Latch Answer:- (Page 220) Question No: ( Marks: 3 ) Explain Rotate Left Right Operation with the help of diagram. Answer:- (Page 354) Question No: ( Marks: 3 ) You are given the block diagram of 74HC190 integrated circuit up/down counter, explain the function of labeled inputs/outputs. Answer:-(Page 295)

226 1. Active-low CTEN counter enable input 2. D/U the count down/up input. When the input is set to logic 1, the counter counts down and when the input is set to logic 0, the counter counts up 3. The MAX/MIN output that is set to high when the terminal count 1001 is reached when counting up or when the terminal count 0000 is reached when counting down. The MAX/MIN output is logic high for one complete cycle when a terminal count is reached. Question No: ( Marks: 5 ) Explain Memory Select or Enable Signals Answer:- (Page 397) In a computer system there are more than one memory chips to store program information. At any particular instant a read or write operation is carried out on a single addressable location. The unique location can only be accessed in one of the several memory chips, thus a single memory chip has to be selected before a read or write operation can be carried out. All memory chips have a chip enable or chip select signal which has to be activated before the memory can be accessed. Question No: ( Marks: 5 ) Explain the implementation of First In First Out (FIFO) Memory by using RAM. Answer:- (Page 427) Shift register based FIFO memory is used in digital systems designed for specific applications where small sized buffers are used to allow transfer of data between two devices operating at different data rates. Such digital systems either have no RAM or very small RAM for storing variables. Computers implement FIFO memory by reserving a part of their RAM memory for use as buffers. The Keyboard buffer for example is implemented by reserving a part of the RAM. When RAM is used as FIFO memory, two registers are used to point to the FIFO Buffer Out and Buffer In respectively. The two registers hold the addresses of the locations of the Buffer Out and Buffer In respectively, which are updated as new data is written into the buffer and previous data is read out from the FIFO buffer. Implementation of the FIFO buffer in RAM is usually takes the form of a circular buffer. Question No: ( Marks: 5 ) Explain application of demultiplexer Answer:- (Page 178) Demultiplexer is used to connect a single source to multiple destinations. One use of the Demultiplexer is at the output of the ALU circuit. The output of the ALU has to be stored in one of the multiple registers or storage units. The Data input of the Demultiplexer is connected to the output of the ALU. Each output of the Demultiplexer is connected to each of the multiple registers. By selecting the appropriate output data from the ALU is routed to the appropriate register for storage. The second use of the Demultiplexer is the reconstruction of Parallel Data from the incoming serial data stream. Serial data arrives at the Data input of the Demultiplexer at fixed time intervals. A counter attached to the Select inputs of the Demultiplexer routes the incoming serial bits to successive outputs where each bit is stored. When all the bits have been stored, data can be read out in parallel.

227 FINAL TERM EXAMINATION Spring 2011 Question No: 27 ( Marks: 2 ) 1: Explain the erase operation in context of Flash Memory. Answer:- (Page 421) During the erase operation charge is removed from the memory cell. A sufficiently large positive voltage is applied at the source with respect to the control gate. The voltage applied across the control gate and source is opposite to the voltage applied during programming. If charges are present on the gate, the positive voltage supply at the source attracts the electrons depleting the gate. A FLASH memory is erased prior to programming. 2: How can a serial in/parallel out register be used as a serial in/serial out register? 3: Explain the next-state table with the help of a table for any sequential circuit? Answer:- (Page 306) Once the state diagram of the sequential circuit is defined, a Next-State Table is derived which lists each present state and the corresponding next state. The next state is the state to which the sequential circuit switches when a clock transition occurs. Present State Next State Q2 Q1 Q0 Q2 Q1 Q : What is meant by Non-Monotonicity of Digital to Analog converter? Answer:- (Page 460) if the D/A converter outputs a lower voltage than its preceding output voltage the converter is said to exhibit non-monotonic behavior. 5: Two state assignments are given in the table below. Identify which state assignment is best and why? States State assignment 1 State assignment 2 A B C D 10 11

228 6: Write down at least two functions of a register. Answer:- (Page 306) Technically, a register performs two basic functions. It stores data and it moves or shifts data. The shifting of data involves shifting of bits from one flip-flop to the other within the register or moving data in and out of the register. The shift operation of the binary data is carried out by applying clock signals. Several different kinds of shift operations can be identified. 7: You are given the Next-state table of a Moore machine, using this information draw the state diagram of the machine. Present State Next State Q 2 Q 1 Q 0 Q 2 Q 1 Q Answer:-(Page 338) FINAL TERM EXAMINATION Spring 2011 QNo.1 Define the term Variable in context of Boolean algebra. Answer:- (Page 71) A variable is a symbol usually an uppercase letter used to represent a logical quantity. A variable can have a 0 or 1 value.

229 Q No.2 A general sequential circuit consists of a combinational circuit and memory elements. How this Memory element is implemented. Answer:- (Page 318) A general Sequential circuit consists of a combinational circuit and a memory element. The memory element is made of a set of n flip-flops all connected to a a common clock. The n flip flops store 2n states. The flip-flops change their current state to the next state on each clock transition. The next state is determined by the current state and the external input. The output of the State Machine is determined by the current state and external input. The inputs to the memory which allow the memory to change its state on a clock transition are known as excitation inputs or excitation variables. Q No.3 what is meant by Monotonicity of Digital to Analog converter? Answer:- (Page 460) The output of the D/A converter should give an increasing analogue voltage output when the binary input is varied between its minimum and maximum values. Q No.4 Explain Programmable Logic Devices? Answer:-(Page 179) Programmable Logic Devices are used in many applications to replace the Logic gates and MSI chips. PLDs save circuit space and reduce and save the cost of components in a Digital Circuit. PLDS consists of Arrays of AND gates and OR gates that can be programmed to perform specific functions. Q No.5 How many clock pulses are required to enter a byte of data serially into an 8-bit shift register? 2 Answer:- 8 clock pulses are required to enter a byte of data serially into an 8- bit shift register Q No. 6 How can calculate the frequency of an unknown signal? Answer:-(Page 301) The frequency of the unknown signal can be calculated by counting the number of clock pulses of the unknown signal and dividing the count number by the time interval in which the clock pulses are counted, Q No. 7 Write the drawbacks of 16-bit ALU without look-ahead carry circuit? Q No. 8 How many address bit are required for a 2048-bit memory organized as a 256*8 memory? Q No. 9 Differentiates between Memory capacity and Memory Density? Answer:- (Page 395) Each memory array has a maximum capacity to store information in the form of bits. Memory density on the other hand specifies the number of bits stored per unit area. More the number of bits stored in a unit area more dense the memory, that is, more bits are stored in less space. Q No. 10. Explain Memory Select or Enable signal? Answer:- (Page 397) In a computer system there are more than one memory chips to store program information. At any particular instant a read or write operation is carried out on a single addressable location. The unique location can only be accessed in one of the several memory chips, thus a single memory chip has to be selected before a read or write operation can be carried out. All memory chips have a chip enable or chip select signal which has to be activated before the memory can be accessed.

230 Q No 11. Explain state Assignment Process. Answer:-(Page 335) Each state in a sequential circuit is identified by a unique combination of binary bits. Unless the output of the sequential is directly taken form the flip-flop outputs such as counters, the states can be selected to allow minimum bit changes when changing from one state to the other. Keeping the bits changes to minimum when changing from one state to the next, results in simpler combinational circuits that determine the next state. Q No 12. Briefly Explain Next-state table with the help of any sequential circuit.5 Answer:- Repeated FINAL TERM EXAMINATION Spring In the highest frequency component in an analog signal is 20 KHz, what is the minimum sample frequency Answer:- Repeated 2. How many bytes will be there in 16K x 8 memory? Answer:- Repeated 3. Convert the hexadecimal number 7AB1 into binary numbers. Write down all the steps. Answer:- (Page 27) Replacing each Hexadecimal digit by its 4-bit binary equivalent 7= 0111, A= 1010, B=1011, 1= 0001 So, 7AB1 = Explain grouping of cells in k-map. 3 Answer:- (Page 90) Groups are formed on the basis of 1s (Minterms) or 0s (maxterms). A group is selected to have maximum number of cells of Minterms or Maxterms, keeping in view that the size of the group should be a power of 2. The idea is to form minimal number of largest groups that uniquely cover all the cells, thereby ensuring that all minterms or maxterms are included. 5. Provide some of guidelines for selection of state assignment. 3 Answer:-(Page 337) Generally, the selection of State Assignment is based on the following guidelines. Choose an initial coded state into which the state machine (sequential circuit) can easily be forced to reset (000 or 111) Minimize the State Variables that change on each transition Maximize the number of state variables that don t change in a group of related states If there are unused states, then choose the best state variable combinations to achieve the first three goals.

231 6. Discuss at least one difference in Johnson and ring Counter 3 Answer:-(Page 355) The Ring Counter is similar to the Johnson counter, except that the Q output of the last flip-flop of the shift register is connected to the data input of the first flip-flop of the shift register. 7. Three types of error while converting Analogue signal into digital. 3 Answer:-(Page 354) 1. Missing Code 2. Incorrect Code 3. Offset Error 8. Explain memory read operation with help of example 5 Answer:- (page 397) Memory Read operation is carried out by first selecting the memory chip by activating the Memory Select signal. The Read signal is asserted to configure the memory circuitry for reading data from the memory. An address (100) is applied on the Address Lines. The internal address decoder of the memory decodes the address and selects one unique row from which data is read. Figure The address of the location in the memory from which data is to be read is supplied by the microprocessor. The microprocessor stores the address in its address buffer. The data read from the memory is stored in a data buffer inside the microprocessor. In the diagram shown, a microprocessor places an address 100 on its external address bus connected to the address lines of the memory. The internal address decoder of the memory decodes the address 100 and activates a row select line which selects the row location 4. The data ( ) at the location is read from the memory and placed on the data bus where it is latched by the microprocessor and stored in its data buffer. 9. Explain flesh analogue to digital converter 5 Answer:- (Page 447) The Flash A/D converter is based on a resistor potential divider, where multiple resistors of identical value form a voltage divider. A reference voltage is applied at one end of the potential divider which divides the voltage equally across all the resistors. The input analogue voltage is applied at the non-inverting inputs of a set of Op- Amp based comparators. The inverting input of each comparator is connected to the resistive voltage divider which provides reference voltages for all the comparators. If the input voltage is larger than the reference voltage the output of the comparator is logic high otherwise it is logic low. The outputs of all the comparators are connected to the input of a priority encoder which converts the comparator outputs to a binary coded equivalent value.

232 10. Briefly explain address multiplexing in DRAM. 5 Answer:- (Page 410) DRAM chips use address multiplexing to reduce the number of address lines by half. The address required to select a memory location is split into row and column addresses. To access a DRAM location for reading or writing of information the row address is first applied at the address lines. The row address is latched by the Row Address Latch of the DRAM memory chip. The column address is applied next at the same address lines. The column address is latched by the Column Address Latch. Two signals RAS and CAS are used as strobe signals to control the Row Address and Column Address latches respectively. The external address lines are multiplexed as the same set of address lines are used to apply the row address and the column address at different time instances. The outputs of the Row Address Latch and the Column Address Latch are connected to the Row and Column Decoders which select a single row and column line selecting the storage cell to be accessed. FINAL TERM EXAMINATION Spring 2011 Explain READ Write signal used for memory. 03 Answer:- (Page 396) Read/Write signals are required to configure the memory for read and write operation. Memory chips have a single Read/Write signal. When the signal is set to high it allows data to be read from the memory. When the signal is set to low data is written into the memory. Some memory chips have two separate Read and Write signals. The read and write signals are separately asserted to control the Read and Write operation. What is difference between PROM and ROM. 03 Answer:- Click here for detail The difference between a PROM and a ROM (read-only memory) is that a PROM is manufactured as blank memory, whereas a ROM is programmed during the manufacturing process. To write data onto a PROM chip, you need a special device called a PROM programmer or PROM burner. The process of programming a PROM is sometimes called burning the PROM. Making decade counter by cascading two 74HC What is difference between memory capacity and memory density? 05 Answer:- Repeated Describe Flash Analogue to Digital converter. 05 Answer:- Repeated

233 Explain don s care condition. Answer:- (Page 96) Function Tables represent the function by listing all the possible inputs and marking the corresponding outputs with 1s and 0s. Thus a circuit having four inputs can be described by a 4-variable function table having 16 possible input combinations. For each of the 16 possible input conditions the corresponding output bits are marked as 1s and 0s depending upon the minterms or maxterms. It is however, possible that out of the 16 possible input combinations, three input combinations never occur. Since these three input combinations never occur so should their corresponding outputs be marked as 0s or 1s? Since these inputs never care therefore we don t need to worry about the output of these input states. They are considered to be don t care conditions. FINAL TERM EXAMINATION 2011 Question#1 Give advantages of Counters are available in integrated circuits? (Marks 2) Question #2 Successive approximation counter have a fixed consecutive time Is tarha ka qs tha (Marks 2) Question #4 How many states in 8-bit Johnson counter? (Marks 2) Answer:-(Page 354) The sequence of states that are implemented by a n-bit Johnson counter are 2n So, 8 bit Johnson counter has 2*8 = 16 states Question #5 Diff b/w truth table and next state table (Marks 3) Question #6 How hexadecimal number is converted into binary number give one example? (Marks 3) Answer:-(Page 28) Converting from Hexadecimal back to binary is also very simple. Each digit of the Hexadecimal number is replaced by an equivalent binary string of 4-bits. FD13 Hexadecimal Number Replacing each Hexadecimal digit by its 4-bit binary equivalent Question #7 Diff b/w ROM and PROM? (Marks 3) Answer:- Repeat Question #8 How we can implement full adder from two half adder? (Marks 3) Answer:- Repeat

234 Question #9 Make State diagram? Answer:- Repeat Question #10 Explain FRGA? (Marks 5) Answer:- (Page 437) Programmable Logic Devices are based on a programmable AND-OR gate array which are programmed to implement any function in the SOP form. The output of the AND-OR gate array can be directly used as a combinational circuit output. Provision is there to connect the output of the AND-OR gate array to a D-flip-flop for Sequential circuit operation. An FPGA is a more flexible device than PLDs as instead of a single AND-OR gate array, an FPGA device contains multiple logic blocks that can be individually programmed to perform different functions. Each Logic Block is connected to other blocks through row and column interconnects that can be programmed to connect any Logic block to another. Question #11 (Marks 5) Differentiate b/w memory density and memory capacity? Answer:- Repeated FINAL TERM EXAMINATION Spring 2010 Question No: 27 (Mark s: 2) Define quantization process. Answer:- (Page 444) The process of converting the analogue signal into a digital representation (code) is known as quantization Question No: 28 (Marks: 2) Explain the difference between 1-to-4 Demultiplexer and 2-to-4 Binary Decoder? Answer:- (Page 178) The only difference between the two is the addition of the Data Input line, which is used as enable line in the 2-to-4 Decoder circuit figure Assuming the select inputs I1 and I0 are set to 1 and 0 respectively. The O2 output is set to 1 if the Data input is 1 or it is set to 0 if the Data input is 0. Question No: 29 (Marks: 2) A general Sequential circuit consists of a combinational circuit and a memory element. How this memory element is implemented Answer:- Repeated Question No: 30 (Marks: 2) Suppose a 2 bit up-counter, having states A, B, C, D. Write down GOTO statements to show how present states change to next states.

235 Question No: 31 (Marks: 3) Name three Operations that can be performed on FLASH Memory Answer:- (Page 420) FLASH Memory operations are classified into Programming Operation Read Operation Erase Operation Question No: 32 (Marks: 3) Explain Rotate Right Operation of shift register with the help of diagram. Answer:- Repeated Question No: 33 ( Marks: 3 ) You are given the block diagram of 74HC190 integrated circuit up/down counter, explain the function of labeled inputs/outputs. Answer:- Repeated Question No: 34 ( Marks: 5 ) Draw the state diagram of 3-bit up-down counter, use an external input X, when X sets to logic 1, the counter counts downwards, otherwise upward. Question No: 35 (Marks: 5) Differentiate between synchronous and asynchronous RAM. Answer:- (Page 406) Synchronous RAM is very similar to the Asynchronous RAM, in terms of the memory array, the address decoders, read/write and enable inputs. In the Asynchronous memory the various input signals are asynchronous and are not tied to the clock, whereas in the Synchronous memory all the inputs are synchronized with respect to the clock and are latched into their various registers on an active clock pulse edge. Question No: 36 ( Marks: 5 ) Explain Memory Select or Enable Signals Answer:- Repeated

236 FINAL TERM EXAMINATION Spring 2010 Question No: 27 ( Marks: 2 ) Draw the Truth-Table of NOR based S-R Latch Answer:- (Page 222) Input Output S R Q t Q t invalid Table 22.3 Truth-Table of NOR based S-R Latch Question No: 28 ( Marks: 2 ) Two state assignments are given in the table below. Identify which state assignment is best and why? States State Assignment 1 State Assignment 1 A B C D Question No: 29 ( Marks: 2 ) Write down at least two functions of a register. Answer:- Repeat Question No: 30 ( Marks: 2 ) Define quantization process. Answer:- Repeat Question No: 31 ( Marks: 3 ) How can we calculate the frequency of an unknown signal? Answer:- Repeat Question No: 32 ( Marks: 3 )

237 Given the following statement used in PLD programming: Y PIN 23 ISTYPE com ; Explain what does this statement mean? Answer:- (Page 360) The statement describes Y available at output pins 23. The Y variable is a Combinational output available directly from the AND-OR gate array output. The active-low or active-high output of the Registered Mode can also be specified in the declaration statement Question No: 33 ( Marks: 3 ) Explain dynamic RAM in your own words. Answer:- Click here for detail Dynamic random-access memory (DRAM) is a type of random-access memory that stores each bit of data in a separate capacitor within an integrated circuit. The capacitor can be either charged or discharged; these two states are taken to represent the two values of a bit, conventionally called 0 and 1. Since capacitors leak charge, the information eventually fades unless the capacitor charge is refreshed periodically. Because of this refresh requirement, it is a dynamic memory as opposed to SRAM and other static memory. Question No: 34 ( Marks: 5 ) You are given the Next-state table of a Moore machine, using this information draw the state diagram of the machine. Answer:- repeat Present State Next State Q 2 Q 1 Q 0 Q 2 Q 1 Q Question No: 35 ( Marks: 5 ) Explain Memory Select or Enable Signals Answer:- repeat Question No: 36 ( Marks: 5 ) Performance characteristics of D/A converters are determined by five parameters. Name them. Answer:- (Page 460) Performances characteristics of D/A converters are determined by five parameters are: 1. Resolution 2. Linearity 3. Monotonicity 4. Setting time 5. Accuracy FINAL TERM EXAMINATION

238 Spring 2010 Question No: 27 (Marks: 2) Explain the erase operation in context of Flash Memory. Answer:- repeat Question No: 28 (Marks: 2) Explain the difference between 1-to-4 Demultiplexer and 2-to-4 Binary Decoder? Answer:- repeat Question No: 29 (Marks: 2) Some of the counters (e.g. 74HC163) are called pre-set counters. why? Answer:- Click here for detail 74HC163) are called pre-set counters because A counter set in advance to stop or produce output once a specific count has been reached. Question No: 30 (Marks: 2) How many bytes will be there in 32 K x 8 memory? Answer:- (Page 395) A 32 K x 4 memory stores 32K nibbles or 32 x 1024 = nibbles Question No: 31 (Marks: 3) Differentiate between truth table and next-state table Question No: 32 (Marks: 3) Name the three types of errors Analogue to Digital converters exhibit during their conversion operation. Answer:- repeat Question No: 33 (Marks: 3) How can a serial in/parallel out register be used as a serial in/serial out register? Question No: 34 (Marks: 5) Explain the implementation of First In First out (FIFO) Memory by using RAM. Answer:- repeat Question No: 35 (Marks: 5) Explain memory read operation with the help of an example Answer:- repeat Question No: 36 (Marks: 5) Explain the next-state table with the help of a table for any sequential circuit Answer:- repeat

239 CS302- Digital Logic Design LATEST SOLVED MCQS FROM FINAL TERM PAPERS Latest Mcqs MC PSMD01(IEMS) FINALTERM EXAMINATION Spring 2011 Question No: 1 ( Marks: 1 ) - Please choose one A 8-bit serial in / parallel out shift register contains the value 8, clock signal(s) will be required to shift the value completely out of the register (Page 356) Question No: 2 ( Marks: 1 ) - Please choose one In a sequential circuit the next state is determined by and State variable, current state Current state, flip-flop output Current state and external input (Page 318) Input and clock signal applied Question No: 3 ( Marks: 1 ) - Please choose one The divide-by-60 counter in digital clock is implemented by using two cascading counters: Mod-6, Mod-10 (Page 299) Mod-50, Mod-10 Mod-10, Mod-50 Mod-50, Mod-6 Question No: 4 ( Marks: 1 ) - Please choose one In NOR gate based S-R latch if both S and R inputs are set to logic 0, the previous output state is maintained. True (Page 221) False

240 Question No: 5 ( Marks: 1 ) - Please choose one The minimum time for which the input signal has to be maintained at the input of flip-flop is called of the flip-flop. Set-up time Hold time (Page 242) Pulse Interval time Pulse Stability time (PST) Question No: 6 ( Marks: 1 ) - Please choose one 74HC163 has two enable input pins which are and ENP, ENT (Page 285) ENI, ENC ENP, ENC ENT, ENI Question No: 7 ( Marks: 1 ) - Please choose one is said to occur when multiple internal variables change due to change in one input variable Clock Skew Race condition (Page 267) Hold delay Hold and Wait Question No: 8 ( Marks: 1 ) - Please choose one The input overrides the input Asynchronous, synchronous (Page 369) Synchronous, asynchronous Preset input (PRE), Clear input (CLR) Clear input (CLR), Preset input (PRE) Question No: 9 ( Marks: 1 ) - Please choose one A decade counter is. Mod-3 counter Mod-5 counter Mod-8 counter Mod-10 counter (Page 274) Question No: 10 ( Marks: 1 ) - Please choose one In asynchronous transmission when the transmission line is idle, It is set to logic low It is set to logic high (Page 356) Remains in previous state State of transmission line is not used to start transmission

241 Question No: 11 ( Marks: 1 ) A Nibble consists of bits - Please choose one 2 4 (Page 394) 8 16 Question No: 12 ( Marks: 1 ) - Please choose one The output of this circuit is always. 1 0 A Click here for detail Question No: 13 ( Marks: 1 ) - Please choose one Excess-8 code assigns to (Page 34) Question No: 14 ( Marks: 1 ) - Please choose one The voltage gain of the Inverting Amplifier is given by the relation Vout / Vin = - Rf / Ri (Page 446) Vout / Rf = - Vin / Ri Rf / Vin = - Ri / Vout Rf / Vin = Ri / Vout Question No: 15 ( Marks: 1 ) LUT is acronym for - Please choose one Look Up Table (Page 439) Local User Terminal Least Upper Time Period None of given options

242 Question No: 16 ( Marks: 1 ) - Please choose one The three fundamental gates are AND, NAND, XOR OR, AND, NAND NOT, NOR, XOR NOT, OR, AND (Page 40) Question No: 17 ( Marks: 1 ) - Please choose one The total amount of memory that is supported by any digital system depends upon The organization of memory The structure of memory The size of decoding unit The size of the address bus of the microprocessor (Page 430) Question No: 18 ( Marks: 1 ) - Please choose one Stack is an acronym for FIFO memory LIFO memory (Page 429) Flash Memory Bust Flash Memory Question No: 19 ( Marks: 1 ) - Please choose one Addition of two octal numbers 36 and 71 results in Question No: 20 ( Marks: 1 ) - Please choose one is one of the examples of synchronous inputs. J-K input (Page 235) EN input Preset input (PRE) Clear Input (CLR) Question No: 21 ( Marks: 1 ) - Please choose one occurs when the same clock signal arrives at different times at different clock inputs due to propagation delay. Race condition Clock Skew (Page 226) Ripple Effect None of given options

243 Question No: 22 ( Marks: 1 ) - Please choose one Consider an up/down counter that counts between 0 and 15, if external input(x) is 0 the counter counts upward (0000 to 1111) and if external input (X) is 1 the counter counts downward (1111 to 0000), now suppose that the present state is 1100 and X=1, the next state of the counter will be (not sure) Question No: 23 ( Marks: 1 ) - Please choose one In a state diagram, the transition from a current state to the next state is determined by Current state and the inputs (Page 332) Current state and outputs Previous state and inputs Previous state and outputs Question No: 24 ( Marks: 1 ) - Please choose one is used to simplify the circuit that determines the next state. State diagram Next state table State reduction State assignment (Page 335) Question No: 25 ( Marks: 1 ) - Please choose one A 8-bit serial in / parallel out shift register contains the value 8, clock signal(s) will be required to shift the value completely out of the register (Page 356) rep Question No: 26 ( Marks: 1 ) - Please choose one Assume that a 4-bit serial in/serial out shift register is initially clear. We wish to store the nibble What will be the 4-bit pattern after the second clock pulse? (Right-most bit first.) Click here for detail 1111

244 Question No: 27 ( Marks: 1 ) - Please choose one LUT is acronym for Look Up Table (Page 439) rep Local User Terminal Least Upper Time Period None of given options. Question No: 28 ( Marks: 1 ) - Please choose one The diagram given below represents Demorgans law Associative law Product of sum form Sum of product form (Page 78) Question No: 29 ( Marks: 1 ) - Please choose one The operation of J-K flip-flop is similar to that of the SR flip-flop except that the J-K flip-flop Doesn t have an invalid state (Page 232) Sets to clear when both J = 0 and K = 0 It does not show transition on change in pulse It does not accept asynchronous inputs Question No: 30 ( Marks: 1 ) - Please choose one A multiplexer with a register circuit converts Serial data to parallel Parallel data to serial (Page 356) rep Serial data to serial Parallel data to parallel Question No: 31 ( Marks: 1 ) - Please choose one A GAL is essentially a. Non-reprogrammable PAL PAL that is programmed only by the manufacturer Very large PAL Reprogrammable PAL (Page 183)

245 Question No: 32 ( Marks: 1 ) - Please choose one in, all the columns in the same row are either read or written. Sequential Access MOS Access FAST Mode Page Access (Page 413) None of given options Question No: 33 ( Marks: 1 ) - Please choose one In order to synchronize two devices that consume and produce data at different rates, we can use Read Only Memory Fist In First Out Memory (Page 425) Flash Memory Fast Page Access Mode Memory Question No: 34 ( Marks: 1 ) - Please choose one A positive edge-triggered flip-flop changes its state when Low-to-high transition of clock (Page 228) High-to-low transition of clock Enable input (EN) is set Preset input (PRE) is set FINALTERM EXAMINATION Spring 2010 Question No: 1 ( Marks: 1 ) - Please choose one A 8-bit serial in / parallel out shift register contains the value 8, clock signal(s) will be required to shift the value completely out of the register (Page 356) rep Question No: 2 ( Marks: 1 ) - Please choose one A frequency counter Counts pulse width Counts no. of clock pulses in 1 second (Page 301) Counts high and low range of given clock pulse None of given options

246 Question No: 3 ( Marks: 1 ) - Please choose one In a sequential circuit the next state is determined by and State variable, current state Current state, flip-flop output Current state and external input Input and clock signal applied (Page 305) Question No: 4 ( Marks: 1 ) - Please choose one The divide-by-60 counter in digital clock is implemented by using two cascading counters: Mod-6, Mod-10 Mod-50, Mod-10 Mod-10, Mod-50 Mod-50, Mod-6 (Page 229) rep Question No: 5 ( Marks: 1 ) - Please choose one In NOR gate based S-R latch if both S and R inputs are set to logic 0, the previous output state is maintained. True (Page 221) rep False Question No: 6 ( Marks: 1 ) - Please choose one Flip flops are also called Bi-stable dualvibrators Bi-stable transformer Bi-stable multivibrators (Page 228) Bi-stable singlevibrators Question No: 7 ( Marks: 1 ) - Please choose one The minimum time for which the input signal has to be maintained at the input of flip-flop is called of the flip-flop. Set-up time Hold time (Page 242) rep Pulse Interval time Pulse Stability time (PST) Question No: 8 ( Marks: 1 ) - Please choose one 74HC163 has two enable input pins which are and ENP, ENT (Page 285) ENI, ENC ENP, ENC ENT, ENI

247 Question No: 9 ( Marks: 1 ) - Please choose one is said to occur when multiple internal variables change due to change in one input variable Clock Skew Race condition (Page 267) Hold delay Hold and Wait Question No: 10 ( Marks: 1 ) - Please choose one Given the state diagram of an up/down counter, we can find The next state of a given present state (Page 371) The previous state of a given present state Both the next and previous states of a given state The state diagram shows only the inputs/outputs of a given states Question No: 11 ( Marks: 1 ) - Please choose one The input overrides the input Asynchronous, synchronous (Page 369) rep Synchronous, asynchronous Preset input (PRE), Clear input (CLR) Clear input (CLR), Preset input (PRE) Question No: 12 ( Marks: 1 ) - Please choose one A logic circuit with an output consists of. two AND gates, two OR gates, two inverters three AND gates, two OR gates, one inverter two AND gates, one OR gate, two inverters (Lecture 8) two AND gates, one OR gate Question No: 13 ( Marks: 1 ) - Please choose one A decade counter is. Mod-3 counter Mod-5 counter Mod-8 counter Mod-10 counter (Page 274)

248 Question No: 14 ( Marks: 1 ) - Please choose one In asynchronous transmission when the transmission line is idle, It is set to logic low It is set to logic high (Page 356) rep Remains in previous state State of transmission line is not used to start transmission Question No: 15 ( Marks: 1 ) - Please choose one A Nibble consists of bits 2 4 (Page 394) 8 16 Question No: 16 ( Marks: 1 ) - Please choose one The output of this circuit is always. 1 0 A Click here for detail rep Question No: 17 ( Marks: 1 ) - Please choose one Excess-8 code assigns to (Page 34) rep Question No: 18 ( Marks: 1 ) - Please choose one The voltage gain of the Inverting Amplifier is given by the relation V out / V in = - R f / R i (Page 446) V out / R f = - V in / R i R f / V in = - R i / V out R f / V in = R i / V out

249 Question No: 19 ( Marks: 1 ) - Please choose one LUT is acronym for Look Up Table (Page 439) Local User Terminal Least Upper Time Period None of given options rep Question No: 20 ( Marks: 1 ) - Please choose one DRAM stands for Dynamic RAM (Page 407) Data RAM Demoduler RAM None of given options Question No: 21 ( Marks: 1 ) - Please choose one The three fundamental gates are AND, NAND, XOR OR, AND, NAND NOT, NOR, XOR NOT, OR, AND (Page 40) Question No: 22 ( Marks: 1 ) - Please choose one Which of the following statement is true regarding above block diagram? Triggering takes place on the negative-going edge of the CLK pulse Triggering takes place on the positive-going edge of the CLK pulse Triggering can take place anytime during the HIGH level of the CLK waveform Triggering can take place anytime during the LOW level of the CLK waveform Question No: 23 ( Marks: 1 ) - Please choose one The total amount of memory that is supported by any digital system depends upon The organization of memory The structure of memory The size of decoding unit The size of the address bus of the microprocessor (Page 430) rep

250 Question No: 24 ( Marks: 1 ) - Please choose one The expression F=A+B+C describes the operation of three bits Gate. OR (Page 42) AND NOT NAND Question No: 25 ( Marks: 1 ) - Please choose one Stack is an acronym for FIFO memory LIFO memory (Page 429) rep Flash Memory Bust Flash Memory Question No: 26 ( Marks: 1 ) - Please choose one Addition of two octal numbers 36 and 71 results in FINALTERM EXAMINATION Spring 2010 Question No: 1 ( Marks: 1 ) - Please choose one The ANSI/IEEE Standard 754 defines a Single-Precision Floating Point format for binary numbers. 8-bit 16-bit 32-bit (Page 25) 64-bit Question No: 2 ( Marks: 1 ) - Please choose one The decimal 17 in BCD will be represented as (According to rule) 11110

251 Question No: 3 ( Marks: 1 ) - Please choose one The basic building block for a logical circuit is A Flip-Flop A Logical Gate (Page 7) An Adder None of given options Question No: 4 ( Marks: 1 ) - Please choose one The output of the expression F=A.B.C will be Logic when A=1, B=0, C=1. Undefined One Zero (According to rule) No Output as input is invalid. Question No: 5 ( Marks: 1 ) - Please choose one is invalid number of cells in a single group formed by the adjacent cells in K-map (According to rule 2^n ) 16 Question No: 6 ( Marks: 1 ) - Please choose one The PROM consists of a fixed non-programmable Gate array configured as a decoder. AND (Page 182) OR NOT XOR Question No: 7 ( Marks: 1 ) - Please choose one is one of the examples of synchronous inputs. J-K input (Page 235) rep EN input Preset input (PRE) Clear Input (CLR) Question No: 8 ( Marks: 1 ) - Please choose one is one of the examples of asynchronous inputs. J-K input S-R input D input Clear Input (CLR) (Page 235)

252 Question No: 9 ( Marks: 1 ) - Please choose one The input overrides the input Asynchronous, synchronous (Page 369) rep Synchronous, asynchronous Preset input (PRE), Clear input (CLR) Clear input (CLR), Preset input (PRE) Question No: 10 ( Marks: 1 ) - Please choose one occurs when the same clock signal arrives at different times at different clock inputs due to propagation delay. Race condition Clock Skew (Page 226) rep Ripple Effect None of given options Question No: 11 ( Marks: 1 ) - Please choose one Consider an up/down counter that counts between 0 and 15, if external input(x) is 0 the counter counts upward (0000 to 1111) and if external input (X) is 1 the counter counts downward (1111 to 0000), now suppose that the present state is 1100 and X=1, the next state of the counter will be (not sure) Question No: 12 ( Marks: 1 ) - Please choose one In a state diagram, the transition from a current state to the next state is determined by Current state and the inputs (Page 232) Current state and outputs Previous state and inputs Previous state and outputs Question No: 13 ( Marks: 1 ) - Please choose one is used to minimize the possible no. of states of a circuit. State assignment (Page 341) State reduction Next state table State diagram

253 Question No: 14 ( Marks: 1 ) - Please choose one is used to simplify the circuit that determines the next state. State diagram Next state table State reduction State assignment (Page 335) Question No: 15 ( Marks: 1 ) - Please choose one The best state assignment tends to. Maximizes the number of state variables that don t change in a group of related states (Page 337) Minimizes the number of state variables that don t change in a group of related states Minimize the equivalent states None of given options Question No: 16 ( Marks: 1 ) - Please choose one The output of this circuit is always. 1 0 A Click here for detail rep Question No: 17 ( Marks: 1 ) - Please choose one A 8-bit serial in / parallel out shift register contains the value 8, clock signal(s) will be required to shift the value completely out of the register (Page 356) rep Question No: 18 ( Marks: 1 ) - Please choose one 5-bit Johnson counter sequences through states 7 10 (Page 354) 32 25

254 Question No: 19 ( Marks: 1 ) - Please choose one Assume that a 4-bit serial in/serial out shift register is initially clear. We wish to store the nibble What will be the 4-bit pattern after the second clock pulse? (Right-most bit first.) Click here for detail 1111 rep Question No: 20 ( Marks: 1 ) - Please choose one The address from which the data is read, is provided by Depends on circuitry None of given options RAM Microprocessor (Page 397) Question No: 21 ( Marks: 1 ) - Please choose one FIFO is an acronym for First In, First Out (Page 424) Fly in, Fly Out Fast in, Fast Out None of given options Question No: 22 ( Marks: 1 ) - Please choose one LUT is acronym for Look Up Table (Page 439) rep Local User Terminal Least Upper Time Period None of given options Question No: 23 ( Marks: 1 ) - Please choose one The voltage gain of the Inverting Amplifier is given by the relation V out / V in = - R f / R i (Page 446) V out / R f = - V in / R i R f / V in = - R i / V out R f / V in = R i / V out

255 Question No: 24 ( Marks: 1 ) - Please choose one of a D/A converter is determined by comparing the actual output of a D/A converter with the expected output. Resolution Accuracy (Page 460) rep Quantization Missing Code Question No: 25 ( Marks: 1 ) - Please choose one Above is the circuit diagram of. Asynchronous up-counter (Page 270) Asynchronous down-counter Synchronous up-counter Synchronous down-counter Question No: 26 ( Marks: 1 ) - Please choose one The sequence of states that are implemented by a n-bit Johnson counter is n+2 (n plus 2) 2n (n multiplied by 2) (Page 354) 2 n (2 raise to power n) n 2 (n raise to power 2) Question No: 1 ( Marks: 1 ) - Please choose one "A + B = B + A" is Demorgan s Law Distributive Law Commutative Law (Page 72) Associative Law FINALTERM EXAMINATION Spring 2010

256 Question No: 2 ( Marks: 1 ) - Please choose one The diagram given below represents Demorgans law Associative law Product of sum form Sum of product form (Page 78) rep Question No: 3 ( Marks: 1 ) - Please choose one Following is standard POS expression True (Lecture 9) False Question No: 4 ( Marks: 1 ) - Please choose one An alternate method of implementing Comparators which allows the Comparators to be easily cascaded without the need for extra logic gates is Using a single comparator Using Iterative Circuit based Comparators (Page 155) Connecting comparators in vertical hierarchy Extra logic gates are always required. Question No: 5 ( Marks: 1 ) Demultiplexer is also called - Please choose one Data selector Data router Data distributor (Page 178) Data encoder Question No: 6 ( Marks: 1 ) - Please choose one The operation of J-K flip-flop is similar to that of the SR flip-flop except that the J-K flip-flop Doesn t have an invalid state (Page 232) rep Sets to clear when both J = 0 and K = 0 It does not show transition on change in pulse It does not accept asynchronous inputs

257 Question No: 7 ( Marks: 1 ) - Please choose one A positive edge-triggered flip-flop changes its state when Low-to-high transition of clock (Page 228) rep High-to-low transition of clock Enable input (EN) is set Preset input (PRE) is set Question No: 8 ( Marks: 1 ) - Please choose one A flip-flop is connected to +5 volts and it draws 5 ma of current during its operation, the power dissipation of the flip-flop is 10 mw 25 mw (Page 242) 64 mw 1024 Question No: 9 ( Marks: 1 ) - Please choose one counters as the name indicates are not triggered simultaneously. Asynchronous (Page 269) Synchronous Positive-Edge triggered Negative-Edge triggered Question No: 10 ( Marks: 1 ) - Please choose one 74HC163 has two enable input pins which are and ENP, ENT (Page 285) rep ENI, ENC ENP, ENC ENT, ENI Question No: 11 ( Marks: 1 ) - Please choose one The divide-by-60 counter in digital clock is implemented by using two cascading counters: Mod-6, Mod-10 (Page 299) Mod-50, Mod-10 Mod-10, Mod-50 Mod-50, Mod-6

258 Question No: 12 ( Marks: 1 ) - Please choose one In a state diagram, the transition from a current state to the next state is determined by Current state and the inputs (Page 332) Current state and outputs Previous state and inputs Previous state and outputs Question No: 13 ( Marks: 1 ) - Please choose one A synchronous decade counter will have flip-flops 3 4 (Page 281) 7 10 Question No: 14 ( Marks: 1 ) - Please choose one is used to minimize the possible no. of states of a circuit. State assignment (Page 341) rep State reduction Next state table State diagram Question No: 15 ( Marks: 1 ) - Please choose one A multiplexer with a register circuit converts Serial data to parallel Parallel data to serial Serial data to serial Parallel data to parallel (Page 356) rep Question No: 16 ( Marks: 1 ) - Please choose one The alternate solution for a demultiplexer-register combination circuit is Parallel in / Serial out shift register Serial in / Parallel out shift register (Page 356) Parallel in / Parallel out shift register Serial in / Serial Out shift register Question No: 17 ( Marks: 1 ) - Please choose one A GAL is essentially a. Non-reprogrammable PAL PAL that is programmed only by the manufacturer Very large PAL Reprogrammable PAL (Page 183) rep

259 Question No: 18 ( Marks: 1 ) - Please choose one The output of this circuit is always. 1 0 A Click here For detail rep Question No: 20 ( Marks: 1 ) - Please choose one in, all the columns in the same row are either read or written. Sequential Access MOS Access FAST Mode Page Access (Page 413) rep None of given options Question No: 21 ( Marks: 1 ) - Please choose one FIFO is an acronym for First In, First Out (Page 424) rep Fly in, Fly Out Fast in, Fast Out None of given options Question No: 22 ( Marks: 1 ) - Please choose one In order to synchronize two devices that consume and produce data at different rates, we can use Read Only Memory Fist In First Out Memory (Page 425) rep Flash Memory Fast Page Access Mode Memory Question No: 23 ( Marks: 1 ) - Please choose one A frequency counter Counts pulse width Counts no. of clock pulses in 1 second (Page 301) rep Counts high and low range of given clock pulse None of given options

260 Question No: 24 ( Marks: 1 ) - Please choose one The sequence of states that are implemented by a n-bit Johnson counter is n+2 (n plus 2) 2n (n multiplied by 2) (Page 354) rep 2 n (2 raise to power n) n 2 (n raise to power 2) Question No: 25 ( Marks: 1 ) - Please choose one Stack is an acronym for FIFO memory LIFO memory (Page 429) rep Flash Memory Bust Flash Memory Question No: 26 ( Marks: 1 ) - Please choose one The 4-bit 2 s complement representation of +5 is (Page 22) FINALTERM EXAMINATION Spring 2010 Question No: 1 ( Marks: 1 ) The storage cell in SRAM is a flip flop a capacitor (Page 407) a fuse a magnetic domain - Please choose one Question No: 2 ( Marks: 1 ) - Please choose one What is the difference between a D latch and a D flip-flop? The D latch has a clock input. The D flip-flop has an enable input. The D latch is used for faster operation. The D flip-flop has a clock input. Click here for detail

261 Question No: 3 ( Marks: 1 ) - Please choose one For a positive edge-triggered J-K flip-flop with both J and K HIGH, the outputs will if the clock goes HIGH. toggle Click here for detail set reset not change Question No: 4 ( Marks: 1 ) - Please choose one The OR gate performs Boolean. multiplication subtraction division addition (Page 42) Question No: 5 ( Marks: 1 ) - Please choose one If an S-R latch has a 1 on the S input and a 0 on the R input and then the S input goes to 0, the latch will be set (Page 219) reset invalid clear 5. Determine the values of A, B, C, and D that make the sum term A(bar) + B+C(bar)+D equal to zero. A = 1, B = 0, C = 0, D = 0 A = 1, B = 0, C = 1, D = 0 (Lecture 8) A = 0, B = 1, C = 0, D = 0 A = 1, B = 0, C = 1, D = 1 Question No: 6 ( Marks: 1 ) - Please choose one The power dissipation, PD, of a logic gate is the product of the dc supply voltage and the peak current Click here for detail dc supply voltage and the average supply current ac supply voltage and the peak current ac supply voltage and the average supply current Question No: 7 ( Marks: 1 ) - Please choose one A Karnaugh map is similar to a truth table because it presents all the possible values of input variables and the resulting output of each value. True Click here for detail False Question No: 8 ( Marks: 1 ) - Please choose one NOR Gate can be used to perform the operation of AND, OR and NOT Gate True (Page 50) False

262 Question No: 9 ( Marks: 1 ) - Please choose one Using multiplexer as parallel to serial converter requires connected to the multiplexer A parallel to serial converter circuit (Page 244) A counter circuit A BCD to Decimal decoder A 2-to-8 bit decoder Question No: 10 ( Marks: 1 ) - Please choose one The 3-variable Karnaugh Map (K-Map) has cells for min or max terms 4 8 (Page 89) Question No: 11 ( Marks: 1 ) - Please choose one In designing any counter the transition from a current state to the next sate is determined by Current state and inputs (Page 332) Only inputs Only current state current state and outputs Question No: 12 ( Marks: 1 ) - Please choose one Sum term (Max term) is implemented using gates OR (Page 78) AND NOT OR-AND Question No: 13 ( Marks: 1 ) - Please choose one Given the state diagram of an up/down counter, we can find The next state of a given present state (Page 371) rep The previous state of a given present state Both the next and previous states of a given state The state diagram shows only the inputs/outputs of a given states Question No: 14 ( Marks: 1 ) - Please choose one AT T0 THE VALUE STORED IN A 4-BIT LEFT SHIFT WAS 1. WHAT WILL BE THE VALUE OF REGISTER AFTER THREE CLOCK PULSES? (not sure)

263 Question No: 15 ( Marks: 1 ) - Please choose one WHEN BOTH THE INPUTS OF EDGE-TRIGGERED J-K FLOP-FLOP ARE SET TO LOGIC ZERO THE FLOP-FLOP IS TRIGGERED Q=0 AND Q =1 Q=1 AND Q =0 (Page 233) THE OUTPUT OF FLIP-FLOP REMAINS UNCHANGED Question No: 16 ( Marks: 1 ) - Please choose one If S=1 and R=0, then Q(t+1) = for positive edge triggered flip-flop 0 1 (Page 230) Invalid Input is invalid If S=1 and R=1, then Q(t+1) = for negative edge triggered flip-flop 0 1 Invalid (Page 233) Input is invalid Question No: 17 ( Marks: 1 ) - Please choose one The minimum time for which the input signal has to be maintained at the input of flip-flop is called of the flip-flop. Set-up time Hold time (Page 242) rep Pulse Interval time Pulse Stability time (PST) Question No: 18 ( Marks: 1 ) - Please choose one We have a digital circuit. Different parts of circuit operate at different clock frequencies (4MHZ, 2MHZ and 1MHZ), but we have a single clock source having a fix clock frequency (4MHZ), we can get help by Using S-R Flop-Flop D-flipflop J-K flip-flop (Page 252) T-Flip-Flop Question No: 19 ( Marks: 1 ) - Please choose one A counter is implemented using three (3) flip-flops, possibly it will have maximum output status (Page 272) 15

264 Question No: 20 ( Marks: 1 ) - Please choose one In Q output of the last flip-flop of the shift register is connected to the data input of the first flip-flop of the shift register. Moore machine Meally machine Johnson counter Ring counter (Page 355) Question No: 21 ( Marks: 1 ) - Please choose one The of a ROM is the time it takes for the data to appear at the Data Output of the ROM chip after an address is applied at the address input lines Write Time Recycle Time Refresh Time Access Time (Page 417) Question No: 22 ( Marks: 1 ) - Please choose one Bi-stable devices remain in either of their states unless the inputs force the device to switch its state Ten Eight Three Two (Page 262) Question No: 23 ( Marks: 1 ) - Please choose one occurs when the same clock signal arrives at different times at different clock inputs due to propagation delay. Race condition Clock Skew (Page 226) rep Ripple Effect None of given options Question No: 24 ( Marks: 1 ) - Please choose one The alternate solution for a multiplexer and a register circuit is Parallel in / Serial out shift register (Page 356) Serial in / Parallel out shift register Parallel in / Parallel out shift register Serial in / Serial Out shift register Question No: 25 ( Marks: 1 ) - Please choose one Stack is an acronym for FIFO memory LIFO memory (Page 429) rep Flash Memory Bust Flash Memory

265 Question No: 26 ( Marks: 1 ) - Please choose one A full-adder has a Cin = 0. What are the sum (<PRIVATE "TYPE=PICT;ALT=sigma"> ) and the carry (Cout) when A = 1 and B = 1? = 0, Cout = 0 = 0, Cout = 1 (Page 135) = 1, Cout = 0 = 1, Cout = 1 Question No: 27 ( Marks: 1 ) - Please choose one THE GLITCHES DUE TO RACE CONDITION CAN BE AVOIDED BY USING A GATED FLIP-FLOPS PULSE TRIGGERED FLIP-FLOPS POSITIVE-EDGE TRIGGERED FLIP-FLOPS NEGATIVE-EDGE TRIGGERED FLIP-FLOPS (Page 267) Question No: 28 ( Marks: 1 ) - Please choose one The design and implementation of synchronous counters start from Truth table k-map state table state diagram (Page 319) Question No: 29 ( Marks: 1 ) - Please choose one THE HOURS COUNTER IS IMPLEMENTED USING ONLY A SINGLE MOD-12 COUNTER IS REQUIRED MOD-10 AND MOD-6 COUNTERS MOD-10 AND MOD-2 COUNTERS A SINGLE DECADE COUNTER AND A FLIP-FLOP (Page 299) Question No: 30 ( Marks: 1 ) - Please choose one Given the state diagram of an up/down counter, we can find The next state of a given present state (Page 371) rep The previous state of a given present state Both the next and previous states of a given state The state diagram shows only the inputs/outputs of a given states Question No: 31 ( Marks: 1 ) - Please choose one LUT is acronym for Look Up Table (Page 439) rep Local User Terminal Least Upper Time Period None of given options

266 Question No: 32 ( Marks: 1 ) - Please choose one of a D/A converter is determined by comparing the actual output of a D/A converter with the expected output. Resolution Accuracy (Page 460) rep Quantization Missing Code Question No: 33 ( Marks: 1 ) - Please choose one is used to simplify the circuit that determines the next state. State diagram Next state table State reduction State assignment (Page 335) rep Question No: 34 ( Marks: 1 ) - Please choose one The high density FLASH memory cell is implemented using 1 floating-gate MOS transistor (Page 419) 2 floating-gate MOS transistors 4 floating-gate MOS transistors 6 floating-gate MOS transistors Question No: 35 ( Marks: 1 ) - Please choose one Q2 :=Q1 OR X OR Q3 The above ABEL expression will be Q2:= Q1 $ X $ Q3 Q2:= Q1 # X # Q3 (Page 210) Q2:= Q1 & X & Q3 Q2:= Q1! X! Q3 Question No: 36 ( Marks: 1 ) - Please choose one Generally, the Power dissipation of devices remains constant throughout their operation. TTL (Page 65) CMOS 3.5 series CMOS 5 Series Power dissipation of all circuits increases with time. Question No: 37 ( Marks: 1 ) - Please choose one When the control line in tri-state buffer is high the buffer operates like a gate AND OR NOT (Page 196) XOR

267 Question No: 38 ( Marks: 1 ) - Please choose one 3.3 v CMOS series is characterized by and as compared to the 5 v CMOS series. Low switching speeds, high power dissipation Fast switching speeds, high power dissipation Fast switching speeds, very low power dissipation (Page 61) Low switching speeds, very low power dissipation Question No: 1 ( Marks: 1 ) - Please choose one The output of an AND gate is one when All of the inputs are one (Page 40) Any of the input is one Any of the input is zero All the inputs are zero Question No: 2 ( Marks: 1 ) - Please choose one The OR Gate performs a Boolean function Addition (Page 42) rep Subtraction Multiplication Division FINALTERM EXAMINATION Fall 2009 Question No: 3 ( Marks: 1 ) - Please choose one A Karnaugh map is similar to a truth table because it presents all the possible values of input variables and the resulting output of each value. True rep False Click here for Detail Question No: 4 ( Marks: 1 ) - Please choose one The binary numbers A = 1100 and B = 1001 are applied to the inputs of a comparator. What are the output levels? A > B = 1, A < B = 0, A < B = 1 A > B = 0, A < B = 1, A = B = 0 A > B = 1, A < B = 0, A = B = 0 (Page 109) A > B = 0, A < B = 1, A = B = 1

268 Question No: 5 ( Marks: 1 ) - Please choose one AND Gate level NOT Gate level OR Gate level The diagram above shows the general implementation of form boolean arbitrary POS (Page 122) SOP Question No: 6 ( Marks: 1 ) - Please choose one The device shown here is most likely a Comparator Multiplexer Click here for detail Demultiplexer Parity generator Question No: 7 ( Marks: 1 ) - Please choose one Demultiplexer converts data to data Parallel data, serial data Serial data, parallel data (Page 356) Encoded data, decoded data All of the given options.

269 Question No: 8 ( Marks: 1 ) - Please choose one Flip flops are also called Bi-stable dualvibrators Bi-stable transformer Bi-stable multivibrators (Page 228) rep Bi-stable singlevibrators Question No: 9 ( Marks: 1 ) - Please choose one If S=1 and R=0, then Q(t+1) = for positive edge triggered flip-flop 0 1 (Page 230) Invalid Input is invalid Question No: 10 ( Marks: 1 ) - Please choose one If S=1 and R=1, then Q(t+1) = for negative edge triggered flip-flop 0 1 Invalid (Page 230) Input is invalid Question No: 11 ( Marks: 1 ) - Please choose one The operation of J-K flip-flop is similar to that of the SR flip-flop except that the J-K flip-flop Doesn t have an invalid state (Page 232) rep Sets to clear when both J = 0 and K = 0 It does not show transition on change in pulse It does not accept asynchronous inputs Question No: 12 ( Marks: 1 ) - Please choose one The minimum time for which the input signal has to be maintained at the input of flip-flop is called of the flip-flop. Set-up time Hold time (Page 242) Pulse Interval time Pulse Stability time (PST) Question No: 13 ( Marks: 1 ) - Please choose one We have a digital circuit. Different parts of circuit operate at different clock frequencies (4MHZ, 2MHZ and 1MHZ), but we have a single clock source having a fix clock frequency (4MHZ), we can get help by Using S-R Flop-Flop D-flipflop J-K flip-flop (Page 252) T-Flip-Flop

270 Question No: 14 ( Marks: 1 ) - Please choose one In asynchronous digital systems all the circuits change their state with respect to a common clock True False (Page 245) Question No: 15 ( Marks: 1 ) - Please choose one A positive edge-triggered flip-flop changes its state when Low-to-high transition of clock (Page 228) rep High-to-low transition of clock Enable input (EN) is set Preset input (PRE) is set Question No: 16 ( Marks: 1 ) - Please choose one A negative edge-triggered flip-flop changes its state when Enable input (EN) is set Preset input (PRE) is set Low-to-high transition of clock High-to-low transition of clock (Page 228) Question No: 17 ( Marks: 1 ) - Please choose one A flip-flop is connected to +5 volts and it draws 5 ma of current during its operation, the power dissipation of the flip-flop is 10 mw 25 mw (Page 242) 64 mw 1024 Question No: 18 ( Marks: 1 ) - Please choose one occurs when the same clock signal arrives at different times at different clock inputs due to propagation delay. Race condition Clock Skew (Page 226) rep Ripple Effect None of given options Question No: 19 ( Marks: 1 ) - Please choose one A counter is implemented using three (3) flip-flops, possibly it will have maximum output status (Page 272) rep 15

271 Question No: 20 ( Marks: 1 ) - Please choose one A divide-by-50 counter divides the input signal to a 1 Hz signal. 10 Hz 50 Hz (Page 298) 100 Hz 500 Hz Question No: 21 ( Marks: 1 ) - Please choose one The design and implementation of synchronous counters start from Truth table k-map state table state diagram (Page 319) Question No: 22 ( Marks: 1 ) - Please choose one A synchronous decade counter will have flip-flops 3 4 (Page 281) rep 7 10 Question No: 23 ( Marks: 1 ) - Please choose one The output of this circuit is always. 1 0 A Click here for Detail rep Question No: 24 ( Marks: 1 ) - Please choose one At T0 the value stored in a 4-bit left shift was 1. What will be the value of register after three clock pulses? (not sure) rep

272 Question No: 25 ( Marks: 1 ) - Please choose one In the Q output of the last flip-flop of the shift register is connected to the data input of the first flipflop. Moore machine Meally machine Johnson counter (Page 354 ) Ring counter Question No: 26 ( Marks: 1 ) - Please choose one In Q output of the last flip-flop of the shift register is connected to the data input of the first flip-flop of the shift register. Moore machine Meally machine Johnson counter Ring counter (Page 355) rep Question No: 27 ( Marks: 1 ) - Please choose one Which is not characteristic of a shift register? Serial in/parallel in (Page 346) Serial in/parallel out Parallel in/serial out Parallel in/parallel out Question No: 28 ( Marks: 1 ) - Please choose one Assume that a 4-bit serial in/serial out shift register is initially clear. We wish to store the nibble What will be the 4-bit pattern after the second clock pulse? (Right-most bit first.) Click here for detail rep Question No: 29 ( Marks: 1 ) - Please choose one The of a ROM is the time it takes for the data to appear at the Data Output of the ROM chip after an address is applied at the address input lines Write Time Recycle Time Refresh Time Access Time (Page 417) rep

273 Question No: 30 ( Marks: 1 ) - Please choose one The sequence of states that are implemented by a n-bit Johnson counter is n+2 (n plus 2) 2n (n multiplied by 2) (Page 354) rep 2 n (2 raise to power n) n 2 (n raise to power 2) FINALTERM EXAMINATION Fall 2009 Question No: 1 ( Marks: 1 ) - Please choose one NOR Gate can be used to perform the operation of AND, OR and NOT Gate FALSE TRUE (Page 250) Question No: 2 ( Marks: 1 ) - Please choose one The output of an XNOR gate is 1 when I) All the inputs are zero II) Any of the inputs is zero III) Any of the inputs is one IV) All the inputs are one I Only IV Only I and IV only II and III only (Page 53) Question No: 3 ( Marks: 1 ) - Please choose one NAND gate is formed by connecting AND Gate and then NOT Gate (Page 45) NOT Gate and then AND Gate AND Gate and then OR Gate OR Gate and then AND Gate Question No: 4 ( Marks: 1 ) - Please choose one Consider A=1,B=0,C=1. A, B and C represent the input of three bit NAND gate the output of the NAND gate will be Zero One (Page 46) Undefined No output as input is invalid

274 Question No: 5 ( Marks: 1 ) - Please choose one The capability that allows the PLDs to be programmed after they have been installed on a circuit board is called Radiation-Erase programming method (REPM) In-System Programming (ISP) (Page 194) In-chip Programming (ICP) Electronically-Erase programming method(eepm) Question No: 6 ( Marks: 1 ) - Please choose one The ABEL symbol for OR operation is! & # $ (Page 201) rep Question No: 7 ( Marks: 1 ) - Please choose one If S=1 and R=1, then Q(t+1) = for negative edge triggered flip-flop 0 1 Invalid (Page 230) rep Input is invalid Question No: 8 ( Marks: 1 ) - Please choose one The operation of J-K flip-flop is similar to that of the SR flip-flop except that the J-K flip-flop Doesn t have an invalid state (Page 232) rep Sets to clear when both J = 0 and K = 0 It does not show transition on change in pulse It does not accept asynchronous inputs Question No: 9 ( Marks: 1 ) - Please choose one For a gated D-Latch if EN=1 and D=1 then Q(t+1) = 0 1 (Page 227) rep Q(t) Invalid Question No: 10 ( Marks: 1 ) - Please choose one In asynchronous digital systems all the circuits change their state with respect to a common clock True False (Page 245) rep

275 Question No: 11 ( Marks: 1 ) - Please choose one A positive edge-triggered flip-flop changes its state when Low-to-high transition of clock (Page 228) rep High-to-low transition of clock Enable input (EN) is set Preset input (PRE) is set Question No: 12 ( Marks: 1 ) - Please choose one is one of the examples of asynchronous inputs. J-K input S-R input D input Clear Input (CLR) (Page 235) rep Question No: 13 ( Marks: 1 ) - Please choose one The input overrides the input Asynchronous, synchronous (Page 369) rep Synchronous, asynchronous Preset input (PRE), Clear input (CLR) Clear input (CLR), Preset input (PRE) Question No: 14 ( Marks: 1 ) - Please choose one Following Is the circuit diagram of mono-stable device which gate will be replaced by the red colored rectangle in the circuit. AND NAND NOR XNOR (Page 262) Question No: 15 ( Marks: 1 ) - Please choose one In outputs depend only on the combination of current state and inputs. Mealy machine (Page 332) Moore Machine State Reduction table State Assignment table

276 Question No: 16 ( Marks: 1 ) - Please choose one is used to simplify the circuit that determines the next state. State diagram Next state table State reduction State assignment (Page 335) rep Question No: 17 ( Marks: 1 ) - Please choose one A multiplexer with a register circuit converts Serial data to parallel Parallel data to serial (Page 356) rep Serial data to serial Parallel data to parallel Question No: 18 ( Marks: 1 ) - Please choose one In asynchronous transmission when the transmission line is idle, It is set to logic low It is set to logic high (Page 356) rep Remains in previous state State of transmission line is not used to start transmission Question No: 19 ( Marks: 1 ) - Please choose one In the following statement Z PIN 20 ISTYPE reg.invert ; The keyword reg.invert indicates An inverted register input An inverted register input at pin 20 Active-high Registered Mode output Active-low Registered Mode output (Page 360) Question No: 20 ( Marks: 1 ) A Nibble consists of bits - Please choose one 2 4 (Page 394) 8 16

277 Question No: 21 ( Marks: 1 ) - Please choose one The output of this circuit is always. 1 0 A Click here for detail rep Question No: 22 ( Marks: 1 ) - Please choose one At T0 the value stored in a 4-bit left shift was 1. What will be the value of register after three clock pulses? (not sure) rep Question No: 23 ( Marks: 1 ) - Please choose one A bidirectional 4-bit shift register is storing the nibble Its input is LOW. The nibble 0111 is waiting to be entered on the serial data-input line. After two clock pulses, the shift register is storing Click he re for detail Question No: 24 ( Marks: 1 ) - Please choose one The high density FLASH memory cell is implemented using 1 floating-gate MOS transistor (Page 419) rep 2 floating-gate MOS transistors 4 floating-gate MOS transistors 6 floating-gate MOS transistors Question No: 25 ( Marks: 1 ) - Please choose one In order to synchronize two devices that consume and produce data at different rates, we can use Read Only Memory Fist In First Out Memory (Page 425) Flash Memory Fast Page Access Mode Memory

278 Question No: 26 ( Marks: 1 ) - Please choose one If the FIFO Memory output is already filled with data then It is locked; no data is allowed to enter It is not locked; the new data overwrites the previous data. Previous data is swapped out of memory and new data enters None of given options Question No: 27 ( Marks: 1 ) - Please choose one The process of converting the analogue signal into a digital representation (code) is known as Strobing Amplification Quantization (Page 445) Digitization Question No: 28 ( Marks: 1 ) - Please choose one Above is the circuit diagram of. Asynchronous up-counter (Page 270) rep Asynchronous down-counter Synchronous up-counter Synchronous down-counter Question No: 29 ( Marks: 1 ) - Please choose one ( A B)(A B C)(A C) is an example of Product of sum form (Page 77) Sum of product form Demorgans law Associative law Question No: 30 ( Marks: 1 ) - Please choose one Q2 :=Q1 OR X OR Q3 The above ABEL expression will be Q2:= Q1 $ X $ Q3 Q2:= Q1 # X # Q3 (Page 210) Q2:= Q1 & X & Q3 Q2:= Q1! X! Q3

279 FINALTERM EXAMINATION Fall 2009 Question No: 1 ( Marks: 1 ) - Please choose one Caveman number system is Base number system 2 5 (Page 11) Question No: 2 ( Marks: 1 ) - Please choose one The output of an XOR gate is zero (0) when I) All the inputs are zero II) Any of the inputs is zero III) Any of the inputs is one IV) All the inputs are one I Only IV Only I and IV only (Page 53) II and III only Question No: 3 ( Marks: 1 ) - Please choose one The decimal 17 in BCD will be represented as 10001(right opt is not given) (According to rule) rep Question No: 4 ( Marks: 1 ) - Please choose one A Karnaugh map is similar to a truth table because it presents all the possible values of input variables and the resulting output of each value. True Click here for Detail rep False Question No: 5 ( Marks: 1 ) - Please choose one The simplest and most commonly used Decoders are the Decoders n to 2n (Page 158) (n-1) to 2n (n-1) to (2n-1) n to 2n-1

280 Question No: 6 ( Marks: 1 ) - Please choose one The Encoder is used as a keypad encoder. 2-to-8 encoder 4-to-16 encoder BCD-to-Decimal Decimal-to-BCD Priority (Page 166) Question No: 7 ( Marks: 1 ) - Please choose one 3-to-8 decoder can be used to implement Standard SOP and POS Boolean expressions True (Page 161) False Question No: 8 ( Marks: 1 ) - Please choose one If S=1 and R=0, then Q(t+1) = for positive edge triggered flip-flop 0 1 (Page 230) Invalid Input is invalid Question No: 9 ( Marks: 1 ) - Please choose one If the S and R inputs of the gated S-R latch are connected together using a gate then there is only a single input to the latch. The input is represented by D instead of S or R (A gated D-Latch) AND OR NOT (Page 226) XOR Question No: 10 ( Marks: 1 ) - Please choose one In asynchronous digital systems all the circuits change their state with respect to a common clock True False (Page 245) rep Question No: 11 ( Marks: 1 ) - Please choose one The low to high or high to low transition of the clock is considered to be a(n) State Edge (Page 228) Trigger One-shot

281 Question No: 12 ( Marks: 1 ) - Please choose one A positive edge-triggered flip-flop changes its state when Low-to-high transition of clock (Page 228) High-to-low transition of clock Enable input (EN) is set Preset input (PRE) is set Question No: 13 ( Marks: 1 ) - Please choose one RCO Stands for Reconfiguration Counter Output Reconfiguration Clock Output Ripple Counter Output Ripple Clock Output (Page 285) Question No: 14 ( Marks: 1 ) - Please choose one Bi-stable devices remain in either of their states unless the inputs force the device to switch its state Ten Eight Three Two (Page 262) rep Question No: 15 ( Marks: 1 ) - Please choose one is one of the examples of asynchronous inputs. J-K input S-R input D input Clear Input (CLR) (Page 255) rep Question No: 16 ( Marks: 1 ) - Please choose one occurs when the same clock signal arrives at different times at different clock inputs due to propagation delay. Race condition Clock Skew (Page 226) rep Ripple Effect None of given options Question No: 17 ( Marks: 1 ) - Please choose one A transparent mode means The changes in the data at the inputs of the latch are seen at the output (Page 245) The changes in the data at the inputs of the latch are not seen at the output Propagation Delay is zero (Output is immediately changed when clock signal is applied) Input Hold time is zero (no need to maintain input after clock transition)

282 Question No: 18 ( Marks: 1 ) - Please choose one In outputs depend only on the current state. Mealy machine Moore Machine (Page 332) State Reduction table State Assignment table Question No: 19 ( Marks: 1 ) - Please choose one The alternate solution for a multiplexer and a register circuit is Parallel in / Serial out shift register (Page 356) rep Serial in / Parallel out shift register Parallel in / Parallel out shift register Serial in / Serial Out shift register Question No: 20 ( Marks: 1 ) - Please choose one The alternate solution for a demultiplexer-register combination circuit is Parallel in / Serial out shift register Serial in / Parallel out shift register Parallel in / Parallel out shift register Serial in / Serial Out shift register (Page 356) rep Question No: 21 ( Marks: 1 ) - Please choose one In asynchronous transmission when the transmission line is idle, It is set to logic low It is set to logic high (Page 356) rep Remains in previous state State of transmission line is not used to start transmission Question No: 22 ( Marks: 1 ) - Please choose one Smallest unit of binary data is a Bit (Page 394) Nibble Byte Word Question No: 23 ( Marks: 1 ) - Please choose one A Nibble consists of bits 2 4 (Page 394) rep 8 16

283 Question No: 24 ( Marks: 1 ) - Please choose one A GAL is essentially a. Non-reprogrammable PAL PAL that is programmed only by the manufacturer Very large PAL Reprogrammable PAL (Page 183) rep Question No: 25 ( Marks: 1 ) - Please choose one A 8-bit serial in / parallel out shift register contains the value 8, clock signal(s) will be required to shift the value completely out of the register (Page 356) rep Question No: 26 ( Marks: 1 ) - Please choose one DRAM stands for Dynamic RAM (Page 407) rep Data RAM Demoduler RAM None of given options Question No: 27 ( Marks: 1 ) - Please choose one FIFO is an acronym for First In, First Out (Page 424) rep Fly in, Fly Out Fast in, Fast Out None of given options (Diagram is missing) Question No: 28 ( Marks: 1 ) - Please choose one In the circuit diagram of 3-bit synchronous counter shown above, The red rectangle would be replaced by which gate? AND OR NAND XNOR Question No: 29 ( Marks: 1 ) - Please choose one The sequence of states that are implemented by a n-bit Johnson counter is n+2 (n plus 2) 2n (n multiplied by 2) 2n (2 raise to power n) n2 (n raise to power 2) (Page 354) rep

284 Question No: 30 ( Marks: 1 ) - Please choose one Stack is an acronym for FIFO memory LIFO memory (Page 429) rep Flash Memory Bust Flash Memory FINALTERM EXAMINATION Fall 2009 Question No: 1 ( Marks: 1 ) - Please choose one The diagram given below represents Demorgans law Associative law Product of sum form Sum of product form (Page 78) rep Question No: 2 ( Marks: 1 ) - Please choose one Excess-8 code assigns to (Page 34) rep

285 Question No: 3 ( Marks: 1 ) - Please choose one NOR gate is formed by connecting OR Gate and then NOT Gate (Page 47) NOT Gate and then OR Gate AND Gate and then OR Gate OR Gate and then AND Gate Question No: 4 ( Marks: 1 ) - Please choose one A full-adder has a Cin = 0. What are the sum (<PRIVATE "TYPE=PICT;ALT=sigma"> ) and the carry (Cout) when A = 1 and B = 1? = 0, Cout = 0 = 0, Cout = 1 (Page 135) = 1, Cout = 0 = 1, Cout = 1 rep Question No: 5 ( Marks: 1 ) - Please choose one A particular half adder has 2 INPUTS AND 1 OUTPUT 2 INPUTS AND 2 OUTPUT (Page 134) 3 INPUTS AND 1 OUTPUT 3 INPUTS AND 2 OUTPUT Question No: 6 ( Marks: 1 ) - Please choose one THE FOUR OUTPUTS OF TWO 4-INPUT MULTIPLEXERS, CONNECTED TO FORM A 16-INPUT MULTIPLEXER, ARE CONNECTED TOGETHER THROUGH A 4-INPUT GATE AND OR (Page 171) NAND XOR Question No: 7 ( Marks: 1 ) - Please choose one A FIELD-PROGRAMMABLE LOGIC ARRAY CAN BE PROGRAMMED BY THE USER AND NOT BY THE MANUFACTURER. TRUE (Page 182) FALSE Question No: 8 ( Marks: 1 ) - Please choose one Flip flops are also called Bi-stable dualvibrators Bi-stable transformer Bi-stable multivibrators (Page 228) Bi-stable singlevibrators

286 Question No: 9 ( Marks: 1 ) - Please choose one A positive edge-triggered flip-flop changes its state when Low-to-high transition of clock (Page 228) High-to-low transition of clock Enable input (EN) is set Preset input (PRE) is set Question No: 10 ( Marks: 1 ) - Please choose one is one of the examples of synchronous inputs. J-K input (Page 235) EN input Preset input (PRE) Clear Input (CLR) Question No: 11 ( Marks: 1 ) - Please choose one THE GLITCHES DUE TO RACE CONDITION CAN BE AVOIDED BY USING A GATED FLIP-FLOPS PULSE TRIGGERED FLIP-FLOPS POSITIVE-EDGE TRIGGERED FLIP-FLOPS NEGATIVE-EDGE TRIGGERED FLIP-FLOPS (Page 267) rep Question No: 12 ( Marks: 1 ) - Please choose one The design and implementation of synchronous counters start from Truth table k-map state table state diagram (Page 319) rep Question No: 13 ( Marks: 1 ) - Please choose one THE HOURS COUNTER IS IMPLEMENTED USING ONLY A SINGLE MOD-12 COUNTER IS REQUIRED MOD-10 AND MOD-6 COUNTERS MOD-10 AND MOD-2 COUNTERS A SINGLE DECADE COUNTER AND A FLIP-FLOP (Page 299) rep Question No: 14 ( Marks: 1 ) - Please choose one Given the state diagram of an up/down counter, we can find The next state of a given present state (Page 371) rep The previous state of a given present state Both the next and previous states of a given state The state diagram shows only the inputs/outputs of a given states

287 Question No: 15 ( Marks: 1 ) - Please choose one In outputs depend only on the current state. Mealy machine Moore Machine (Page 332) rep State Reduction table State Assignment table Question No: 16 ( Marks: 1 ) - Please choose one A synchronous decade counter will have flip-flops 3 4 (Page 281) 7 10 Question No: 17 ( Marks: 1 ) - Please choose one A multiplexer with a register circuit converts Serial data to parallel Parallel data to serial (Page 356) rep Serial data to serial Parallel data to parallel Question No: 18 ( Marks: 1 ) - Please choose one The alternate solution for a multiplexer and a register circuit is Parallel in / Serial out shift register (Page 356) Serial in / Parallel out shift register Parallel in / Parallel out shift register Serial in / Serial Out shift register Question No: 19 ( Marks: 1 ) - Please choose one AT T0 THE VALUE STORED IN A 4-BIT LEFT SHIFT WAS 1. WHAT WILL BE THE VALUE OF REGISTER AFTER THREE CLOCK PULSES? (not sure) rep Question No: 20 ( Marks: 1 ) - Please choose one A 8-bit serial in / parallel out shift register contains the value 8, clock signal(s) will be required to shift the value completely out of the register (Page 356)

288 Question No: 21 ( Marks: 1 ) - Please choose one 5-BIT JOHNSON COUNTER SEQUENCES THROUGH STATES 7 10 (Page 354) rep Question No: 22 ( Marks: 1 ) - Please choose one In Q output of the last flip-flop of the shift register is connected to the data input of the first flip-flop of the shift register. Moore machine Meally machine Johnson counter Ring counter (Page 355) Question No: 23 ( Marks: 1 ) - Please choose one DRAM stands for Dynamic RAM (Page 407) rep Data RAM Demoduler RAM None of given options Question No: 24 ( Marks: 1 ) - Please choose one If the FIFO Memory output is already filled with data then It is locked; no data is allowed to enter It is not locked; the new data overwrites the previous data. Previous data is swapped out of memory and new data enters None of given options Question No: 25 ( Marks: 1 ) - Please choose one LUT is acronym for Look Up Table (Page 439) rep Local User Terminal Least Upper Time Period None of given options Question No: 26 ( Marks: 1 ) - Please choose one of a D/A converter is determined by comparing the actual output of a D/A converter with the expected output. Resolution Accuracy (Page 460) rep Quantization Missing Code

289 (Diagram is missing) Question No: 27 ( Marks: 1 ) - Please choose one In the circuit diagram of 3-bit synchronous counterthe red rectangle, shown above would be replaced which gate? AND OR NAND XNOR Question No: 28 ( Marks: 1 ) - Please choose one WHEN BOTH THE INPUTS OF EDGE-TRIGGERED J-K FLOP-FLOP ARE SET TO LOGIC ZERO THE FLOP-FLOP IS TRIGGERED Q=0 AND Q =1 Q=1 AND Q =0 THE OUTPUT OF FLIP-FLOP REMAINS UNCHANGED (page 223) Question No: 29 ( Marks: 1 ) - Please choose one A frequency counter Counts pulse width Counts no. of clock pulses in 1 second (Page 301) Counts high and low range of given clock pulse None of given options rep Question No: 30 ( Marks: 1 ) - Please choose one Stack is an acronym for FIFO memory LIFO memory (Page 429) rep Flash Memory Bust Flash Memory

290 CS302- Digital Logic Design SOLVED SUBJECTIVE FROM FINAL TERM PAPERS Jun 03,2011 Latest Subjective MC PSMD01(IEMS) FINAL TERM EXAMINATION Fall In the highest frequency component in an analog signal is 20 KHz, what is the minimum sample frequency (Marks 2) Answer:- Click here for detail In the highest frequency component in an analog signal is 20 KHz, and minimum sample frequency is 40 KHz. 2. Write down the ABEL symbols that are used for NOT, AND, OR and XOR operations. (Marks 2) Answer:- Page 201 Logic Operation ABEL Symbol NOT! AND & OR # XOR $ 3. Differentiate between Moore machine and Mealy machine. (Marks 2) Answer:- Page 318 The Sequential circuit whose output depends on the current state and the input is known as Mealy Machine. Sequential circuit whose output is determined by the current state only is known as Moore Machine. 4. How many bytes will be there in 16K x 8 memory? (Marks 2) Answer:- Page 395 A 16 K x 8 memory, stores 16K bytes or 16 x 1024 = bytes or bits. 1. How many address bits are required for a 2048-bit memory organized as a 256 x 8 memory? (Marks 3) 2. Explain Rotate Right Operation of shift register with the help of Diagram. (Marks 3) Answer:- Page 354 The serial output of the register is connected to the serial input of the register. By applying clock pulses data is shifted right. The data shifted out of the serial out pin at the right hand side is re-circulated back into the shift register input at the left hand side. Thus the data is rotated right within the register.

291 3. Difference between State Assignment and State Reduction process. (Marks 3) Answer:- (Page 332 & 335) 1. In state Reduction A state diagram show the sequence of current and next states through which the state machine sequences while in State Assignment Each state in a sequential circuit is identified by a unique combination of binary bits. 2. In state Reduction the transition from a current state to the next state is determined by current state and the inputs while in State Assignment the states can be selected to allow minimum bit changes when changing from one state to the other. 3. State Assignment results in simpler combinational circuits that determine the next state while Reduction in the number of state results in fewer flip-flops and a simpler circuit. 4. Explain Full-Adder Sum and Carry out Boolean Expression. (Marks 3) Answer:- (Page 135) Full-Adder Sum & Carry Out Boolean Expressions The Sum and Carry Out expressions of the Full-Adder can be determined from the function table. The Full-Adder Sum and Carry Out outputs are defined by the expressions Sum = ABC + ABC + ABC + ABC Sum = A(BC + BC) + A(BC + BC) Sum = A(B C) + A(B C) Sum = A B C CarryOut = ABC + ABC + ABC + ABC CarryOut = C(AB + AB) + AB(C + C) CarryOut = C(A B) + AB 1. Explain Latches in your own words. (Marks 5) Answer:- (Page 218) A latch is a temporary storage device that has two stable states. A latch output can change from one state to the other by applying appropriate inputs. A latch normally has two inputs, the binary input combinations at the latch input allows the latch to change its state. A latch has two outputs Q and its complement Q(bar). The latch is said to be in logic high state when Q=1 and Q(bar)=0 and it is in the logic low state when Q=0 and Q(bar)=1. When the latch is set to a certain state it retains its state unless the inputs are changed to set the latch to a new state. Thus a latch is a memory element which is able to retain the information stored in it.

292 2. Differentiate between synchronous and asynchronous memory. (Marks 5) Answer:- (Page 406) In the Asynchronous memory the various input signals are asynchronous and are not tied to the clock, whereas in the Synchronous memory all the inputs are synchronized with respect to the clock and are latched into their various registers on an active clock pulse edge. 4. Draw state diagram of Moore machine. (Marks 5) Answer:- (Page 338) FINAL TERM EXAMINATION Spring 2011 Question No: ( Marks: 2 ) Write down at least two applications of a shiftregister. Answer:- (Page 356) The two applications of the shift registers are 1. Serial to Parallel converter 2. Keyboard encoder Question No: ( Marks: 2 ) Explain memory expansion process. Answer:- (Page 430) Computer and Digital systems have the capability to allow RAM memory to be expanded as the needed arises by inserting extra memory in dedicated memory sockets on the computer motherboard.

293 Question No: ( Marks: 2 ) Draw the NOR based S-R Latch Answer:- (Page 220) Question No: ( Marks: 3 ) Explain Rotate Left Right Operation with the help of diagram. Answer:- (Page 354) Question No: ( Marks: 3 ) You are given the block diagram of 74HC190 integrated circuit up/down counter, explain the function of labeled inputs/outputs. Answer:-(Page 295)

294 1. Active-low CTEN counter enable input 2. D/U the count down/up input. When the input is set to logic 1, the counter counts down and when the input is set to logic 0, the counter counts up 3. The MAX/MIN output that is set to high when the terminal count 1001 is reached when counting up or when the terminal count 0000 is reached when counting down. The MAX/MIN output is logic high for one complete cycle when a terminal count is reached. Question No: ( Marks: 5 ) Explain Memory Select or Enable Signals Answer:- (Page 397) In a computer system there are more than one memory chips to store program information. At any particular instant a read or write operation is carried out on a single addressable location. The unique location can only be accessed in one of the several memory chips, thus a single memory chip has to be selected before a read or write operation can be carried out. All memory chips have a chip enable or chip select signal which has to be activated before the memory can be accessed. Question No: ( Marks: 5 ) Explain the implementation of First In First Out (FIFO) Memory by using RAM. Answer:- (Page 427) Shift register based FIFO memory is used in digital systems designed for specific applications where small sized buffers are used to allow transfer of data between two devices operating at different data rates. Such digital systems either have no RAM or very small RAM for storing variables. Computers implement FIFO memory by reserving a part of their RAM memory for use as buffers. The Keyboard buffer for example is implemented by reserving a part of the RAM. When RAM is used as FIFO memory, two registers are used to point to the FIFO Buffer Out and Buffer In respectively. The two registers hold the addresses of the locations of the Buffer Out and Buffer In respectively, which are updated as new data is written into the buffer and previous data is read out from the FIFO buffer. Implementation of the FIFO buffer in RAM is usually takes the form of a circular buffer. Question No: ( Marks: 5 ) Explain application of demultiplexer Answer:- (Page 178) Demultiplexer is used to connect a single source to multiple destinations. One use of the Demultiplexer is at the output of the ALU circuit. The output of the ALU has to be stored in one of the multiple registers or storage units. The Data input of the Demultiplexer is connected to the output of the ALU. Each output of the Demultiplexer is connected to each of the multiple registers. By selecting the appropriate output data from the ALU is routed to the appropriate register for storage. The second use of the Demultiplexer is the reconstruction of Parallel Data from the incoming serial data stream. Serial data arrives at the Data input of the Demultiplexer at fixed time intervals. A counter attached to the Select inputs of the Demultiplexer routes the incoming serial bits to successive outputs where each bit is stored. When all the bits have been stored, data can be read out in parallel.

295 FINAL TERM EXAMINATION Spring 2011 Question No: 27 ( Marks: 2 ) 1: Explain the erase operation in context of Flash Memory. Answer:- (Page 421) During the erase operation charge is removed from the memory cell. A sufficiently large positive voltage is applied at the source with respect to the control gate. The voltage applied across the control gate and source is opposite to the voltage applied during programming. If charges are present on the gate, the positive voltage supply at the source attracts the electrons depleting the gate. A FLASH memory is erased prior to programming. 2: How can a serial in/parallel out register be used as a serial in/serial out register? 3: Explain the next-state table with the help of a table for any sequential circuit? Answer:- (Page 306) Once the state diagram of the sequential circuit is defined, a Next-State Table is derived which lists each present state and the corresponding next state. The next state is the state to which the sequential circuit switches when a clock transition occurs. Present State Next State Q2 Q1 Q0 Q2 Q1 Q : What is meant by Non-Monotonicity of Digital to Analog converter? Answer:- (Page 460) if the D/A converter outputs a lower voltage than its preceding output voltage the converter is said to exhibit non-monotonic behavior. 5: Two state assignments are given in the table below. Identify which state assignment is best and why? States State assignment 1 State assignment 2 A B C D 10 11

296 6: Write down at least two functions of a register. Answer:- (Page 306) Technically, a register performs two basic functions. It stores data and it moves or shifts data. The shifting of data involves shifting of bits from one flip-flop to the other within the register or moving data in and out of the register. The shift operation of the binary data is carried out by applying clock signals. Several different kinds of shift operations can be identified. 7: You are given the Next-state table of a Moore machine, using this information draw the state diagram of the machine. Present State Next State Q 2 Q 1 Q 0 Q 2 Q 1 Q Answer:-(Page 338) FINAL TERM EXAMINATION Spring 2011 QNo.1 Define the term Variable in context of Boolean algebra. Answer:- (Page 71) A variable is a symbol usually an uppercase letter used to represent a logical quantity. A variable can have a 0 or 1 value.

297 Q No.2 A general sequential circuit consists of a combinational circuit and memory elements. How this Memory element is implemented. Answer:- (Page 318) A general Sequential circuit consists of a combinational circuit and a memory element. The memory element is made of a set of n flip-flops all connected to a a common clock. The n flip flops store 2n states. The flip-flops change their current state to the next state on each clock transition. The next state is determined by the current state and the external input. The output of the State Machine is determined by the current state and external input. The inputs to the memory which allow the memory to change its state on a clock transition are known as excitation inputs or excitation variables. Q No.3 what is meant by Monotonicity of Digital to Analog converter? Answer:- (Page 460) The output of the D/A converter should give an increasing analogue voltage output when the binary input is varied between its minimum and maximum values. Q No.4 Explain Programmable Logic Devices? Answer:-(Page 179) Programmable Logic Devices are used in many applications to replace the Logic gates and MSI chips. PLDs save circuit space and reduce and save the cost of components in a Digital Circuit. PLDS consists of Arrays of AND gates and OR gates that can be programmed to perform specific functions. Q No.5 How many clock pulses are required to enter a byte of data serially into an 8-bit shift register? 2 Answer:- 8 clock pulses are required to enter a byte of data serially into an 8- bit shift register Q No. 6 How can calculate the frequency of an unknown signal? Answer:-(Page 301) The frequency of the unknown signal can be calculated by counting the number of clock pulses of the unknown signal and dividing the count number by the time interval in which the clock pulses are counted, Q No. 7 Write the drawbacks of 16-bit ALU without look-ahead carry circuit? Q No. 8 How many address bit are required for a 2048-bit memory organized as a 256*8 memory? Q No. 9 Differentiates between Memory capacity and Memory Density? Answer:- (Page 395) Each memory array has a maximum capacity to store information in the form of bits. Memory density on the other hand specifies the number of bits stored per unit area. More the number of bits stored in a unit area more dense the memory, that is, more bits are stored in less space. Q No. 10. Explain Memory Select or Enable signal? Answer:- (Page 397) In a computer system there are more than one memory chips to store program information. At any particular instant a read or write operation is carried out on a single addressable location. The unique location can only be accessed in one of the several memory chips, thus a single memory chip has to be selected before a read or write operation can be carried out. All memory chips have a chip enable or chip select signal which has to be activated before the memory can be accessed.

298 Q No 11. Explain state Assignment Process. Answer:-(Page 335) Each state in a sequential circuit is identified by a unique combination of binary bits. Unless the output of the sequential is directly taken form the flip-flop outputs such as counters, the states can be selected to allow minimum bit changes when changing from one state to the other. Keeping the bits changes to minimum when changing from one state to the next, results in simpler combinational circuits that determine the next state. Q No 12. Briefly Explain Next-state table with the help of any sequential circuit.5 Answer:- Repeated FINAL TERM EXAMINATION Spring In the highest frequency component in an analog signal is 20 KHz, what is the minimum sample frequency Answer:- Repeated 2. How many bytes will be there in 16K x 8 memory? Answer:- Repeated 3. Convert the hexadecimal number 7AB1 into binary numbers. Write down all the steps. Answer:- (Page 27) Replacing each Hexadecimal digit by its 4-bit binary equivalent 7= 0111, A= 1010, B=1011, 1= 0001 So, 7AB1 = Explain grouping of cells in k-map. 3 Answer:- (Page 90) Groups are formed on the basis of 1s (Minterms) or 0s (maxterms). A group is selected to have maximum number of cells of Minterms or Maxterms, keeping in view that the size of the group should be a power of 2. The idea is to form minimal number of largest groups that uniquely cover all the cells, thereby ensuring that all minterms or maxterms are included. 5. Provide some of guidelines for selection of state assignment. 3 Answer:-(Page 337) Generally, the selection of State Assignment is based on the following guidelines. Choose an initial coded state into which the state machine (sequential circuit) can easily be forced to reset (000 or 111) Minimize the State Variables that change on each transition Maximize the number of state variables that don t change in a group of related states If there are unused states, then choose the best state variable combinations to achieve the first three goals.

299 6. Discuss at least one difference in Johnson and ring Counter 3 Answer:-(Page 355) The Ring Counter is similar to the Johnson counter, except that the Q output of the last flip-flop of the shift register is connected to the data input of the first flip-flop of the shift register. 7. Three types of error while converting Analogue signal into digital. 3 Answer:-(Page 354) 1. Missing Code 2. Incorrect Code 3. Offset Error 8. Explain memory read operation with help of example 5 Answer:- (page 397) Memory Read operation is carried out by first selecting the memory chip by activating the Memory Select signal. The Read signal is asserted to configure the memory circuitry for reading data from the memory. An address (100) is applied on the Address Lines. The internal address decoder of the memory decodes the address and selects one unique row from which data is read. Figure The address of the location in the memory from which data is to be read is supplied by the microprocessor. The microprocessor stores the address in its address buffer. The data read from the memory is stored in a data buffer inside the microprocessor. In the diagram shown, a microprocessor places an address 100 on its external address bus connected to the address lines of the memory. The internal address decoder of the memory decodes the address 100 and activates a row select line which selects the row location 4. The data ( ) at the location is read from the memory and placed on the data bus where it is latched by the microprocessor and stored in its data buffer. 9. Explain flesh analogue to digital converter 5 Answer:- (Page 447) The Flash A/D converter is based on a resistor potential divider, where multiple resistors of identical value form a voltage divider. A reference voltage is applied at one end of the potential divider which divides the voltage equally across all the resistors. The input analogue voltage is applied at the non-inverting inputs of a set of Op- Amp based comparators. The inverting input of each comparator is connected to the resistive voltage divider which provides reference voltages for all the comparators. If the input voltage is larger than the reference voltage the output of the comparator is logic high otherwise it is logic low. The outputs of all the comparators are connected to the input of a priority encoder which converts the comparator outputs to a binary coded equivalent value.

300 10. Briefly explain address multiplexing in DRAM. 5 Answer:- (Page 410) DRAM chips use address multiplexing to reduce the number of address lines by half. The address required to select a memory location is split into row and column addresses. To access a DRAM location for reading or writing of information the row address is first applied at the address lines. The row address is latched by the Row Address Latch of the DRAM memory chip. The column address is applied next at the same address lines. The column address is latched by the Column Address Latch. Two signals RAS and CAS are used as strobe signals to control the Row Address and Column Address latches respectively. The external address lines are multiplexed as the same set of address lines are used to apply the row address and the column address at different time instances. The outputs of the Row Address Latch and the Column Address Latch are connected to the Row and Column Decoders which select a single row and column line selecting the storage cell to be accessed. FINAL TERM EXAMINATION Spring 2011 Explain READ Write signal used for memory. 03 Answer:- (Page 396) Read/Write signals are required to configure the memory for read and write operation. Memory chips have a single Read/Write signal. When the signal is set to high it allows data to be read from the memory. When the signal is set to low data is written into the memory. Some memory chips have two separate Read and Write signals. The read and write signals are separately asserted to control the Read and Write operation. What is difference between PROM and ROM. 03 Answer:- Click here for detail The difference between a PROM and a ROM (read-only memory) is that a PROM is manufactured as blank memory, whereas a ROM is programmed during the manufacturing process. To write data onto a PROM chip, you need a special device called a PROM programmer or PROM burner. The process of programming a PROM is sometimes called burning the PROM. Making decade counter by cascading two 74HC What is difference between memory capacity and memory density? 05 Answer:- Repeated Describe Flash Analogue to Digital converter. 05 Answer:- Repeated

301 Explain don s care condition. Answer:- (Page 96) Function Tables represent the function by listing all the possible inputs and marking the corresponding outputs with 1s and 0s. Thus a circuit having four inputs can be described by a 4-variable function table having 16 possible input combinations. For each of the 16 possible input conditions the corresponding output bits are marked as 1s and 0s depending upon the minterms or maxterms. It is however, possible that out of the 16 possible input combinations, three input combinations never occur. Since these three input combinations never occur so should their corresponding outputs be marked as 0s or 1s? Since these inputs never care therefore we don t need to worry about the output of these input states. They are considered to be don t care conditions. FINAL TERM EXAMINATION 2011 Question#1 Give advantages of Counters are available in integrated circuits? (Marks 2) Question #2 Successive approximation counter have a fixed consecutive time Is tarha ka qs tha (Marks 2) Question #4 How many states in 8-bit Johnson counter? (Marks 2) Answer:-(Page 354) The sequence of states that are implemented by a n-bit Johnson counter are 2n So, 8 bit Johnson counter has 2*8 = 16 states Question #5 Diff b/w truth table and next state table (Marks 3) Question #6 How hexadecimal number is converted into binary number give one example? (Marks 3) Answer:-(Page 28) Converting from Hexadecimal back to binary is also very simple. Each digit of the Hexadecimal number is replaced by an equivalent binary string of 4-bits. FD13 Hexadecimal Number Replacing each Hexadecimal digit by its 4-bit binary equivalent Question #7 Diff b/w ROM and PROM? (Marks 3) Answer:- Repeat Question #8 How we can implement full adder from two half adder? (Marks 3) Answer:- Repeat

302 Question #9 Make State diagram? Answer:- Repeat Question #10 Explain FRGA? (Marks 5) Answer:- (Page 437) Programmable Logic Devices are based on a programmable AND-OR gate array which are programmed to implement any function in the SOP form. The output of the AND-OR gate array can be directly used as a combinational circuit output. Provision is there to connect the output of the AND-OR gate array to a D-flip-flop for Sequential circuit operation. An FPGA is a more flexible device than PLDs as instead of a single AND-OR gate array, an FPGA device contains multiple logic blocks that can be individually programmed to perform different functions. Each Logic Block is connected to other blocks through row and column interconnects that can be programmed to connect any Logic block to another. Question #11 (Marks 5) Differentiate b/w memory density and memory capacity? Answer:- Repeated FINAL TERM EXAMINATION Spring 2010 Question No: 27 (Mark s: 2) Define quantization process. Answer:- (Page 444) The process of converting the analogue signal into a digital representation (code) is known as quantization Question No: 28 (Marks: 2) Explain the difference between 1-to-4 Demultiplexer and 2-to-4 Binary Decoder? Answer:- (Page 178) The only difference between the two is the addition of the Data Input line, which is used as enable line in the 2-to-4 Decoder circuit figure Assuming the select inputs I1 and I0 are set to 1 and 0 respectively. The O2 output is set to 1 if the Data input is 1 or it is set to 0 if the Data input is 0. Question No: 29 (Marks: 2) A general Sequential circuit consists of a combinational circuit and a memory element. How this memory element is implemented Answer:- Repeated Question No: 30 (Marks: 2) Suppose a 2 bit up-counter, having states A, B, C, D. Write down GOTO statements to show how present states change to next states.

303 Question No: 31 (Marks: 3) Name three Operations that can be performed on FLASH Memory Answer:- (Page 420) FLASH Memory operations are classified into Programming Operation Read Operation Erase Operation Question No: 32 (Marks: 3) Explain Rotate Right Operation of shift register with the help of diagram. Answer:- Repeated Question No: 33 ( Marks: 3 ) You are given the block diagram of 74HC190 integrated circuit up/down counter, explain the function of labeled inputs/outputs. Answer:- Repeated Question No: 34 ( Marks: 5 ) Draw the state diagram of 3-bit up-down counter, use an external input X, when X sets to logic 1, the counter counts downwards, otherwise upward. Question No: 35 (Marks: 5) Differentiate between synchronous and asynchronous RAM. Answer:- (Page 406) Synchronous RAM is very similar to the Asynchronous RAM, in terms of the memory array, the address decoders, read/write and enable inputs. In the Asynchronous memory the various input signals are asynchronous and are not tied to the clock, whereas in the Synchronous memory all the inputs are synchronized with respect to the clock and are latched into their various registers on an active clock pulse edge. Question No: 36 ( Marks: 5 ) Explain Memory Select or Enable Signals Answer:- Repeated

304 FINAL TERM EXAMINATION Spring 2010 Question No: 27 ( Marks: 2 ) Draw the Truth-Table of NOR based S-R Latch Answer:- (Page 222) Input Output S R Q t Q t invalid Table 22.3 Truth-Table of NOR based S-R Latch Question No: 28 ( Marks: 2 ) Two state assignments are given in the table below. Identify which state assignment is best and why? States State Assignment 1 State Assignment 1 A B C D Question No: 29 ( Marks: 2 ) Write down at least two functions of a register. Answer:- Repeat Question No: 30 ( Marks: 2 ) Define quantization process. Answer:- Repeat Question No: 31 ( Marks: 3 ) How can we calculate the frequency of an unknown signal? Answer:- Repeat Question No: 32 ( Marks: 3 )

305 Given the following statement used in PLD programming: Y PIN 23 ISTYPE com ; Explain what does this statement mean? Answer:- (Page 360) The statement describes Y available at output pins 23. The Y variable is a Combinational output available directly from the AND-OR gate array output. The active-low or active-high output of the Registered Mode can also be specified in the declaration statement Question No: 33 ( Marks: 3 ) Explain dynamic RAM in your own words. Answer:- Click here for detail Dynamic random-access memory (DRAM) is a type of random-access memory that stores each bit of data in a separate capacitor within an integrated circuit. The capacitor can be either charged or discharged; these two states are taken to represent the two values of a bit, conventionally called 0 and 1. Since capacitors leak charge, the information eventually fades unless the capacitor charge is refreshed periodically. Because of this refresh requirement, it is a dynamic memory as opposed to SRAM and other static memory. Question No: 34 ( Marks: 5 ) You are given the Next-state table of a Moore machine, using this information draw the state diagram of the machine. Answer:- repeat Present State Next State Q 2 Q 1 Q 0 Q 2 Q 1 Q Question No: 35 ( Marks: 5 ) Explain Memory Select or Enable Signals Answer:- repeat Question No: 36 ( Marks: 5 ) Performance characteristics of D/A converters are determined by five parameters. Name them. Answer:- (Page 460) Performances characteristics of D/A converters are determined by five parameters are: 1. Resolution 2. Linearity 3. Monotonicity 4. Setting time 5. Accuracy FINAL TERM EXAMINATION

306 Spring 2010 Question No: 27 (Marks: 2) Explain the erase operation in context of Flash Memory. Answer:- repeat Question No: 28 (Marks: 2) Explain the difference between 1-to-4 Demultiplexer and 2-to-4 Binary Decoder? Answer:- repeat Question No: 29 (Marks: 2) Some of the counters (e.g. 74HC163) are called pre-set counters. why? Answer:- Click here for detail 74HC163) are called pre-set counters because A counter set in advance to stop or produce output once a specific count has been reached. Question No: 30 (Marks: 2) How many bytes will be there in 32 K x 8 memory? Answer:- (Page 395) A 32 K x 4 memory stores 32K nibbles or 32 x 1024 = nibbles Question No: 31 (Marks: 3) Differentiate between truth table and next-state table Question No: 32 (Marks: 3) Name the three types of errors Analogue to Digital converters exhibit during their conversion operation. Answer:- repeat Question No: 33 (Marks: 3) How can a serial in/parallel out register be used as a serial in/serial out register? Question No: 34 (Marks: 5) Explain the implementation of First In First out (FIFO) Memory by using RAM. Answer:- repeat Question No: 35 (Marks: 5) Explain memory read operation with the help of an example Answer:- repeat Question No: 36 (Marks: 5) Explain the next-state table with the help of a table for any sequential circuit Answer:- repeat

307 CS302- Digital Logic Design Dec 07,2011 SUBJECTIVE SOLVED FROM MIDTERM PAPERS MC PSMD01(IEMS)

308 MIDTERM EXAMINATION 2011 (October-November) Q-21 Draw function table of a half adder circuit? (2) Answer: - Page 135 Lec14 Q-22 What is difference b/w BCD to decimal decoder and binary 4-to-16 bit decoder? (2) Answer: (Page 163) Lec17 The operation of the BCD-to-Decimal Decoder is the same as a Binary 4-to-16 decoder, the only difference being that the BCD-to-Decimal Decoder has ten output pins instead of sixteen and the input is a valid BCD number. Q-23 Explain major use of decoder circuits? (3) Lec16 Answer: (Page 158) Decoders have two major uses in Computer Systems. 1. Selection of Peripheral Devices Computers have different internal and external devices like the Hard Disk, CD Drive, Modem, Printer etc. Each of these different devices is selected by specifying different codes. A decoder similar to the Electronic Door Lock/Unlock circuit is used to uniquely select or deselect the appropriate devices. 2. Instruction Decoder Computer programs are based on instructions which are decode by the Computer Hardware and implemented. These instruction codes are decoded by an Instruction Decoder to generate signals that control different logic circuits like the ALU and memory to perform these operations. Q-25 PALS comes in different configurations and are identified by a unique number, identify parts of this number? (5) Answer: (Page 186) Lec19 PALs come in different configurations they are identified by unique number. The numbers begin with the prefix PAL followed by two digits that indicate the number of inputs followed by a letter L active-low, H active-high or P programmable polarity followed by a single or two digits that indicate the number of outputs. In addition to the standard number there may be suffixes which specify the speed, package type and temperature range

309 Q-26 One of the ABEL entry methods uses logic equation. Explain at least two examples? (5) Answer: (Page 201) Lec20 ABEL however is case sensitive, thus variable A is treated separately from variable a. All ABEL equations must end with ;. Examples:- (a) (b) Solution (a)x = A&!B & C #!A &!B &!C # A & B #!B & C; (b)y = (!A # B #!C #D) & (A # B # C); MIDTERM EXAMINATION 2011 (October-November) Q-21 Draw the function table of 2-to-4 decoder (2 marks) Answer: (Page 158) Lec16 A 2-to-4 Decoder is represented by the function table. Input Output I 1 I 0 O 0 O 1 O 2 O Function Table of a 2-to-4 Binary Decoder

310 Q-24 Explain BCD to Decimal Decoder (3marks) Answer: (Page 163) Lec17 "The operation of the BCD-to-Decimal Decoder is the same as a Binary 4-to-16 decoder, the only difference being that the BCD-to-Decimal Decoder has ten output pins instead of sixteen and the input is a valid BCD number. Thus invalid BCD codes 1010, 1011, 1100, 1101, 1110 and 1111 applied at the input of the Decoder do not activate any of the ten outputs." Q-26 Explain 8-input Multiplexer with the help of circuit Diagram and Function Table. (5marks) Answer: (Page 170) Lec18 Input Output C B A F C C C C C C C C3

311 Q-21 MIDTERM EXAMINATION 2011 (October-November) What is meant by ABEL? (2 marks) Answer: (Page 201) Lec20 ABEL which is an acronym for Advanced Boolean Expression Language is hardware description language used for implementing logic designs using PLDs. Q-22 Why preferable to use another method than 5-variable K-Map? (2 marks) Answer: (Page 102) Lec11 Karnuagh map method becomes difficult to manage when numbers of variables exceed 4. In both the Karnaugh maps, finding the redundant terms is not very obvious. The Quine-McCluskey approach of simplifying Boolean expression is based on an exhaustive search where each minterm is compared with every other minterm in order to remove single variables. Q-24 Draw circuit diagram of 2-input of 8-bit multiplexer? Answer: (Page 172) Lec18 (3 marks)

312 Q-25 Uses of Demultiplexer? (5 marks) Answer: (Page 178) Lec19 Demultiplexer is used to connect a single source to multiple destinations. One use of the Demultiplexer is at the output of the ALU circuit. The output of the ALU has to be stored in one of the multiple registers or storage units. The Data input of the Demultiplexer is connected to the output of the ALU. Each output of the Demultiplexer is connected to each of the multiple registers. By selecting the appropriate output data from the ALU is routed to the appropriate register for storage. The second use of the Demultiplexer is the reconstruction of Parallel Data from the incoming serial data stream. Serial data arrives at the Data input of the Demultiplexer at fixed time intervals. A counter attached to the Select inputs of the Demultiplexer routes the incoming serial bits to successive outputs where each bit is stored. When all the bits have been stored, data can be read out in parallel. MIDTERM EXAMINATION 2011 (October-November) Q-21 Define Sequential Circuit. MARKS: 2 Answer: (Page 8) Lec1 Digital circuits that generate a new output on the basis of some previously stored information and the new input are known as Sequential circuits. Digital circuits that use memory elements for their operation are known as Sequential circuits. (Page 218) Q-22 How a circuit with multiple outputs is shown in truth table? MARKS: 2 Answer: (Page 103) Lec11 Circuits having multiple outputs are represented by multiple function tables one for each output or a single function table having multiple output columns. The example of a BCD to 7-Segment Decoder circuit which has 4 inputs and 7 outputs is considered to explain functions having multiple outputs. Q-23 How decoder is used as demultiplexer. MARKS: 3: Answer: (Page 178) Lec19 A Demultiplexer is available as a Decoder/Demultiplexer chip which can be configured to operate as a Demultiplexer or a Decoder.

313 Q-21 Draw the Tri_state buffer. 2 Answer: (Page 196) Lec20 MIDTERM EXAMINATION 2011 (October-November) Q-22 Draw the half adder graph. 2 Answer: (Page 134) Lec14 Q-23 Draw NOR gate based S_R (set rest) Latch. 3 Answer: (Page 220) Lec22

314 Q-22 MIDTERM EXAMINATION 2011 (October-November) Two bit comparator? Explain by at least one example Answer: (Page 109) Lec12 A 2-bit Comparator circuit compares two 2-bit numbers A and B. The comparator circuit has three outputs. It sets the A>B output to 1 if A>B. It sets the A=B output to 1 if A=B and sets A<B output to 1 if A < B. Q-23 Explain PLDs Answer: (Page 179) Lec19 Programmable Logic Devices are used in many applications to replace the Logic gates and MSI chips. PLDs save circuit space and reduce and save the cost of components in a Digital Circuit. PLDS consists of Arrays of AND gates and OR gates that can be programmed to perform specific functions. Q-24 Comparator All possibilities for A = B. Answer: (Page 109) Lec12 The output A=B is set to 1 when the input combinations are 00 00, 01 01, and Q-25 one diagram for PLD array with its fuses connecting columns to rows Answer: (Page 180) Lec19

315 MIDTERM EXAMINATION 2011(May) Define decoder 2 marks Answer:- (Page 157) A Decoder has multiple inputs and multiple outputs. The Decoder device accepts as an input a multi-bit code and activates one or more of its outputs to indicate the presence of the multi-bit code. Why S and R input of NAND based latch should not be at logic high at same time 2 marks Answer:- (Page 220) When inputs are S = 1 and R = 0 the output Q is set to 0. Inputs S = 0 and R = 0 are not applied as they place the latch in an invalid state. The NAND gate based S-R latch has active-low inputs." 2 input 4 bit multiplexer function table 3 marks Answer:- (Page 169) Inputs Outputs G S 1Y 2Y 3Y 4Y 1 X A 2A 3A 4A 0 1 1B 2B 3B 4B Table 18.1 Function table of 2-Input 4-Bit Multiplexer Half adder explanation its function table Boolean expression and circuit diagram 5 marks Answer:- (Page 134) Half-Adder A Half-Adder can be fully described in terms of its Function table, its Sum and Carry Out Boolean Expressions and the circuit Implementation. Half-Adder Function Table The Half-Adder has a 2-bit input and a 2-bit output. The function table of the Half-Adder has two input columns representing the two single bit numbers A and B. The function table also has two output columns representing the Sum bit and Carry Out bit. Half-Adder Sum & Carry Out Boolean Expressions The Sum and Carry Out expressions of the Half-Adder can be determined from the function table. The Half-Adder Sum and Carry Out outputs are defined by the expressions

316 Explain S-R latch in your own words Answer:- (Page 218) A latch is a temporary storage device that has two stable states. A latch output can change from one state to the other by applying appropriate inputs. A latch normally has two inputs, the binary input combinations at the latch input allows the latch to change its state. A latch has two outputs Q and its complement Q The latch is said to be in logic high state when Q=1 and Q =0 and it is in the logic low state when Q=0 and Q =1. When the latch is set to a certain state it retains its state unless the inputs are changed to set the latch to a new state. Thus a latch is a memory element which is able to retain the information stored in it. MIDTERM EXAMINATION 2011 Write down the ABEL symbols that are used for NOT, AND, OR and XOR operations. Answer:- (Page 201) NOT=! AND= & OR = # XOR =$. MIDTERM EXAMINATION 2010 Question No: 17 ( Marks: 2 ) Why a 2-bit comparator is called parallel comparator? Answer:- (Page 154) The 2-bit Comparator discussed earlier is considered to be a Parallel Comparator as all the bits are compared simultaneously. External Logic has to be used to Cascade together two such Comparators to form a 4-bit Comparator. Question No: 18 ( Marks: 2 ) Explain at least two advantages of the circuit having low power consumption Answer:- (Page 65)

317 Advantages of low power consumption are circuits that can be run from batteries instead of mains power supplies. Thus portable devices that run on batteries. Secondly, low power consumption means less heat is dissipated by the logic devices; this means that logic gates can be tightly packed to reduce the circuit size without having to worry about dissipating the access heat generated by the logic devices. Question No: 19 ( Marks: 2 ) Name the four OLMC configurations Answer:- (Page 196) The four OLMC configurations are Combination Mode with active-low output Combinational Mode with active-high output Registered Mode with active-low output Registered Mode with active-high output Question No: 20 ( Marks: 3 ) Explain Test Vector in context of ABEL Answer:- (Page 204) Once the Logic circuit design has been entered its operation is verified by using test vectors. A test vector specifies the inputs and the corresponding outputs. The software simulates the operation of the logic circuit by applying the test vector and checking the outputs. Test vectors are essentially the same as Truth Tables Question No: 21 ( Marks: 3 ) For a two bit comparator circuit specify the inputs for which the output A < B is set to 1 Answer:- (Page 109) The output A<B is set to 1 when the input combinations are 00 01, 00 10, 00 11, 01 10, and Question No: 22 ( Marks: 5 ) Explain Tri-State Buffers with the help of block diagram Answer:- (Page 196) Tri-State Buffer is a NOT gate with a control line that disconnects the output from the input. When the control line is high the buffer operates like a NOT gate and when the control line is low the output is disconnected from the output and high impedance is seen at the output. Tri-state buffers are used to disconnect the outputs of devices which are connected or share a common output line.

318 Question No: 23 ( Marks: 5 ) Explain the Operation of Odd-Parity Generator Circuit with the help of timing diagram Answer:- (Page 196) The timing diagram shows the operation of the Odd-Parity generator circuit. The A, B, C and D timing diagrams represent the changing 4-bit data values. During time interval t0 the 4-bit data value is 0000, during time interval t1, the data value changes to Similarly during time intervals t2, t3, t4 up to t8 the data values change to 0010, 0011, 0100 and 1000 respectively. During interval t0 the output of the two XOR gates is 0 and 0, therefore the output of the XNOR gate is 1. At interval t1, the outputs of the two XOR gates is 1 and 0, therefore the output of the XNOR gate is 0. The output P can similarly be traced for intervals t2 to t8. MIDTERM EXAMINATION 2010 Question No: 17 ( Marks: 2 ) For what values of A, B, C and D, value of the expression given below will be logic 1. Explain at least one combination. A. B ABCD... Answer:- The Multiplexers are used to route the contents of any two registers to the ALU inputs. Many Audio signals in telephone network. Computer use Dynamic Memory addressing using same address line for row and column addressing to access data. Question No: 18 ( Marks: 2 ) Provide some of the inputs for which the adjacent 1s detector circuit have active high output? Answer:- (Page 123) The Adjacent 1s Detector accepts 4-bit inputs. If two adjacent 1s are detected in the input, the output is set to high. input combinations will be 0011, 0110, 0111, 1011, 1100, 1101, 1110 and 1111 The output function is a 1.

319 Question No: 19 ( Marks: 2 ) Draw the Truth-Table of NOR based S-R Latch Answer:- (Page 222) Question No: 20 ( Marks: 3 ) For a two bit comparator circuit specify the inputs for which A > B Answer:- (Page 109) The output A<B is set to 1 when the input combinations are 00 01, 00 10, 00 11, 01 10, and Question No: 21 ( Marks: 3 ) Draw the circuit diagram of NOR based S-R Latch? Answer:- (Page 220) Question No: 22 ( Marks: 5 ) One of the ABEL entry methods uses logic equations; explain it with at least a single example. Answer: (Page 201) ABEL however is case sensitive, thus variable A is treated separately from variable a. All ABEL equations must end with ;. Examples:- (a) (b)

320 Solution (a)x = A&!B & C #!A &!B &!C # A & B #!B & C; (b)y = (!A # B #!C #D) & (A # B # C); Question No: 23 ( Marks: 5 ) Explain Carry propagation in Parallel binary adder? Answer: (Page 137) Parallel Binary Adders can be implemented by connecting the required number of 1-bit full adders in a configuration represented in figure However, there is a practical limitation to the number of 1-bit Full- Adders that can be connected in parallel. In the 4-bit Parallel Adder, the Most significant bit adder which adds bits A3, B3 and the Carry bit C3, cannot proceed until it receives the Carry from the next least significant 1-bit adder which adds bits A2, B2. The A2, B2 bit adder cannot precede unless it receives the carry input C2 from the A1, B1 adder. The A1, B1 adder in tern depends on A0, B0 adder to provide the carry input. Thus the carry has to propagate through each Full-adder before it reaches the last or most significant full adder. MIDTERM EXAMINATION 2010 "Write the uses of multiplexer". 2 marks Answer: (Page 167) Multiplexer is a digital switch that has several inputs and a single output. Multiplexers are also known as Data Selectors. The main use of the Multiplexer is to select data from multiple sources and to route it to a single Destination "Write any two advantages of Boolean expressions". 2 marks Answer: (Page 71) Boolean expressions which represent Boolean functions help in two ways. The function and operation of a Logic Circuit can be determined by Boolean expressions without implementing the Logic Circuit. Secondly, Logic circuits can be very large and complex. Such large circuits having many gates can be simplified and implemented using fewer gates. "Draw the diagram of odd parity generator circuit". 2 marks Answer: (Page 132)

321 "What does a 8-bit adder/subtracter circuit do"? 3 marks Answer: (Page 146) The Add/Subtract function select input are tied together. The Carry In of the 1st 4-bit Adder circuit is connected to the Add/Subtract function select input. The Carry Out of the 1st 4-bit Adder circuit is connected to the Carry In of the 2 nd 4-bit Adder circuit. "Draw the function table of 3 to 8 decoder". 3 marks Answer: (Page 160) Inputs Outputs G1 G2A G2B C B A Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 0 X X X X X X 1 X X X X X X 1 X X X "Describe 16 bit ALU". 5 marks Answer: (Page 151) The inputs A, B and the output F of the four, 4-bit ALUs 0, 1, 2 and 3 are connected to appropriate bits of the 16-bit inputs A, B and output F respectively. Thus bits A(0-3), B(0-3)and F(0-3) are connected to inputs and output of ALU0, bits A(4-7), B(4-7) and F(4-7) are connected to inputs and output of ALU1, bits A(8-11), B(8-11) and F(8-11) are connected to inputs and output of ALU2 and bits A(12-15), B(12-15) and F(12-15) are connected to inputs and output of ALU3. The Group-Carry Generate and Propagate outputs of the four ALUs are connected to the inputs of Look-Ahead Carry generator 74X182 respectively. The Carry outputs C1, C2 and C3 from the Look-Ahead Carry generator circuit are generated after a gate delay of 2 and are connected to the Carry in pins of ALUS 1, 2 and 3 respectively. "Describe in your own words about latches". Answer: (repeated) 5 marks MIDTERM EXAMINATION 2009 Question No: 17 ( Marks: 1 )

322 Briefly state the basic principle of Repeated Division-by-2 method. Answer: (Page 17) Repeated Division-by-2 method allows decimal numbers of any magnitude to be converted into binary. Question No: 18 ( Marks: 1 ) Briefly state the basic principle of Repeated Multiplication-by-2 Method. Answer: Page 17 Repeated Multiplication-by-2 method allows decimal fractions of any magnitude to be easily converted into binary. Question No: 19 ( Marks: 2 ) Draw the circuit diagram of a Tri-State buffer. Answer: (Repeated) Question No: 20 ( Marks: 3 ) Add -13 and +7 by converting them in binary system your result must be in binary. Question No: 21 ( Marks: 5 ) Explain Sum of Weights method with example for Octal to Decimal conversion Answer: (Page 14) (Page 33) In the Sum-of-Weights method an extended expression is written in terms of the Binary Base Number 2 and the weights of the Binary number to be converted. The weights correspond to each of the binary bits which are multiplied by the corresponding binary value.binary bits having the value 0 do not contribute any value towards the final sum expression. An Octal number can be directly converted into Decimal by using the sum of weights method. The conversion steps using the Sum-of-Weights method are shown Octal number 4 x x x x 80 Writing the number in an expression (4 x 512) + (0 x 64) + (3 x 8) + (3 x 1) Summing the Weights 2075 Decimal equivalent Question No: 22 ( Marks: 10 ) Explain the Implementation of an Odd-Parity Generator Circuit i.e by drawing function table, maping it to K-map and then simplifying the expression. Question No: 17 ( Marks: 1 ) MIDTERM EXAMINATION 2009 Briefly state the basic principle of Repeated Multiplication-by-2 Method. Answer: (Repeated) Question No: 18 ( Marks: 1 )

323 How standard Boolean expressions can be converted into truth table format. Answer: (Page 87) All standard Boolean expressions can be easily converted into truth table format using binary values for each term in the expression. Standard SOP or POS expressions can also be determined from a truth table. Question No: 19 ( Marks: 2 ) What will be the out put of the diagram given below Question No: 20 ( Marks: 3 ) When an Input (source) file is created in ABEL a module is created which has three sections. Name These three sections. Answer: (Page 205) 1. Declarations 2. Logic Descriptions 3. Test Vectors Question No: 21 ( Marks: 5 ) Explain AND Gate and some of its uses Answer: (Page 40) The AND Gate performs a logical multiplication function. An AND Gate has multiple inputs and a single output. Most commonly used AND Gates are two input AND gates. An important use of an AND gate in addition to the multiplication operation is its use to disable or enable a device. Counter device counts from 0 to 100. The counter device increments its current count value to the next when it receives a pulse at its clock input. Question No: 22 ( Marks: 10 ) Write down different situations where we need the sequential circuits. Answer: (Page 217) This type of system uses storage elements called flip-flops that are employed to change their binary value only at discrete instants of time. Synchronous sequential circuits use logic gates and flip-flop storage devices. Sequential circuits have a clock signal as one of their inputs. All state transitions in such circuits occur only when the clock value is either 0 or 1 or happen at the rising or falling edges of the clock depending on the type of memory elements used in the circuit. MIDTERM EXAMINATION 2009 Question No: 17 ( Marks: 1 ) How can a PLD be programmed? Answer: (Page 194) PLDs are programmed with the help of computer which runs the programming software. The computer is

324 connected to a programmer socket in which the PLD is inserted for programming. PLDs can also be programmed when they are installed on a circuit board Question No: 18 ( Marks: 1 ) How many input and output bits do a Half-Adder contain? Answer: (Page 134): The Half-Adder has a 2 input bits and 2 output bits. Question No: 19 ( Marks: 2 ) Explain the difference between 1-to-4 Demultiplexer 2-to-4 Binary Decoder? Answer: (Page 178) The circuit of the 1-to-4 Demultiplexer is similar to the 2-to-4 Binary Decoder. The only difference between the two is the addition of the Data Input line, which is used as enable line in the 2-to-4 Decoder circuit. Question No: 20 ( Marks: 3 ) Name the three declarations that are included in declaration section of the module that is created when an Input (source) file is created in ABEL. Answer: (repeated) Question No: 21 ( Marks: 5 ) Explain with example how noise affects Operation of a CMOS AND Gate circuit. Answer: (Page 123) Two CMOS 5 volt series AND gates are connected together. Figure 7.3 The first AND gate has both its inputs connected to logic high, therefore the output of the gate is guaranteed to be logic high. The logic high voltage output of the first AND gate is assumed to be 4.6 volts well within the valid VOH range of volts. Assume the same noise signal (as described earlier) is added to the output signal of the first AND gate. Question No: 22 ( Marks: 10 ) Explain the SOP based implementation of the Adjacent 1s Detector Circuit Answer: (Page 123) The Adjacent 1s Detector accepts 4-bit inputs. If two adjacent 1s are detected in the input, the output is set to high. The operation of the Adjacent 1s Detector is represented by the function table. Table In the function table, for the input combinations 0011, 0110, 0111, 1011, 1100, 1101, 1110 and 1111 the output function is a 1. Implementing the circuit directly from the function table based on the SOP form requires 8 AND gates for the 8 product terms (minterms) with an 8-input OR gate. Figure The total gate count is One 8 input OR gate Eight 4 input AND gates Ten NOT gates The expression can be simplified using a Karnaugh map, figure 13.4, and then the simplified expression can be implemented to reduce the gate count. The simplified expression isab + CD +BC. The circuit implemented using the expression AB + CD +BC has reduced to 3 input OR gate and 2 input AND gates. Figure 13.5

325 MIDTERM EXAMINATION 2009 Question No: 17 ( Marks: 1 ) Which device performs an operation which is the opposite of the Decoder function? Answer: (Page 163) An Encoder functional device performs an operation which is the opposite of the Decoder function. Question No: 18 ( Marks: 1 ) Name any two modes in which PALs are programmed. Answer: (Page 199) The three modes in which PALs are programmed are Simple Complex Registered Question No: 19 ( Marks: 2 ) Explain Combinational Function Devices? Answer: (Page 133) Digital circuits are formed by the combination of Logic Gates. Xor, Xnor, NAND, NOR are combinational function devices. Question No: 20 ( Marks: 3 ) Differentiate between hexadecimal and octal number system Answer: Octa decimal use Base 8 whereas Hexa decimal use Base 16 Question No: 21 ( Marks: 5 ) Explain Sum-of-Weights Method for Hexadecimal to Decimal Conversion with at least one example? Answer: The hexadecimal (Hex) numbering system provides even shorter notation than octal. Hexadecimal uses a base of 16. It employs 16 digits: number 0 through 9, and letters A through F, with A through F substituted for numbers 10 to 15, respectively, Hexadecimal numbers can be expressed as their decimal equivalents by using the sum of weights method, as shown in the following example: Weight Hex. Number 1 B 7 7 x 16 0 = 7 x 1 = 7 11 x 16 1 = 11x 16 = x 16 2 = 1 x 256 = 256 Sum of products

326 Like octal numbers, hexadecimal numbers can easily be converted to binary or vise versa. Conversion is accomplished by writing the 4-bit binary equivalent of the hex digit for each position, as illustrated in the following example: Hex. Number 1 B Binary number Hexadecimal Binary Decimal A B C D E F Question No: 22 ( Marks: 10 ) Draw the function table of two-bit comparator circuit, map it to K-Map and derive the expression for (A > B) Answer: (Page 109) Input Output A 1 A 0 B 1 B 0 A>B A=B A<B

327

328 vustudypakpattan.blogspot.com CS302- Digital Logic Design SOLVED SUBJECTIVE FROM FINAL TERM PAPERS Latest Subjective FINAL TERM EXAMINATION Fall In the highest frequency component in an analog signal is 20 KHz, what is the minimum sample frequency (Marks 2) Answer:- Click here for detail In the highest frequency component in an analog signal is 20 KHz, and minimum sample frequency is 40 KHz. 2. Write down the ABEL symbols that are used for NOT, AND, OR and XOR operations. (Marks 2) Answer:- Page 201 Logic ABEL Symbol Operation NOT! AND & OR # XOR $ 3. Differentiate between Moore machine and Mealy machine. (Marks 2) Answer:- Page 318 The Sequential circuit whose output depends on the current state and the input is known as Mealy Machine. Sequential circuit whose output is determined by the current state only is known as Moore Machine. 4. How many bytes will be there in 16K x 8 memory? (Marks 2) Answer:- Page 395 A 16 K x 8 memory, stores 16K bytes or 16 x 1024 = bytes or bits. 1. How many address bits are required for a 2048-bit memory organized as a 256 x 8 memory? (Marks 3) 2. Explain Rotate Right Operation of shift register with the help of Diagram. (Marks 3) Answer:- Page 354 The serial output of the register is connected to the serial input of the register. By applying clock pulses data is shifted right. The data shifted out of the serial out pin at the right hand side is re-circulated back into the shift register input at the left hand side. Thus the data is rotated right within the register. Solved By Muhammad Khan

329 vustudypakpattan.blogspot.com 3. Difference between State Assignment and State Reduction process. (Marks 3) Answer:- (Page 332 & 335) 1. In state Reduction A state diagram show the sequence of current and next states through which the state machine sequences while in State Assignment Each state in a sequential circuit is identified by a unique combination of binary bits. 2. In state Reduction the transition from a current state to the next state is determined by current state and the inputs while in State Assignment the states can be selected to allow minimum bit changes when changing from one state to the other. 3. State Assignment results in simpler combinational circuits that determine the next state while Reduction in the number of state results in fewer flip-flops and a simpler circuit. 4. Explain Full-Adder Sum and Carry out Boolean Expression. (Marks 3) Answer:- (Page 135) Full-Adder Sum & Carry Out Boolean Expressions The Sum and Carry Out expressions of the Full-Adder can be determined from the function table. The Full-Adder Sum and Carry Out outputs are defined by the expressions Sum = ABC + ABC + ABC + ABC Sum = A(BC + BC) + A(BC +BC) Sum = A(B C) + A(B C) Sum = A B C CarryOut = ABC + ABC + ABC + ABC CarryOut = C(AB + AB) + AB(C + C) CarryOut = C(A B) + AB 1. Explain Latches in your own words. (Marks 5) Answer:- (Page 218) A latch is a temporary storage device that has two stable states. A latch output can change from one state to the other by applying appropriate inputs. A latch normally has two inputs, the binary input combinations at the latch input allows the latch to change its state. A latch has two outputs Q and its complement Q(bar). The latch is said to be in logic high state when Q=1 and Q(bar)=0 and it is in the logic low state when Q=0 and Q(bar)=1. When the latch is set to a certain state it retains its state unless the inputs are changed to set the latch to a new state. Thus a latch is a memory element which is able to retain the information stored in it. Solved By Muhammad Khan

330 vustudypakpattan.blogspot.com 2. Differentiate between synchronous and asynchronous memory. (Marks 5) Answer:- (Page 406) In the Asynchronous memory the various input signals are asynchronous and are not tied to the clock, whereas in the Synchronous memory all the inputs are synchronized with respect to the clock and are latched into their various registers on an active clock pulse edge. 4. Draw state diagram of Moore machine. (Marks 5) Answer:- (Page 338) FINAL TERM EXAMINATION Spring 2011 Question No: ( Marks: 2 ) Write down at least two applications of a shiftregister. Answer:- (Page 356) The two applications of the shift registers are 1. Serial to Parallel converter 2. Keyboard encoder Question No: ( Marks: 2 ) Explain memory expansion process. Answer:- (Page 430) Computer and Digital systems have the capability to allow RAM memory to be expanded as the needed arises by inserting extra memory in dedicated memory sockets on the computer motherboard. Solved By Muhammad Khan

331 Question No: ( Marks: 2 ) Draw the NOR based S-R Latch Answer:- (Page 220) vustudypakpattan.blogspot.com Question No: ( Marks: 3 ) Explain Rotate Left Right Operation with the help of diagram. Answer:- (Page 354) Question No: ( Marks: 3 ) You are given the block diagram of 74HC190 integrated circuit up/down counter, explain the function of labeled inputs/outputs. Answer:-(Page 295) Solved By Muhammad Khan

332 vustudypakpattan.blogspot.com 1. Active-low CTEN counter enable input 2. D/U the count down/up input. When the input is set to logic 1, the counter counts down and when the input is set to logic 0, the counter counts up 3. The MAX/MIN output that is set to high when the terminal count 1001 is reached when counting up or when the terminal count 0000 is reached when counting down. The MAX/MIN output is logic high for one complete cycle when a terminal count is reached. Question No: ( Marks: 5 ) Explain Memory Select or Enable Signals Answer:- (Page 397) In a computer system there are more than one memory chips to store program information. At any particular instant a read or write operation is carried out on a single addressable location. The unique location can only be accessed in one of the several memory chips, thus a single memory chip has to be selected before a read or write operation can be carried out. All memory chips have a chip enable or chip select signal which has to be activated before the memory can be accessed. Question No: ( Marks: 5 ) Explain the implementation of First In First Out (FIFO) Memory by using RAM. Answer:- (Page 427) Shift register based FIFO memory is used in digital systems designed for specific applications where small sized buffers are used to allow transfer of data between two devices operating at different data rates. Such digital systems either have no RAM or very small RAM for storing variables. Computers implement FIFO memory by reserving a part of their RAM memory for use as buffers. The Keyboard buffer for example is implemented by reserving a part of the RAM. When RAM is used as FIFO memory, two registers are used to point to the FIFO Buffer Out and Buffer In respectively. The two registers hold the addresses of the locations of the Buffer Out and Buffer In respectively, which are updated as new data is written into the buffer and previous data is read out from the FIFO buffer. Implementation of the FIFO buffer in RAM is usually takes the form of a circular buffer. Question No: ( Marks: 5 ) Explain application of demultiplexer Answer:- (Page 178) Demultiplexer is used to connect a single source to multiple destinations. One use of the Demultiplexer is at the output of the ALU circuit. The output of the ALU has to be stored in one of the multiple registers or storage units. The Data input of the Demultiplexer is connected to the output of the ALU. Each output of the Demultiplexer is connected to each of the multiple registers. By selecting the appropriate output data from the ALU is routed to the appropriate register for storage. The second use of the Demultiplexer is the reconstruction of Parallel Data from the incoming serial data stream. Serial data arrives at the Data input of the Demultiplexer at fixed time intervals. A counter attached to the Select inputs of the Demultiplexer routes the incoming serial bits to successive outputs where each bit is stored. When all the bits have been stored, data can be read out in parallel. Solved By Muhammad Khan

333 vustudypakpattan.blogspot.com FINAL TERM EXAMINATION Spring 2011 Question No: 27 ( Marks: 2 ) 1: Explain the erase operation in context of Flash Memory. Answer:- (Page 421) During the erase operation charge is removed from the memory cell. A sufficiently large positive voltage is applied at the source with respect to the control gate. The voltage applied across the control gate and source is opposite to the voltage applied during programming. If charges are present on the gate, the positive voltage supply at the source attracts the electrons depleting the gate. A FLASH memory is erased prior to programming. 2: How can a serial in/parallel out register be used as a serial in/serial out register? 3: Explain the next-state table with the help of a table for any sequential circuit? Answer:- (Page 306) Once the state diagram of the sequential circuit is defined, a Next-State Table is derived which lists each present state and the corresponding next state. The next state is the state to which the sequential circuit switches when a clock transition occurs. Present State Next State Q2 Q1 Q0 Q2 Q1 Q : What is meant by Non-Monotonicity of Digital to Analog converter? Answer:- (Page 460) if the D/A converter outputs a lower voltage than its preceding output voltage the converter is said to exhibit non-monotonic behavior. 5: Two state assignments are given in the table below. Identify which state assignment is best and why? Answer:- States State assignment 1 State assignment 2 A B C D Solved By Muhammad Khan

334 vustudypakpattan.blogspot.com 6: Write down at least two functions of a register. Answer:- (Page 306) Technically, a register performs two basic functions. It stores data and it moves or shifts data. The shifting of data involves shifting of bits from one flip-flop to the other within the register or moving data in and out of the register. The shift operation of the binary data is carried out by applying clock signals. Several different kinds of shift operations can be identified. 7: You are given the Next-state table of a Moore machine, using this information draw the state diagram of the machine. Present State Next State Q2 Q1 Q0 Q2 Q1 Q Answer:-(Page 338) FINAL TERM EXAMINATION Spring 2011 Solved By Muhammad Khan

335 vustudypakpattan.blogspot.com QNo.1 Define the term "Variable" in context of Boolean algebra. Answer:- (Page 71) A variable is a symbol usually an uppercase letter used to represent a logical quantity. A variable can have a 0 or 1 value. Solved By Muhammad Khan

336 vustudypakpattan.blogspot.com Q No.2 A general sequential circuit consists of a combinational circuit and memory elements. How this Memory element is implemented. Answer:- (Page 318) A general Sequential circuit consists of a combinational circuit and a memory element. The memory element is made of a set of n flip-flops all connected to a a common clock. The n flip flops store 2n states. The flip-flops change their current state to the next state on each clock transition. The next state is determined by the current state and the external input. The output of the State Machine is determined by the current state and external input. The inputs to the memory which allow the memory to change its state on a clock transition are known as excitation inputs or excitation variables. Q No.3 what is meant by Monotonicity of Digital to Analog converter? Answer:- (Page 460) The output of the D/A converter should give an increasing analogue voltage output when the binary input is varied between its minimum and maximum values. Q No.4 Explain Programmable Logic Devices? Answer:-(Page 179) Programmable Logic Devices are used in many applications to replace the Logic gates and MSI chips. PLDs save circuit space and reduce and save the cost of components in a Digital Circuit. PLDS consists of Arrays of AND gates and OR gates that can be programmed to perform specific functions. Q No.5 How many clock pulses are required to enter a byte of data serially into an 8-bit shift register? 2 Answer:- 8 clock pulses are required to enter a byte of data serially into an 8- bit shift register Q No. 6 How can calculate the frequency of an unknown signal? Answer:-(Page 301) The frequency of the unknown signal can be calculated by counting the number of clock pulses of the unknown signal and dividing the count number by the time interval in which the clock pulses are counted, Q No. 7 Write the drawbacks of 16-bit ALU without look-ahead carry circuit? Q No. 8 How many address bit are required for a 2048-bit memory organized as a 256*8 memory? Q No. 9 Differentiates between Memory capacity and Memory Density? Answer:- (Page 395) Each memory array has a maximum capacity to store information in the form of bits. Memory density on the other hand specifies the number of bits stored per unit area. More the number of bits stored in a unit area more dense the memory, that is, more bits are stored in less space. Q No. 10. Explain Memory Select or Enable signal? Answer:- (Page 397) In a computer system there are more than one memory chips to store program information. At any particular instant a read or write operation is carried out on a single addressable location. The unique location can only be accessed in one of the several memory chips, thus a single memory chip has to be selected before a read or write operation can be carried out. All memory chips have a chip enable or chip select signal which has to be activated before the memory can be accessed. Solved By Muhammad Khan

337 vustudypakpattan.blogspot.com Q No 11. Explain state Assignment Process. Answer:-(Page 335) Each state in a sequential circuit is identified by a unique combination of binary bits. Unless the output of the sequential is directly taken form the flip-flop outputs such as counters, the states can be selected to allow minimum bit changes when changing from one state to the other. Keeping the bits changes to minimum when changing from one state to the next, results in simpler combinational circuits that determine the next state. Q No 12. Briefly Explain Next-state table with the help of any sequential circuit.5 Answer:- Repeated FINAL TERM EXAMINATION Spring In the highest frequency component in an analog signal is 20 KHz, what is the minimum sample frequency Answer:- Repeated 2. How many bytes will be there in 16K x 8 memory? Answer:- Repeated 3. Convert the hexadecimal number 7AB1 into binary numbers. Write down all the steps. Answer:- (Page 27) Replacing each Hexadecimal digit by its 4-bit binary equivalent 7= 0111, A= 1010, B=1011, 1= 0001 So, 7AB1 = Explain grouping of cells in k-map. 3 Answer:- (Page 90) Groups are formed on the basis of 1s (Minterms) or 0s (maxterms). A group is selected to have maximum number of cells of Minterms or Maxterms, keeping in view that the size of the group should be a power of 2. The idea is to form minimal number of largest groups that uniquely cover all the cells, thereby ensuring that all minterms or maxterms are included. 5. Provide some of guidelines for selection of state assignment. 3 Answer:-(Page 337) Generally, the selection of State Assignment is based on the following guidelines. Choose an initial coded state into which the state machine (sequential circuit) can easily be forced to reset (000 or 111) Minimize the State Variables that change on each transition Maximize the number of state variables that don't change in a group of related states If there are unused states, then choose the best state variable combinations to achieve the first three goals. Solved By Muhammad Khan

338 vustudypakpattan.blogspot.com 6. Discuss at least one difference in Johnson and ring Counter 3 Answer:-(Page 355) The Ring Counter is similar to the Johnson counter, except that the Q output of the last flip-flop of the shift register is connected to the data input of the first flip-flop of the shift register. 7. Three types of error while converting Analogue signal into digital. 3 Answer:-(Page 354) 1. Missing Code 2. Incorrect Code 3. Offset Error 8. Explain memory read operation with help of example 5 Answer:- (page 397) Memory Read operation is carried out by first selecting the memory chip by activating the Memory Select signal. The Read signal is asserted to configure the memory circuitry for reading data from the memory. An address (100) is applied on the Address Lines. The internal address decoder of the memory decodes the address and selects one unique row from which data is read. Figure The address of the location in the memory from which data is to be read is supplied by the microprocessor. The microprocessor stores the address in its address buffer. The data read from the memory is stored in a data buffer inside the microprocessor. In the diagram shown, a microprocessor places an address 100 on its external address bus connected to the address lines of the memory. The internal address decoder of the memory decodes the address 100 and activates a row select line which selects the row location 4. The data ( ) at the location is read from the memory and placed on the data bus where it is latched by the microprocessor and stored in its data buffer. 9. Explain flesh analogue to digital converter 5 Answer:- (Page 447) The Flash A/D converter is based on a resistor potential divider, where multiple resistors of identical value form a voltage divider. A reference voltage is applied at one end of the potential divider which divides the voltage equally across all the resistors. The input analogue voltage is applied at the non-inverting inputs of a set of Op- Amp based comparators. The inverting input of each comparator is connected to the resistive voltage divider which provides reference voltages for all the comparators. If the input voltage is larger than the reference voltage the output of the comparator is logic high otherwise it is logic low. The outputs of all the comparators are connected to the input of a priority encoder which converts the comparator outputs to a binary coded Solved By Muhammad Khan

339 equivalent value. vustudypakpattan.blogspot.com Solved By Muhammad Khan

340 vustudypakpattan.blogspot.com 10. Briefly explain address multiplexing in DRAM. 5 Answer:- (Page 410) DRAM chips use address multiplexing to reduce the number of address lines by half. The address required to select a memory location is split into row and column addresses. To access a DRAM location for reading or writing of information the row address is first applied at the address lines. The row address is latched by the Row Address Latch of the DRAM memory chip. The column address is applied next at the same address lines. The column address is latched by the Column Address Latch. Two signals RAS and CAS are used as strobe signals to control the Row Address and Column Address latches respectively. The external address lines are multiplexed as the same set of address lines are used to apply the row address and the column address at different time instances. The outputs of the Row Address Latch and the Column Address Latch are connected to the Row and Column Decoders which select a single row and column line selecting the storage cell to be accessed. FINAL TERM EXAMINATION Spring 2011 Explain READ Write signal used for memory. 03 Answer:- (Page 396) Read/Write signals are required to configure the memory for read and write operation. Memory chips have a single Read/Write signal. When the signal is set to high it allows data to be read from the memory. When the signal is set to low data is written into the memory. Some memory chips have two separate Read and Write signals. The read and write signals are separately asserted to control the Read and Write operation. What is difference between PROM and ROM. 03 Answer:- Click here for detail The difference between a PROM and a ROM (read-only memory) is that a PROM is manufactured as blank memory, whereas a ROM is programmed during the manufacturing process. To write data onto a PROM chip, you need a special device called a PROM programmer or PROM burner. The process of programming a PROM is sometimes called burning the PROM. Making decade counter by cascading two 74HC What is difference between memory capacity and memory density? 05 Answer:- Repeated Describe Flash Analogue to Digital converter. 05 Answer:- Repeated Solved By Muhammad Khan

341 vustudypakpattan.blogspot.com Explain don s care condition. Answer:- (Page 96) Function Tables represent the function by listing all the possible inputs and marking the corresponding outputs with 1s and 0s. Thus a circuit having four inputs can be described by a 4-variable function table having 16 possible input combinations. For each of the 16 possible input conditions the corresponding output bits are marked as 1s and 0s depending upon the minterms or maxterms. It is however, possible that out of the 16 possible input combinations, three input combinations never occur. Since these three input combinations never occur so should their corresponding outputs be marked as 0s or 1s? Since these inputs never care therefore we don't need to worry about the output of these input states. They are considered to be don't care conditions. FINAL TERM EXAMINATION 2011 Question#1 Give advantages of Counters are available in integrated circuits? (Marks 2) Question #2 Successive approximation counter have a fixed consecutive time Is tarha ka qs tha (Marks 2) Question #4 How many states in 8-bit Johnson counter? (Marks 2) Answer:-(Page 354) The sequence of states that are implemented by a n-bit Johnson counter are 2n So, 8 bit Johnson counter has 2*8 = 16 states Question #5 Diff b/w truth table and next state table (Marks 3) Question #6 How hexadecimal number is converted into binary number give one example? (Marks 3) Answer:-(Page 28) Converting from Hexadecimal back to binary is also very simple. Each digit of the Hexadecimal number is replaced by an equivalent binary string of 4-bits. FD13 Hexadecimal Number Replacing each Hexadecimal digit by its 4-bit binary equivalent Question #7 Diff b/w ROM and PROM? (Marks 3) Answer:- Repeat Question #8 How we can implement full adder from two half adder? (Marks 3) Answer:- Repeat Solved By Muhammad Khan

342 Question #9 Make State diagram? Answer:- Repeat vustudypakpattan.blogspot.com Question #10 Explain FRGA? (Marks 5) Answer:- (Page 437) Programmable Logic Devices are based on a programmable AND-OR gate array which are programmed to implement any function in the SOP form. The output of the AND-OR gate array can be directly used as a combinational circuit output. Provision is there to connect the output of the AND-OR gate array to a D-flip-flop for Sequential circuit operation. An FPGA is a more flexible device than PLDs as instead of a single AND-OR gate array, an FPGA device contains multiple logic blocks that can be individually programmed to perform different functions. Each Logic Block is connected to other blocks through row and column interconnects that can be programmed to connect any Logic block to another. Question #11 (Marks 5) Differentiate b/w memory density and memory capacity? Answer:- Repeated FINAL TERM EXAMINATION Spring 2010 Question No: 27 (Mark s: 2) Define quantization process. Answer:- (Page 444) The process of converting the analogue signal into a digital representation (code) is known as quantization Question No: 28 (Marks: 2) Explain the difference between 1-to-4 Demultiplexer and 2-to-4 Binary Decoder? Answer:- (Page 178) The only difference between the two is the addition of the Data Input line, which is used as enable line in the 2-to-4 Decoder circuit figure Assuming the select inputs I1 and I0 are set to 1 and 0 respectively. The O2 output is set to 1 if the Data input is 1 or it is set to 0 if the Data input is 0. Question No: 29 (Marks: 2) A general Sequential circuit consists of a combinational circuit and a memory element. How this memory element is implemented Answer:- Repeated Question No: 30 (Marks: 2) Suppose a 2 bit up-counter, having states "A, B, C, D". Write down GOTO statements to show how present states change to next states. Solved By Muhammad Khan

343 vustudypakpattan.blogspot.com Question No: 31 (Marks: 3) Name three Operations that can be performed on FLASH Memory Answer:- (Page 420) FLASH Memory operations are classified into Programming Operation Read Operation Erase Operation Question No: 32 (Marks: 3) Explain Rotate Right Operation of shift register with the help of diagram. Answer:- Repeated Question No: 33 ( Marks: 3 ) You are given the block diagram of 74HC190 integrated circuit up/down counter, explain the function of labeled inputs/outputs. Answer:- Repeated Question No: 34 ( Marks: 5 ) Draw the state diagram of 3-bit up-down counter, use an external input X, when X sets to logic 1, the counter counts downwards, otherwise upward. Question No: 35 (Marks: 5) Differentiate between synchronous and asynchronous RAM. Answer:- (Page 406) Synchronous RAM is very similar to the Asynchronous RAM, in terms of the memory array, the address decoders, read/write and enable inputs. In the Asynchronous memory the various input signals are asynchronous and are not tied to the clock, whereas in the Synchronous memory all the inputs are synchronized with respect to the clock and are latched into their various registers on an active clock pulse edge. Question No: 36 ( Marks: 5 ) Explain Memory Select or Enable Signals Answer:- Repeated FINAL TERM EXAMINATION Spring 2010 Solved By Muhammad Khan

344 vustudypakpattan.blogspot.com Question No: 27 ( Marks: 2 ) Draw the Truth-Table of NOR based S-R Latch Answer:- (Page 222) Input Output S R Qt Qt invalid Table 22.3 Truth-Table of NOR based S-R Latch Question No: 28 ( Marks: 2 ) Two state assignments are given in the table below. Identify which state assignment is best and why? States State assignment 1 State assignment 2 A B C D Question No: 29 ( Marks: 2) Write down at least two functions of a register. Answer:- Repeat Question No: 30 ( Marks: 2 ) Define quantization process. Answer:- Repeat Question No: 31 ( Marks: 3 ) How can we calculate the frequency of an unknown signal? Answer:- Repeat Question No: 32 ( Marks: 3 ) Solved By Muhammad Khan

345 vustudypakpattan.blogspot.com Given the following statement used in PLD programming: Y PIN 23 ISTYPE com ; Explain what does this statement mean? Answer:- (Page 360) The statement describes Y available at output pins 23. The Y variable is a 'Combinational' output available directly from the AND-OR gate array output. The active-low or active-high output of the Registered Mode can also be specified in the declaration statement Question No: 33 ( Marks: 3 ) Explain dynamic RAM in your own words. Answer:- Click here for detail Dynamic random-access memory (DRAM) is a type of random-access memory that stores each bit of data in a separate capacitor within an integrated circuit. The capacitor can be either charged or discharged; these two states are taken to represent the two values of a bit, conventionally called 0 and 1. Since capacitors leak charge, the information eventually fades unless the capacitor charge is refreshed periodically. Because of this refresh requirement, it is a dynamic memory as opposed to SRAM and other static memory. Question No: 34 ( Marks: 5 ) You are given the Next-state table of a Moore machine, using this information draw the state diagram of the Present State Next State Q2 Q1 Q0 Q2 Q1 Q machine. Answer:- repeat Question No: 35 ( Marks: 5 ) Explain Memory Select or Enable Signals Answer:- repeat Question No: 36 ( Marks: 5 ) Performance characteristics of D/A converters are determined by five parameters. Name them. Answer:- (Page 460) Solved By Muhammad Khan

346 vustudypakpattan.blogspot.com Performances characteristics of D/A converters are determined by five parameters are: 1. Resolution 2. Linearity 3. Monotonicity 4. Setting time 5. Accuracy FINAL TERM EXAMINATION Solved By Muhammad Khan

347 vustudypakpattan.blogspot.com Spring 2010 Question No: 27 (Marks: 2) Explain the erase operation in context of Flash Memory. Answer:- repeat Question No: 28 (Marks: 2) Explain the difference between 1-to-4 Demultiplexer and 2-to-4 Binary Decoder? Answer:- repeat Question No: 29 (Marks: 2) Some of the counters (e.g. 74HC163) are called pre-set counters. why? Answer:- Click here for detail 74HC163) are called pre-set counters because A counter set in advance to stop or produce output once a specific count has been reached. Question No: 30 (Marks: 2) How many bytes will be there in 32 K x 8 memory? Answer:- (Page 395) A 32 K x 4 memory stores 32K nibbles or 32 x 1024 = nibbles Question No: 31 (Marks: 3) Differentiate between truth table and next-state table Question No: 32 (Marks: 3) Name the three types of errors Analogue to Digital converters exhibit during their conversion operation. Answer:- repeat Question No: 33 (Marks: 3) How can a serial in/parallel out register be used as a serial in/serial out register? Question No: 34 (Marks: 5) Explain the implementation of First In First out (FIFO) Memory by using RAM. Answer:- repeat Question No: 35 (Marks: 5) Explain memory read operation with the help of an example Answer:- repeat Question No: 36 (Marks: 5) Explain the next-state table with the help of a table for any sequential circuit Answer:- repeat Solved By Muhammad Khan

348 VUClub.net FINALTERM EXAMINATION SEMESTER FALL 2004 CS302-Digital Logic Design (S1) Total Marks:70 Duration:120 Min Student ID / Login ID Name PVC Name / Code Date Maximum Time Allowed: (2 Hours) Please read the following instructions carefully before attempting any of the questions: 1. Attempt all questions. 2. Calculators are NOT allowed. 3. Do not ask any questions about the contents of this examination from anyone. a. If you think that there is something wrong with any of the questions, attempt it to the best of your understanding. b. If you believe that some essential piece of information is missing, make an appropriate assumption and use it to solve the problem. 4. Circuit Diagrams, Equations and Truth Tables should be clear. Write down all the steps in Subjective Questions. Marks will be deducted for missing steps. **WARNING: Please note that Virtual University takes serious note of unfair means. Anyone found involved in cheating will get an `F` grade in this course. 1

349 For Teacher s use only Question Q1 Q2 Q3 Q4 Q5 Q6 Q7 Total Marks Question No: 1 Marks: 8+8 a) Convert each of the following POS expression to minimum SOP expression using a Karnaugh Map. ( A + B)( A+ B+ C)( B+ C+ D)( A+ B+ C+ D) b) Convert the decimal numbers 78 and 34 into Octal. Using octal addition, add the two numbers and convert the octal result back into decimal and verify the answer. Question No: 2 Marks: 8 Draw the timing diagram of Q A, Q A, Q B and Q B. Assume the Positive edge triggering. 2

350 Question No: 3 Marks: 10 Show the complete timing diagram for the 5 stage synchronous binary counter. HIGH J 0 FF0 LSB Q 0 J 1 Q 1 J 2 Q 2 J 3 Q 3 J 4 Q 4 C C C C C K 0 K 1 K 2 K 3 K 4 CLK Question No: 4 Marks: 10 3

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